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copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 february, 2007 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/24-lane versatile pci express switch data book version 1.5 february 2007 website www.plxtech.com technical support www.plxtech.com/support/ phone 800 759-3735 408 774-9060 fax 408 774-2169
copyright information copyright ? 2006 ? 2007 plx technology, inc. all rights reserved. the information in this document is proprietary and confidential to plx technology no part of this document may be reproduced in any form or by any means or used to make any deriva tive work (such as translation, transformation, or adaptation) without written permission from plx technology. plx technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. while the information contained herein is believed to be accurate, such in formation is preliminar y, and no representations or warranties of accuracy or completeness are made. in no event will plx technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. plx technology may make improvemen ts or changes in the product(s) and/or the program(s) described in this documentation at any time. plx technology retains the right to make changes to this product at any time, without notice. products may have minor variations to this publication, known as errata. plx technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of plx technology, inc. products. plx technology and the plx logo are registered tr ademarks and expresslane is a trademark of plx technology, inc. pci express is a trademark of the pci special interest group (pci-sig). all product names are trademarks, re gistered trademarks, or service ma rks of their respective owners. order number: 8524-sil-db-p1-1.5 data book plx technology, inc. ii expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5
february, 2007 revision history expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book iii copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 revision history version date description of changes 1.0 january, 2006 production release, silicon revision bb. includes jtag, power, and ordering in formation for silicon revision aa. includes two package types: ? 35 x 35 mm 680-ball ehbga (aa/bb) 31 x 31 mm 644-ball pbga (bb) all information pertains to aa and bb devices, unless i ndicated otherwise as pex 8524aa or pex 8524bb. 1.1 march, 2006 changed ehbga to plastic bga / pbga section 12.1.2.2, ? intelligent adapter mode nt port reset ? ? changed ?1 ms? to ?1 s? in second paragraph register 11-8, offset 1ch [31] ? corrected cross-re ference to indicate the parity error response enable bit register 11-49, offset 1cch [13] ? corrected value of 1 to indicate > 8 corrected table 17-1 title to indicate field value of 10b miscellaneous chan ges for readability 1.2 june, 2006 changed data book title to include reference to both devices, pex 8524v and pex 8524, and clarified differences betw een the two, and added missing data related to one or the other, as appropriate, particularly in chapter 17, ?t estability and debug,? and chapter 18, ?electrical specifications? removed references to pex 8524aa (silicon revision aa exists only for pex 8524v) removed references to silicon revision ba for pex 8524v and pex 8524 device id ? corrected 35 x 35 (680-ba ll) package device id to be 8532h chapter 2 ? replaced illustrations figure 3-1 and 3-2 ? clarified view as ?see-through top view? table 3-11 ? corrected locations for 644- ball package (pex_petp29 is at b28, pex_perp27 is at d24, a nd pex_pern27 is at e24) figure 4-7 ? replaced illustration tables 4-1 and 5-3 ? updated to indica te that ports 8 and 9 (value of 1h) can be combined to create a x16 port section 5.1.3.1 ? changed ? upstream and downstream st ations? to ?upstream and downstream ports ? section 5.2.5, ?reset and clock initialization timing? ? created new heading, to include table and figure table 8-1 ? moved to ?ram and queue size? section figure 9-3 ? corrected hp_perst# signal to be high chapter 11, register offset 1d0h ? changed ? reserved ? reference to ? factory test only ? section 12.4 ? changed ?upstream port? reference to ?downstream ports? chapters 15 and 16 ? changed ?correspond ing port? references to appropriate nt port interface section 17.1.7 ? removed reference to reserved registers for station 1 tables 17-3, 17-4, and 17-5 ? merged jtag idcode content into a single table, table 17-3 tables 17-3 ? added pex 8524v cont ent; added missing pex 8524 jtag idcode binary part number and changed hex part number figure 19-2 ? rearranged drawing so it can be viewed without turning page appendix b ? updated product ordering tables miscellaneous chan ges for readability 1.3 august, 2006 miscellaneous chan ges, corrections, and enhancem ents throughout the data book.
data book plx technology, inc. iv expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 1.4 january, 2007 rewrote chapter 18, ?electrical specifications.? updated rdk ordering inform ation in appendix b, ?general information.? 1.5 february, 2007 production release, silicon revision bc. miscellaneous changes, corrections, and enhancements throughout the data book. moved table a-2 content into table a-1. version date description of changes
february, 2007 preface expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book v copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 preface the information contained in this data book is subj ect to change without notice. this plx data book is updated periodically as new information is made available. this data book documents information for the pex 8524v, silicon revisions aa, bb, and bc, and pex 8524, silicon revisions bb and bc. the informa tion provided pertains to all silicon revisions, unless specified otherwise. note: throughout this data book, unless specified otherwise, ?pex 8524? is used to indicate pex 8524v and pex 8524. audience this data book provides the functional detail s of plx technology?s expresslane pex 8524vaa/bb/ bc and pex 8524bb/bc 6-port/24-lane versatile pci express sw itches, for hardware designers and software/firmware engineers. supplemental documentation this data book assumes that the reader is familiar with the following documents: plx technology, inc. (plx) 870 w maude avenue, sunnyvale, ca 94085 tel: 800 759-3735 (domestic only) or 408 774-9060, fax: 408 774-2169, www.plxtech.com ? pex 85xx eeprom ? pex 8532/8524/8516 design note ? pex 8524 errata the plx pex 8524 toolbox includes other pex 8524 documentation as well. pci special interest group (pci-sig) 3855 sw 153rd drive, beaverton, or 97006 usa tel: 503 619-0569, fax: 503 644-6708, www.pcisig.com ? pci local bus specification, revision 2.3 ? pci bus power management interface specification, revision 1.1 ? pci to pci bridge architecture specification, revision 1.1 ? pci hot plug specification, revision 1.1 ? pci standard hot plug controller and subsystem specification, revision 1.0 ? pci express base specification, revision 1.0a ? pci express card electromechanical (cem) specification, revision 1.0a ? pci express architecture pci express jitter and ber white paper, revision 1.0 the institute of electrical a nd electronics engineers, inc. 445 hoes lane, piscataway, nj 08854-4141 usa tel: 800 701-4333 (domestic only) or 732 981-0060, fax: 732 981-9667, www.ieee.org ? ieee standard 1149.1-1990, ieee standard test access port and boundary-scan architecture, 1990 ? ieee standard 1149.1a-1993, ieee standard test access port and boundary-scan architecture ? ieee standard 1149.1-1994, specificati ons for vendor-specific extensions ? ieee standard 1149.6-2003, ieee standard test access port and boundary-scan architecture extensions
data book plx technology, inc. vi expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: in this data book, shortened titles are associated with the previously listed documents. the following table lists these abbreviations. terms and abbreviations the following table lists common terms and abbreviations used in this data book. terms and abbreviations defined in the pci express base r1.0a are not included in this table. abbreviation document pci r2.3 pci local bus specification, revision 2.3 pci power mgmt. r1.1 pci bus power manageme nt interface specifi cation, revision 1.1 pci-to-pci bridge r1.1 pci to pci bridge architecture specification, revision 1.1 hot plug r1.1 pci hot plug specification, revision 1.1 pci standard hot plug controller and subsystem r1.0 pci standard hot plug controller and subsystem specification, revision 1.0 pci express base r1.0a pci express base specification, revision 1.0a pci express cem r1.0a pci express card electr omechanical (cem) specifi cation, revision 1.0a ieee standard 1149.1-1990 ieee standard test access po rt and boundary-scan architecture ieee standard 1149.6-2003 ieee standard 1149.6-2003, ieee standard test access port and boundary-scan archit ecture extensions terms and abbreviations definitions amcam address mapping cam that determ ines a memory request route. contains mirror copies of the pci-to-pci bridges memory base and limit registers in the switch. busnocam bus number mapping cam that de termines the completion route. contains mirror copies of the pci-to-pci bridges secondary bus-number and subordinate bus-number registers in the switch. cam content addressable memory. csrs configuration space registers. downstream station a station that contains only downstream ports. egress queue egress ? outgoing traffic from chip egress queue ? egress que uing/scheduling mechanism gpio general-purpose input/output. ingress queue ingress ? incoming traffic to chip ingress queue ? ingress que uing/scheduling mechanism ioamcam i/o address mapping cam that de termines an i/o request rout e. contains mirror copies of the pci-to-pci bridges i/o base and limit registers in the switch. lane lanes are comprised of a bi-directional pa ir of differential pc i express i/o signals. link interface primary side of the nt port, connects to extern al device pins. the secondary side of the nt port is referred to as the nt port virtual interface , and connects to the internal virtual pci express interface. local reference to pci express attributes ( such as , credits) that belong to the pci express station. non-transparent a bridging technique used in the pci express sw itch to isolate memory spaces by presenting the processor as an endpoint rath er than another memory system.
february, 2007 terms and abbreviations expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book vii copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 pci express station a functional unit that provides the pci expres s conforming system interface. includes the serializer and de-serializer (s erdes) hardware interface modul es and pci express interface, which provides the physical layer, data link layer, and tran saction layer logic. phy physical layer. port ports are a collection of lanes configured at startup which contain the functional logic and memory resources to communicate with li ke resources in other pci express devices. prbs pseudo-random bit sequence. qos quality of service. ras reliability, availability, and serviceability. rohs restrictions on the use of certain hazardous substances (rohs) directive. rr round-robin scheduling. serdes serializer/de-serializer. a high-speed differential-signa ling parallel-to-serial and serial-to-parallel conversion l ogic attached to lane pads. tc traffic class. tdm time division multiplexing. tlc transaction layer control. the module pe rforming pci express transaction layer functions. tlp transaction layer packet. pci-expre ss packet formation and organization. transparent refers to standard pci expre ss upstream-to-downstream routing protocol. upstream station upstream station. contains th e component?s upstream port. an upstream station can contain downstream ports. vc virtual channel. virtual interface secondary side of the nt port, connects to the intern al virtual pci express interface. wrr weighted round-robin scheduling. terms and abbreviations definitions
data book plx technology, inc. viii expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 data book notations and conventions notation / convention description blue text indicates that the text is hyperlinked to its descript ion elsewhere in the data book. left-click the blue text to learn more about the hyperlinked information. this format is often used for register names, register bit and field names, register offsets, chapter and section titles, figures, and tables. pex_xxxp[15:0] when the signal name appears in all caps, with the primary port description listed first, field [15:0] in dicates the number of signal balls/pads assigned to that port. the lowercase ?p = positive? or ?n = negative? suffix indicates the differential pair of si gnal, which are always used together. # = active-low signals unless specified otherwise, active-low signals are identified by a ?#? appended to the term ( for example , pex_perst#). program/code samples monospace font ( program or code samples ) is used to identify code samples or programming references. these code samples are case-sensitive, unless specified otherwise. command_done interrupt format. command/status register names. parity error detected register parameter [field] or control function. upper base address[31:16] specific function in 32-bit register bounded by bits [31:16]. number multipliers k = 1,000 (10 3 ) is generally used with frequency response. k = 1,024 (2 10 ) is used for memory size references. kb = 1,024 bytes. m = meg. = 1,000,000 when referring to frequency (decimal notation) = 1,048,576 when referring to me mory sizes (binary notation) 1fh h = suffix which identifies hex values. each prefix term is equivalent to a 4-bit binary value (nibble). legal prefix terms are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, a, b, c, d, e, f. 1010b b = suffix which identifies binary notation ( for example , 01b, 010b, 1010b, and so forth). not used with single-digit values of 0 or 1. 0 through 9 decimal numbers, or single binary numbers. byte eight bits ? abbreviated to ?b? ( for example , 4b = 4 bytes) lsb least-significant byte. lsb least-significant bit. msb most-significant byte. msb most-significant bit. dword dword (32 bits) is the primar y register size in these devices. reserved do not modify reserved bits and words. unless specified otherwise, these bits read as 0 and must be written as 0.
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book ix copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 contents chapter 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 lane configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 chapter 2 pex 8524 applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 multi-purpose and feature-rich pci express switch . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.1 end-to-end packet integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.2 pci express switch non-transparent bridging (ntb) . . . . . . . . . . . . . . . . . . . . . . 5 2.1.3 two virtual channels (vcs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1.4 low power with granular serdes control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.5 flexible port-width configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.6 hot plug in high- availability applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.7 fully compliant power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 host-centric fan-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.2 peer-to-peer communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.3 graphics fan-out switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.4 dual-host model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.5 dual-fabric model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.6 switch-fabric module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.7 pci express port expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.8 adapter board aggregation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2.9 intelligent adapter board usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 software usage model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.1 system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.2 interrupt sources and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chapter 3 signal ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 internal pull-up resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 signal ball descriptions ? pex 8524v, 680-ball pbga . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.1 pci express signals ? 680-ball pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.4.2 hot plug signals ? 680-ball pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.4.3 serial eeprom signals ? 680-ba ll pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.4.4 strapping signals ? 680-ball pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.4.5 jtag interface signals ? 680-ball pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.4.6 no connect signals ? 680-ball pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.4.7 power and ground signals ? 680-ball pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.5 signal ball descriptions ? pex 8524, 644-ball pbga . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.5.1 pci express signals ? 644-ball pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.5.2 hot plug signals ? 644-ball pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.5.3 serial eeprom signals ? 644-ba ll pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.5.4 strapping signals ? 644-ball pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.5.5 jtag interface signals ? 644-ball pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5.6 no connect signals ? 644-ball pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.5.7 power and ground signals ? 644-ball pbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
contents plx technology, inc. x expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port /24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.6 ball assignments by number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.7 pex 8524 physical layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 chapter 4 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 7 4.1 pex 8524 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.1.1 ingress and egress functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 4.1.2 station and port functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.1.2.1 port combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 4.1.2.2 port numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 4.2 pci-compatible software model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 4.2.1 system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.2.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.2.2.1 interrupt sources or events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.2.2.2 intx switch mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.3 pci express station functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 4.3.1 pex 8524 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3.1.1 physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 4.3.1.2 data link layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.3.1.3 transaction layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.3.1.4 virtual channels and traffic classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.3.1.5 non-blocking crossbar switch architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 99 4.3.2 relaxed ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.3.2.1 pex 8524 relaxed ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.3.2.2 pex 8524 relaxed completion ordering ? silicon revisions bb/bc only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.3.2.3 no snoop enable ? silicon revisions bb/bc only . . . . . . . . . . . . . . . . . . . 101 4.4 non-transparent bridging implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.4.1 intelligent adapter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.4.2 dual-host mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.4.2.1 host-failover application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 chapter 5 reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5 5.1 reset overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.1.1 cold reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.1.2 warm reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.1.3 hot reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.1.3.1 hot reset propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 5.1.3.2 hot reset disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.1.4 secondary bus reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.2 initialization procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.2.1 default port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.2.2 default register initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 5.2.3 serial eeprom initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 5.2.3.1 configuration data download . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.3 pci express configuration, control, and status registers . . . . . . . . . . . . . . . . . . . . 111 5.3.1 selecting conf iguration values using serial eeprom . . . . . . . . . . . . . . . . . . . 112 5.3.2 selecting upstream port using serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . 112 5.3.3 setting port configuration us ing serial eeprom . . . . . . . . . . . . . . . . . . . . . . . 113 5.3.4 power management parameters using serial eeprom . . . . . . . . . . . . . . . . . . 114 5.3.5 message signaled in terrupt capability using serial eeprom . . . . . . . . . . . . . . 114 5.3.6 pci express capability using serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5.3.6.1 configuring hot plug controller slot power-up sequence features with serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
february, 2007 plx technology, inc. expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book xi copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 5.3.7 device serial number ex tended capability using serial eeprom . . . . . . . . . . 114 5.3.8 power budgeting extended capability using serial eeprom . . . . . . . . . . . . . . 114 5.3.9 virtual channel ex tended capability using serial eeprom . . . . . . . . . . . . . . . 114 5.3.10 advanced error r eporting capability using serial eeprom . . . . . . . . . . . . . . 114 5.3.11 plx-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 5.3.12 reset and clock initialization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 chapter 6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.1 interrupt support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 6.1.1 pex 8524 interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.2 intx emulation support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.2.1 intx-type interrupt message remapping and collapsing . . . . . . . . . . . . . . . . . 119 6.3 message signaled interrupt (msi) support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.3.1 msi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.3.2 msi capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 chapter 7 software architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.1 pex 8524 software model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.2 configuration mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.2.1 software configuration and routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.3 sample configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7.3.1 switch device number assignment example . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.3.1.1 configuration register programming sequence . . . . . . . . . . . . . . . . . . . . . 127 7.3.1.2 sample pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.3.1.3 sample packet transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 7.3.2 using base address registers (bars) to access registers . . . . . . . . . . . . . . . 129 7.3.2.1 transparent mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7.3.2.2 non-transparent mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.4 interrupt support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 7.5 hot plug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 chapter 8 performance metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 8.2 non-blocking switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 8.2.1 queuing topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 8.2.2 port-to-station aggregation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.2.3 ram and queue size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8.3 quality of service (qos) support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8.3.1 virtual channel (vc) support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 8.3.2 packet arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 8.3.2.1 source scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 8.3.2.2 high-priority virtual channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 8.3.2.3 plx-specific relaxed ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8.3.2.4 internal fabric backpressure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 8.3.2.5 egress scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 8.4 throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.4.1 theoretical upper limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.4.1.1 physical layer overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.4.1.2 data link layer overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.4.1.3 transaction layer overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 8.4.1.4 pci express efficiency upper bound summary . . . . . . . . . . . . . . . . . . . . . 143 8.4.2 single-stream throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8.4.2.1 ingress side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8.4.2.2 egress side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
contents plx technology, inc. xii expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8.4.3 multiple stream throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.4.3.1 enable plx-specific relaxed ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.4.3.2 avoid hot spots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.4.4 throughput and packet size relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 8.4.5 data link layer considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.4.5.1 arbitration between dllp and tlp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.4.5.2 dllp ack frequency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 8.4.5.3 dllp updatefc frequency control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 8.5 latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8.5.1 queuing effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8.5.2 time division multiplex effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 8.5.3 high-priority packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8.5.4 smaller size packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 8.5.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 chapter 9 hot plug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 53 9.1 hot plug purpose and capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 9.1.1 hot plug controller capa bilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 9.1.2 hot plug port external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 9.1.3 hot plug output signal states for disabled hot plug slots . . . . . . . . . . . . . . . . . 157 9.2 pci express capability registers fo r hot plug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 9.3 hot plug interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 9.4 hot plug controller power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 9.4.1 slot power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 9.4.1.1 configuring hot plug controller slot power-up sequence features with serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 9.4.1.2 slot power-up sequencing when power controller present bit is set . . . 160 9.4.1.3 hp_perstx# (reset) and hp_pwrledx# output power-up sequencing when power controller present bit is clear . . . . . . . . . . . . . 163 9.4.1.4 disabling power-up hot plug output sequencing . . . . . . . . . . . . . . . . . . . . 164 9.4.2 slot power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 9.5 hot plug board insertion and removal process . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 chapter 10 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 10.1 power management capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 10.1.1 device power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 10.1.1.1 d0 state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 10.1.1.2 d3hot state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 10.1.1.3 d3cold state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 10.1.2 link power management state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 10.1.3 pex 8524 pci express power management support . . . . . . . . . . . . . . . . . . . 173 chapter 11 pex 8524 transparent mode port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.2 type 1 pex 8524 port register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.3 pex 8524 port register configuration and map . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.4 register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 11.4.1 pci r2.3 -compatible configuration mechanism . . . . . . . . . . . . . . . . . . . . . . . . 184 11.4.2 pci express enhanced configuration mechanism . . . . . . . . . . . . . . . . . . . . . . 185 11.4.3 plx-specific memory-mapped configuration mechanism . . . . . . . . . . . . . . . . 186 11.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 11.6 configuration header registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 11.7 power management capability register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 11.8 message signaled interrupt cap ability registers . . . . . . . . . . . . . . . . . . . . . . . . . . 207
february, 2007 plx technology, inc. expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book xiii copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.9 pci express capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 11.10 device serial number exten ded capability registers . . . . . . . . . . . . . . . . . . . . . . 226 11.11 power budgeting ex tended capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . 227 11.12 virtual channel extended capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 11.12.1 virtual channel arbitration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 11.13 plx-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 11.13.1 error checking and debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 11.13.2 physical layer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 11.13.3 cam routing registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 11.13.3.1 bus number cam registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 11.13.3.2 i/o cam registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 11.13.3.3 amcam (address-mapping cam) registers . . . . . . . . . . . . . . . . . . . . . . 277 11.13.4 ingress control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 11.13.5 i/o cam base and limit upper 16 bits registers . . . . . . . . . . . . . . . . . . . . . . 286 11.13.6 base address registers (bars) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 11.13.7 shadow virtual channel (vc) capability registers . . . . . . . . . . . . . . . . . . . . 294 11.13.8 ingress credit handler (inch) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 11.13.8.1 inch threshold port virtual channel registers . . . . . . . . . . . . . . . . . . . 306 11.13.9 ingress one-bit ecc error count register . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 11.13.10 relaxed completion ordering (ingress) register ? silicon revisions bb/bc only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 11.13.11 relaxed ordering mode (ingress) register . . . . . . . . . . . . . . . . . . . . . . . . . 311 11.13.12 internal credit handler (itch) vc&t threshold registers . . . . . . . . . . . . . 312 11.14 advanced error reporting capab ility registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 chapter 12 non-transparent (nt) bridging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 12.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 12.1.1 device type identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 12.1.2 non-transparent port (nt port) reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 12.1.2.1 fundamental rese t (pex_perst#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 12.1.2.2 intelligent adapter mode nt port reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 12.1.2.3 dual-host mode nt port reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 12.1.2.4 reset propagation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 12.1.3 scratchpad registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 12.1.4 doorbell registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 12.1.5 bar setup registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 12.1.5.1 nt port virtual interface bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 12.1.5.2 nt port link interface bars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 12.1.5.3 bar limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 12.1.6 address translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 12.1.6.1 direct address translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 12.1.6.2 lookup table-based address translation . . . . . . . . . . . . . . . . . . . . . . . . . 329 12.2 requester id translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 12.2.1 transaction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 12.2.2 transaction originating in local host domain . . . . . . . . . . . . . . . . . . . . . . . . . 333 12.2.3 system host domain transaction originating . . . . . . . . . . . . . . . . . . . . . . . . . 335 12.3 nt port power management handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 12.3.1 active-state power management (aspm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 12.3.2 pci-pm and pme turn off support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 12.3.3 message generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 12.4 nt hot plug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 12.4.1 hot plug sequence during host-failover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
contents plx technology, inc. xiv expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 13 nt port interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 13.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 13.2 doorbell interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 13.3 doorbell registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 chapter 14 non-transparent bridging software architectu re . . . . . . . . . . . . . . . . . . . . . . .343 14.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 14.2 system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 14.2.1 pex 8524 intelligent adapte r mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 14.2.2 sample pex 8524 configuration steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 14.2.3 pex 8524 dual-host mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 14.2.4 host-failover application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 14.3 data transfer through nt port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 chapter 15 nt port virtual interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351 15.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 15.2 register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 15.2.1 pci express base r1.0a configuration mechanism . . . . . . . . . . . . . . . . . . . . . 353 15.2.1.1 pci r2.3 -compatible configuration mechanism . . . . . . . . . . . . . . . . . . . . . 353 15.2.1.2 pci express enhanced configuration mechanism . . . . . . . . . . . . . . . . . . . 354 15.2.2 plx-specific memory-mapped configuration mechanism . . . . . . . . . . . . . . . . 355 15.2.3 plx-specific i/o-mapped configuration mechanism . . . . . . . . . . . . . . . . . . . . 356 15.2.4 plx-specific cursor mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 15.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 15.4 configuration header registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 15.5 power management capability register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 15.6 message signaled interrupt cap ability registers . . . . . . . . . . . . . . . . . . . . . . . . . . 368 15.7 pci express capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 15.8 nt port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 15.8.1 nt port virtual interface irq doorbell registers . . . . . . . . . . . . . . . . . . . . . . . 375 15.8.2 nt port scratchpad (mailbox) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 15.8.3 nt port virtual interface bar setup registers . . . . . . . . . . . . . . . . . . . . . . . . . 381 15.8.4 nt port cursor mechanism control registers . . . . . . . . . . . . . . . . . . . . . . . . . 386 15.9 device serial number extended capability registers . . . . . . . . . . . . . . . . . . . . . . . 387 15.10 power budgeting ex tended capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . 387 15.11 virtual channel extended capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 15.12 plx-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 15.12.1 error checking and debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 15.12.2 nt port virtual interface physical layer registers . . . . . . . . . . . . . . . . . . . . . 393 15.12.3 nt port virtual interface ingress control register . . . . . . . . . . . . . . . . . . . . . 394 15.13 pex 8524 non-transparent bridging-specific registers . . . . . . . . . . . . . . . . . . . . 397 15.13.1 nt port virtual interface memory address translation and bar limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 15.13.2 nt port virtual interface lookup table-based address translation registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 15.13.3 nt port link interface vc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 15.13.4 nt port virtual interface base address registers (bars) and bar setup registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 15.13.5 nt port virtual interface send lookup table entry registers . . . . . . . . . . . . 412 15.13.6 nt port link interface capture and virtual interface control registers . . . . . 413 15.14 advanced error reporting capab ility registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
february, 2007 plx technology, inc. expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book xv copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 16 nt port link interface registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 16.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 16.2 register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 16.2.1 pci express base r1.0a configuration mechanism . . . . . . . . . . . . . . . . . . . . . 417 16.2.1.1 pci r2.3 -compatible configuration mechanism . . . . . . . . . . . . . . . . . . . . . 417 16.2.1.2 pci express enhanced configuration mechanism . . . . . . . . . . . . . . . . . . 418 16.2.2 plx-specific memory-mapped configuration mechanism . . . . . . . . . . . . . . . . 419 16.2.3 plx-specific i/o-mapped configuration mechanism . . . . . . . . . . . . . . . . . . . . 420 16.2.4 plx-specific cursor mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 16.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 16.4 configuration header registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 16.5 power management capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 16.6 message signaled interrupt cap ability registers . . . . . . . . . . . . . . . . . . . . . . . . . . 432 16.7 pci express capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 16.8 nt port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 16.8.1 nt port link interface interrupt request (irq) doorbell registers . . . . . . . . . 440 16.8.2 nt port scratchpad (mailbox) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 16.8.3 nt port link interface bar setup registers . . . . . . . . . . . . . . . . . . . . . . . . . . 443 16.8.4 nt port cursor mechanism control registers . . . . . . . . . . . . . . . . . . . . . . . . . 446 16.9 device serial number extended capability registers . . . . . . . . . . . . . . . . . . . . . . . 447 16.10 power budgeting ex tended capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . 447 16.11 virtual channel extended capability registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 16.12 plx-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 16.12.1 error checking and debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 16.12.2 nt port link interface physical layer registers . . . . . . . . . . . . . . . . . . . . . . . 453 16.12.3 nt port link interface ingress control register . . . . . . . . . . . . . . . . . . . . . . . 455 16.13 pex 8524 non-transparent bridging-specific registers . . . . . . . . . . . . . . . . . . . . 458 16.13.1 nt port link interface memory address translation and limit bar registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 16.13.2 nt port link interface receive lookup table entry registers . . . . . . . . . . . . 462 16.14 advanced error reporting capab ility registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 chapter 17 test and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 17.1 physical layer loop-back operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 17.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 17.1.1.1 loop-back test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 17.1.2 internal loop-back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 17.1.3 analog loop-back master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 17.1.4 digital loop-back master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 17.1.5 analog loop-back slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 17.1.6 digital loop-back slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 17.1.7 using the diagnostic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 17.2 pseudo-random and bit-pattern generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 17.3 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 17.3.1 ieee 1149.1 and 1149.6 test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 17.3.2 jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 17.3.3 jtag boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 17.3.4 jtag reset input signal jtag_trst# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 17.4 lane good status leds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
contents plx technology, inc. xvi expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 18 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 1 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 18.2 power-up/power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 18.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 18.4 power characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 18.5 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 18.6 i/o interface signal groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485 18.7 transmit drive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 18.7.1 drive current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 18.7.2 transmit equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 18.7.3 transmit termination adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 18.8 receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 18.8.1 receive equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 18.8.2 receive termination adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 chapter 19 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .495 19.1 pex 8524 package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 19.2 pex 8524 mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 19.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 appendix a serial eeprom memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .501 a.1 serial eeprom memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 appendix b general information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 9 b.1 product ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 b.2 united states and international representatives, and distributors . . . . . . . . . . . . . . 520 b.3 technical support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book xvii copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 registers 11-1. 00h product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 11-2. 04h command/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 11-3. 08h class code and revision id. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 11-4. 0ch miscellaneous control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193 11-5. 10h base address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 11-6. 14h base address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194 11-7. 18h bus number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 11-8. 1ch secondary status, i/o limit, and i/o base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 11-9. 20h memory base and limit address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198 11-10. 24h prefetchable memory base and limit address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 11-11. 28h prefetchable memory upper base address[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 11-12. 2ch prefetchable memory upper limit address[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 11-13. 30h i/o base address[31:16] and i/o limit address[31:16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 11-14. 34h capabilities pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 11-15. 38h expansion rom base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 11-16. 3ch bridge control and interrupt signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 11-17. 40h power management capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 11-18. 44h power management status and control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 11-19. 48h message signaled interrupt capabili ty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 11-20. 4ch message address[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 11-21. 50h message upper address[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 11-22. 54h message data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 11-23. 68h pci express capability list and capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 11-24. 6ch device capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 11-25. 70h device status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 11-26. 74h link capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 11-27. 78h link status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216 11-28. 7ch slot capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 11-29. 80h slot status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220 11-30. 100h device serial number extended capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 11-31. 104h serial number (lower dw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 11-32. 108h serial number (higher dw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 11-33. 138h power budgeting extended capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 11-34. 13ch data select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 11-35. 140h power budgeting data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 11-36. 144h power budget capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 11-37. 148h virtual channel extended capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 11-38. 14ch port vc capability 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 11-39. 150h port vc capability 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230 11-40. 154h port vc status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 11-41. 158h vc0 resource capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 11-42. 15ch vc0 resource control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 11-43. 160h vc0 resource status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 11-44. 164h vc1 resource capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 11-45. 168h vc1 resource control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 11-46. 16ch vc1 resource status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 11-47. 1b8h - 1c4h vc arbitration table phase n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 11-48. 1c8h ecc check disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 11-49. 1cch error handler 32-bit error status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 11-50. 1d0h error handler 32-bit error mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 11-51. 1dch debug control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
registers plx technology, inc. xviii expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11-52. 1e0h power management hot plug user configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 11-53. 1e4h egress control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 11-54. 1e8h bad tlp count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 11-55. 1ech bad dllp count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 11-56. 1f0h plx-specific relaxed ordering enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 11-57. 1f4h software-controlled lane status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 11-58. 1f8h ack transmission latency limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 11-59. 210h phy user test pattern 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 11-60. 214h phy user test pattern 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 11-61. 218h phy user test pattern 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 11-62. 21ch phy user test pattern 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 11-63. 220h physical layer command and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 11-64. 224h port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 11-65. 228h physical layer test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 11-66. 22ch physical layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 11-67. 230h physical layer port command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 11-68. 234h skip ordered-set interval. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 11-69. 238h quad 0 serdes diagnostic data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 11-70. 23ch quad 1 serdes diagnostic data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 11-71. 240h quad 2 serdes diagnostic data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 11-72. 244h quad 3 serdes diagnostic data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 11-73. 248h serdes nominal drive current select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 11-74. 24ch serdes drive current level select 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 11-75. 250h serdes drive current level select 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 11-76. 254h serdes drive equalization level select 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 11-77. 258h serdes drive equalization level select 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 11-78. 260h serial eeprom status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 11-79. 264h serial eeprom buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 11-80. 2c8h bus number cam 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 11-81. 2cch bus number cam 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 11-82. 2e8h bus number cam 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 11-83. 2ech bus number cam 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 11-84. 2f0h bus number cam 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 11-85. 2f4h bus number cam 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 11-86. 308h i/o cam_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 11-87. 30ah i/o cam_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 11-88. 318h i/o cam_8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 11-89. 31ah i/o cam_9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 11-90. 31ch i/o cam_10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 11-91. 31eh i/o cam_11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 11-92. 348h amcam_0 memory limit and base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 11-93. 34ch amcam_0 prefetchable memory limit and base[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 11-94. 350h amcam_0 prefetchable memory base[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 11-95. 354h amcam_0 prefetchable memory limit[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 11-96. 358h amcam_1 memory limit and base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 11-97. 35ch amcam_1 prefetchable memory limit and base[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 11-98. 360h amcam_1 prefetchable memory base[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 11-99. 364h amcam_1 prefetchable memory limit[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 11-100. 3c8h amcam_8 memory limit and base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 11-101. 3cch amcam_8 prefetchable memory limit and base[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 11-102. 3d0h amcam_8 prefetchable memory base[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 11-103. 3d4h amcam_8 prefetchable memory limit[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 11-104. 3d8h amcam_9 memory limit and base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 11-105. 3dch amcam_9 prefetchable memory limit and base[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 11-106. 3e0h amcam_9 prefetchable memory base[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 11-107. 3e4h amcam_9 prefetchable memory limit[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 11-108. 3e8h amcam_10 memory limit and base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 11-109. 3ech amcam_10 prefetchable limit and memory base[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
february, 2007 plx technology, inc. expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book xix copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11-110. 3f0h amcam_10 prefetchable memory base[63:32]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 11-111. 3f4h amcam_10 prefetchable memory limit[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 11-112. 3f8h amcam_11 memory limit and base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 11-113. 3fch amcam_11 prefetchable limit and memory base[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 11-114. 400h amcam_11 prefetchable memory base[63:32]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 11-115. 404h amcam_11 prefetchable memory limit[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 11-116. 660h ingress control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 11-117. 668h ingress port enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 11-118. 680h i/ocam_0 upper port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 11-119. 684h i/ocam_1 upper port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 11-120. 6a0h i/ocam_8 upper port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 11-121. 6a4h i/ocam_9 upper port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 11-122. 6a8h i/ocam_10 upper port 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 11-123. 6ach i/ocam_11 upper port 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 11-124. 6c0h bar0 for port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 11-125. 6c4h bar1 for port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 11-126. 6c8h bar0 for port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 11-127. 6cch bar1 for port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 11-128. 700h bar0 for port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 11-129. 704h bar1 for port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 11-130. 708h bar0 for port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 11-131. 70ch bar1 for port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291 11-132. 710h bar0 for port 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 11-133. 714h bar1 for port 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 11-134. 718h bar0 for port 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 11-135. 71ch bar1 for port 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293 11-136. 740h vc0 port 0 capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 11-137. 744h vc1 port 0 capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295 11-138. 748h vc0 port 1 capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 11-139. 74ch vc1 port 1 capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 11-140. 780h vc0 port 8 capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 11-141. 784h vc1 port 8 capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 11-142. 788h vc0 port 9 capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 11-143. 78ch vc1 port 9 capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 11-144. 790h vc0 port 10 capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 11-145. 794h vc1 port 10 capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 11-146. 798h vc0 port 11 capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 11-147. 79ch vc1 port 11 capability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 11-148. 840h port 0 vc capability_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 11-149. 844h port 1 vc capability_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 11-150. 860h port 8 vc capability_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 11-151. 864h port 9 vc capability_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 11-152. 868h port 10 vc capability_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 11-153. 86ch port 11 vc capability_1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302 11-154. 9f4h inch fc update pending timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304 11-155. 9fch inch mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 11-156. a00h, a18h, a30h, a48h inch threshold port n vc0 posted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 6 11-157. a04h, a1ch, a34h, a4ch inch threshold port n vc0 non-po sted. . . . . . . . . . . . . . . . . . . . . . . . . . . .307 11-158. a08h, a20h, a38h, a50h inch threshold port n vc0 completion . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 11-159. a0ch, a24h, a3ch, a54h inch threshold port n vc1 posted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 11-160. a10h, a28h, a40h, a58h inch threshold port n vc1 non-posted . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 11-161. a14h, a2ch, a44h, a5ch inch threshold port n vc1 comple tion . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 11-162. be8h ingress one-bit ecc error count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 11-163. bech plx-specific relaxed completion ordering (ingress) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 11-164. bfch plx-specific relaxed ordering mode (ingress) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 11-165. c00h itch vc&t threshold_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 11-166. c04h itch vc&t threshold_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 11-167. c08h itch vc&t threshold_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
registers plx technology, inc. xx expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11-168. fb4h pci express enhanced capability header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 11-169. fb8h uncorrectable error status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 11-170. fbch uncorrectable error mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 11-171. fc0h uncorrectable error severity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 11-172. fc4h correctable error status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 11-173. fc8h correctable error mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 11-174. fcch advanced error capabilities and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 11-175. fd0h header log_0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 11-176. fd4h header log_1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 11-177. fd8h header log_2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 11-178. fdch header log_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 15-1. 00h product identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 15-2. 04h status/command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 15-3. 08h class code and revision id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 15-4. 0ch miscellaneous control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 15-5. 14h base address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 15-6. 18h base address 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 15-7. 1ch base address 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 15-8. 20h base address 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 15-9. 24h base address 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 15-10. 2ch subsystem id and subsystem vendor id. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 15-11. 34h new capabilities pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 15-12. 3ch interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 15-13. 40h power management capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 15-14. 44h power management status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 15-15. 68h pci express capability list and capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 15-16. 6ch device capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 15-17. 70h device status and control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 15-18. 74h link capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 15-19. 78h link status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 15-20. 90h set virtual interface irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 15-21. 94h clear virtual interface irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 15-22. 98h set virtual interface irq mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 15-23. 9ch clear virtual interface irq mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 15-24. a0h set link interface irq. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 15-25. a4h clear link interface irq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 15-26. a8h set link interface irq mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 15-27. ach clear link interface irq mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 15-28. d0h nt port virtual interface bar1 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 15-29. d4h nt port virtual interface bar2 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 15-30. d8h nt port virtual interface bar3 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 15-31. dch nt port virtual interface bar4/5 setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 15-32. e0h nt port virtual interface bar5 setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 15-33. f8h configuration address window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 15-34. fch configuration data window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 15-35. 1cch error handler 32-bit error status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 15-36. 1d0h error handler 32-bit error mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 15-37. 1e4h egress nt port virtual interface control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 15-38. 1f8h ack transmission latency limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 15-39. 660h ingress control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 15-40. c3ch memory bar2 address translation[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 15-41. c44h memory bar4/5 address translation[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 15-42. c48h memory bar4/5 address translation[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 15-43. c4ch memory bar2 limit[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 15-44. c54h memory bar4/5 limit[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 15-45. c58h memory bar5 limit[63:32]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 15-46. c5ch - d58h base-translation lookup table entry_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 15-47. d5ch nt link interface vc0 resource control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
february, 2007 plx technology, inc. expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book xxi copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15-48. d60h nt link interface vc1 resource control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403 15-49. d64h nt link interface vc capability 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403 15-50. d6ch bar1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405 15-51. d70h bar2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405 15-52. d74h bar3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406 15-53. d78h bar4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407 15-54. d7ch bar5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407 15-55. d80h bar1 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408 15-56. d84h bar2 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408 15-57. d88h bar3 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409 15-58. d8ch bar4 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410 15-59. d90h bar5 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .411 15-60. d94h - db0h virtual interface send lookup table entry_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412 15-61. df4h nt port link interface capture bus and device number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3 15-62. df8h nt port virtual interface control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413 16-1. 00h product identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421 16-2. 04h status/command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 16-3. 08h class code and revision id. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424 16-4. 0ch miscellaneous control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425 16-5. 10h base address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425 16-6. 14h base address 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 16-7. 18h base address 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 16-8. 1ch base address 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 16-9. 20h base address 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427 16-10. 24h base address 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427 16-11. 2ch subsystem id and subsystem vendor id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427 16-12. 30h expansion rom base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428 16-13. 34h new capabilities pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429 16-14. 3ch interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429 16-15. 40h power management capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430 16-16. 44h power management status and control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431 16-17. 68h pci express capability list and capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .433 16-18. 6ch device capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .434 16-19. 70h device status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .435 16-20. 74h link capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .437 16-21. 78h link status and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .438 16-22. b0h nt port scratchpad_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441 16-23. b4h nt port scratchpad_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441 16-24. b8h nt port scratchpad_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441 16-25. bch nt port scratchpad_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441 16-26. c0h nt port scratchpad_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442 16-27. c4h nt port scratchpad_5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442 16-28. c8h nt port scratchpad_6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442 16-29. cch nt port scratchpad_7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442 16-30. e4h nt port link interface bar0/bar1 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443 16-31. e8h nt port link interface bar2/3 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444 16-32. ech nt port link interface bar3 setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .444 16-33. f0h nt port link interface bar4/5 setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .445 16-34. f4h nt port link interface bar5 setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .445 16-35. f8h configuration address window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .446 16-36. fch configuration data window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .446 16-37. 1cch error handler 32-bit error status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451 16-38. 1d0h error handler 32-bit error mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451 16-39. 1e4h egress nt port link interface control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .452 16-40. 1f8h ack transmission latency limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .452 16-41. 220h physical layer command and status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .454 16-42. 660h ingress control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .456 16-43. c3ch memory bar2/3 address translation[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .459
registers plx technology, inc. xxii expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16-44. c40h memory bar2/3 address translation[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 16-45. c44h memory bar4/5 address translation[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16-46. c48h memory bar4/5 address translation[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16-47. c4ch memory bar2/3 limit[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16-48. c50h memory bar2/3 limit[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 16-49. c54h memory bar4/5 limit[31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 16-50. c58h memory bar4/5 limit[63:32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 16-51. db4h - df0h link interface receive lookup table entry_n_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 63
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 1 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 1 introduction 1.1 features note: throughout this data book, unless specified otherwise, ?pex 8524? is used to indicate pex 8524v and pex 8524. plx technology?s expresslane tm pex 8524 pci express switch device supports the following features: high performance ? pex 8524 = 24 pci express lanes provide 120 gbps aggregate bandwidth [2.5 gbps/lane x 24 lanes x 2 (full duplex)] ? non-blocking internal crossbar architecture supports tlp bandwidth capacity of each x8 (station 0) and x16 (station 1) link ? maximum packet payload size of 256 bytes ? performance tuning flexible configuration ? pex 8524 = 24 pci express lanes, up to 6 ports ? up to 40 possible port configurations ? choice of width (number of lanes) per uniq ue port/link ? x1, x2, x4, or x8 (station 0) or x1, x2, x4, x8, or x16 (station 1) ? designate any port as the upstream port ? configure with strapping balls and/or serial eeprom ? lane reversal support pci express power management ? link power management states ? l0, l0s, l1, l2/l3 ready, and l3 ? device power management states ? d0 and d3hot quality of service (qos) ? all ports support two, full-featured virtual channels (vc0 and vc1) ? all ports support eight traffic class (tc) mapping, independent of other ports ? port arbitration ? hardware-fixed arbitration scheme ? virtual channel arbitration ? weighted round-robin (wrr) or hardware-fixed arbitration scheme non-transparent bridging ? program any one port as non-transparent ? enables dual-host, dual-fabri c, host-failover applications transaction forwarding with address translation reliability, availability, and serviceability (ras) features ? each downstream port includes a pci express hot plug controller ? upstream port supports hot plug as a client ? transaction layer packet digest support poison bit end-to-end cyclic redundancy check (ecrc)
introduction plx technology, inc. 2 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port /24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 ? advanced error reporting capability ? per-port diagnostics tlp errors crc errors ? all on-chip ram are ecc-protected ? serial eeprom content is crc-protected testability ? jtag support for dc package types ? pex 8524vaa/bb/bc ? 35-mm square, 680-ball pbga (plastic bga) package ? pex 8524bb/bc ? 31-mm square, 644-bal l pbga (plastic bga) package compliant to the following standards ? pci local bus specification, revision 2.3 (pci r2.3 ) ? pci bus power management interface specifi cation, revision 1.1 (pci power mgmt. r1.1 ) ? pci to pci bridge architecture specification, revision 1.1 (pci-to-pci bridge r1.1) ? pci hot plug specification, revision 1.1 (pci hot plug r1.1) ? pci standard hot plug controller and subsystem specification, revision 1.0 (pci standard hot plug controller and subsystem r1.0) ? pci express base specification, revision 1.0a (pci express base r1.0a ) ? pci express card electromechanical (cem) specification, revision 1.0a (pci express cem r1.0a ) ? ieee standard 1149.1-1990, ieee standard test access port and boundary-scan architecture, 1990 (i eee standard 1149.1-1990 ) ? ieee standard 1149.1a-1993, ieee standard test access port and boundary-scan architecture ? ieee standard 1149.1-1994, specificati ons for vendor-specific extensions ? ieee standard 1149.6-2003, ieee standard test access port and boundary-scan architecture extensions
february, 2007 overview expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 3 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 1.2 overview this data book describes the pex 8524, a fully n on-blocking, low-latency, low-cost, and low-power 6-port, 24-lane pci express switch. conforming to the pci express base r1.0a , the pex 8524 enables users to add scalable, high-bandwidth i/o to a wide variety of products, including servers, communication products, storage systems, router s, blade servers, and other embedded products. the pex 8524?s flexible hardware configuration and software programmability allow the switch to be tailored to suit a wide variety of applications. 1.3 lane configuration the pex 8524 switch is suitable for host-centric and peer-to-peer comm unication. the pex 8524 contains 24 pci express lanes and up to six ports. figure 1-1 illustrates the way in which the pex 8524 fl exible-lane conf iguration feature supports a variety of switch applications. figure 1-1 (a) illustrates a host-centric port configuration, where a wide pci express link is fanned out into smaller ports with different bandwidth requirements. figure 1-1 (b) illustrates backplane port configur ation, where the wide pci express port provides a high-bandwidth path to a host or a switch fabric from a la rge number of line cards with smaller ports. figure 1-1 (c) illustrates a 6-slot symmetric b ackplane, with x4 links traveli ng to each slot for peer-to-peer applications. figure 1-1. pex 8524 flexible-lane configuration
introduction plx technology, inc. 4 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port /24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 this page intentionally left blank.
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 5 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 2 pex 8524 applications 2.1 multi-purpose and feature-rich pci express switch the expresslane pex 8524 device offers pci expr ess switching capability, conforming to the pci express base r1.0a , enabling users to add scalable, high-bandwidth, non-blocking interconnection to a wide variety of applications including servers, storage systems, communications platforms, blade servers, and embedded-control products. the pex 8524 switch can be used as fan-out, aggregation, dual graphics, or peer-to-peer switching, and is equally well-suited for intelligent i/o module applications. 2.1.1 end-to-end packet integrity the pex 8524 provides end-to-end crc (ecrc) prot ection and poison-bit support to enable designs that require guaranteed error-free packet s. these features are optional in the pci express base r1.0a ; however, plx provides them across its entire expresslane switch product line. 2.1.2 pci express switch non- transparent bridging (ntb) the pex 8524 supports full non-transparent bridging (ntb) functionality to allow implementation of multi-host systems and intelligent i/o modules in applications such as communications, storage, and graphics fan-out. to ensure prompt product migration, non-transparency features are implemented in the same manner as conventional pci applications. non-transparent bridges allow sy stems to isolate memory domains by presenting the processor subsystem as an endpoint, rather than another memory system: base address registers (bars) are used to translate addresses doorbell registers are used to transmit in terrupts between the address domains scratchpad registers are accessible from both addr ess domains, to allow inter-processor communication 2.1.3 two virtual channels (vcs) the pex 8524 switch supports two full-featured vi rtual channels (vcs) and eight traffic classes (tcs). traffic-class mapping to port- specific virtual channels allows different mappings on different ports. in addition, this device offers user-selectable virtual channel arbitration algorithms to enable fine-tuning of quality of service (qos ), required for specific applications. the pex 8524 switch supports hardware-fixed and weighted round-robin arbitration schemes for two vcs. this allows qos fine-tuning, optimum buffer use, and efficient use of system bandwidth.
pex 8524 applications plx technology, inc. 6 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port /24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 2.1.4 low power with granular serdes control the pex 8524 provides low-power capability that is fully compliant with the pci express base r1.0a power management specifications. unused serdes can be disabled to reduce power consumption. the pex 8524 supports serdes output software control to allow power and signal strength optimization in a system. the plx serdes implementation supports four power levels ? off , low , typical , and high . the serdes block also supports loop-back modes and advanced error reporting, which enables efficient system debug and management. 2.1.5 flexible port-width configuration the lane width per port can be individually configured through auto-negotiation, hardware strapping, upstream software configuration, or an optional serial eeprom. the pex 8524 supports a large number of port configurations. for example , if the pex 8524 is used in a fan-out application (as illustrated in figure 2-2 ), the upstream port can be configured as x8, and the downstream ports can be configured as follows: four x4 ports two x8 ports or any other combination, provided that available lanes or ports are not exceeded for peer-to-peer applications, all six ports can be configured as x4 or x2, or a combination of the two. in port aggregation applications, four x2 or two x4 ports can be configured for aggregation into one x8 port in station 0, or x16 port in station 1. figure 2-1 illustrates the most common port configurations. each port supports lane reversal for system design flexibility. figure 2-1. common port width configurations
february, 2007 hot plug in high-availability applications expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 7 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 2.1.6 hot plug in high -availability applications hot plug capability allows replacement of hardwa re modules and maintenance performance without system power down. the pex 8524 hot plug capability and advanced er ror reporting features make the pex 8524 suitable for high-availability (ha) applicat ions. each downstream port includes a standard hot plug controller. if the pex 8524 is used in an a pplication where one or more of its downstream ports connects to pci express slots, the individual port hot plug controller is used to manage the hot plug event of its associated slot. additionally, the upstream port is a fully compliant hot plug client, and the pex 8524 can be used on hot-pluggable adapter board s, backplanes, and fabric modules. 2.1.7 fully compliant power management for applications that require power management, the pex 8524 supports link (l0, l0s, l1, l2/l3 ready, and l3) and device (d0 and d3hot) power management states, in compliance with the pci express base r1.0a power management specifications.
pex 8524 applications plx technology, inc. 8 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port /24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 2.2 applications suitable for host-centric and peer-t o-peer traffic patterns, the pex 8 524 can be configured for a wide variety of form factors and applications, as described in the sections that follow. 2.2.1 host-centric fan-out the pex 8524, with versatile symmetric or asymmetric lane configuration capability, allows application-specific tuning to a va riety of host-centric applications. figure 2-2 illustrates a typical server-based design, where the root complex provides a pci express link needing to be broken into a larger number of smaller ports for a variety of i/o functions with different bandwidth requirements. in this example, the pex 8524 contains one x8 upst ream port, and as many as five downstream ports. the downstream ports can be of differing widths, if required. figure 2-2 also illustrates various ways that the ports can be bridged to provide pci or pci-x, using expresslane pci express bridges ( such as , the plx pex 8114 or pex 8111). figure 2-2. fan-in/fan-out usage
february, 2007 peer-to-peer communication expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 9 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 almost all (non-x86-based) risc microprocessor manufacturers offer pci express interfaces. for enhanced connectivity, the pex 8524 can be directly c onnected to a processor to fan-out its pci express port to a larger number of ports, as illustrated in figure 2-3 . figure 2-3. powerpc/mips cpus fan-out 2.2.2 peer-to-peer communication figure 2-4 represents a pex 8524 backplane that provid es peer-to-peer data exchange for a large number of line cards, wherein the cpu/ host plays the management role. figure 2-4. peer-to-peer communication
pex 8524 applications plx technology, inc. 10 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 2.2.3 graphics fan-out switch the number and variety of pci express native-mode devices is rapidly growing. these devices, such as pci express graphics boards, are e xpected to rapidly become mainst ream. as that occurs, it becomes necessary to use a x8 port on the root complex device and fan it out to two x4 (or x8) ports for dual-graphic applications. root complex ( north bridge ) devices are availa ble with multiple pci express ports, which can be further expanded to c onnect to a larger number of i/os or to support dual-graphics, using the pex 8 524, as illustrated in figure 2-5 . figure 2-5. graphics fan-out
february, 2007 dual-host model expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 11 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 2.2.4 dual-host model the pex 8524 supports applications requiring dual-host, host-failover, and load-sharing applications through the non-transparency feature. figure 2-6 illustrates a dual-host system using an inte lligent adapter board. the primary cpu (on the right) is the active host ? it config ures and enumerates the system, and handles interrupts and error conditions. if the primary host ceas es proper operation, the secondar y host takes over the system. the pex 8524 can dynamically re-assign the upstream port (from primary to secondary) and the non-transparent port (from the secondary to the primary), and allow the sy stem to continue operation. dynamic swapping of the upstream and nt ports is supported on ports 0 and 8. figure 2-6. dual-host usage
pex 8524 applications plx technology, inc. 12 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 2.2.5 dual-fabric model high-performance communications, storage, and blade server systems often require more reliability than a dual-host system provides. for these high-avai lability systems, all single points of failure must be eliminated. the pex 8524 can offer this additional level of redundancy by linking two switch fabric boards in a dual-star topology. as illustrated in figure 2-7 , the host and fabric are on separate boards, and can be simultaneously active. the pex 8524 unique non-transparency feature is used to allow one fabric/host board to be the prim ary and the other the secondary. this approach is used to provide more than two active processing n odes. it is straightforward to create a generalized multi-processor system with smaller pex 8524 switches on each board in non-transparent mode (nt mode), and several pex 8524 fabric boards to provide the fabric backbone. figure 2-7. dual-host and fabric usage
february, 2007 switch-fabric module expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 13 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 2.2.6 switch-fabric module the pex 8524 can also be used in blad e server switch fabric applications. figure 2-8 illustrates use of the pex 8524 in a benes switch configuration. the pex 8524 non-transparency and peer-to-peer functions enable use of fewer total switching elements and fewer hops from source to destination. figure 2-8. benes switch fabric
pex 8524 applications plx technology, inc. 14 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 2.2.7 pci express port expansion the pex 8524 enables, for example , two x8 pci express ports to be expanded into ten ports. certain pci express ports can be bridged to pci or pci-x, using plx bridging products. figure 2-9 illustrates one of the many configurations that the pex 8524 supports. figure 2-9. pci express port expansion
february, 2007 adapter board aggregation expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 15 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 2.2.8 adapter board aggregation the number and variety of pci express native-mode devices is rapidly growing. as these devices become mainstream, it becomes n ecessary to create multi-function an d multi-port adapter boards with pci express capability. the pex 8524 can be used to creat e an adapter or mezzanine board th at aggregates pci express devices into a single port, that can be plu gged into a backplan e or motherboard. figure 2-10 illustrates use of the pex 8524 in this application. the adapter board in figure 2-10 can be transparent, in which case the pci express devices are standard i/o products such as ethernet, fibre channel, and so forth. or, the pex 8524 can provide a non-transparent port to the system (by way of the board edge). in this case, one of the pci express devices can be a cpu or other ?intelligent? device with on-chip processing capability ? thereby needing address domain isolation from the remainder of th e system. this approach is commonly used in raid controllers. figure 2-10. adapter board aggregation
pex 8524 applications plx technology, inc. 16 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 2.2.9 intelligent adapter board usage the pex 8524 supports non-transparency bridging (ntb). figure 2-11 illustrates a host system using an intelligent adapter board, where the adapter bo ard cpu is isolated from the host cpu. the pex 8524 nt port allows the two cpus to be isolated, but communicate with one another through registers designed specifically for that purp ose. the host cpu can dynamically re-assign the upstream port and nt port, allowing system re-configuration. figure 2-11. intelligent adapter board usage
february, 2007 software usage model expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 17 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 2.3 software usage model from a system model viewpoint, each pci express port is a virtual pci-to-pci bridge device, with its own set of pci express configuration registers. the bios or host can configure the other ports by way of the upstream port, using conventional pci enumeration. the virtual pci-to-pci bridges within the pex 8524 are compliant to the pci and pci express system models. the conf iguration space registers (csrs) in a virtual primary/seco ndary pci-to-pci bridge are acces sible by type 0 configuration requests through the virtual prim ary bus interface (matching bus, device, and function numbers). 2.3.1 system configuration the virtual pci-to-pci bridges within the pex 8524 are compliant with the pci and pci express system models. the confi guration space registers (csrs) in a virtual primary/secondary pci-to-pci bridge are accessible by type 0/1 configuration requ ests, by way of the virtual primary bus interface (matching bus, device, and function numbers). 2.3.2 interrupt sources and events the pex 8524 supports the int x interrupt message type (compatible with pci r2.3 interrupt signals) or message signaled interrupts (msi), when enabled. the pex 8524 generates messages for pci express baseline and advanced error reporting error reporting mechanisms. the pex 8524 generates interrupts for hot plug events, and device-specific internal errors, an d forwards interrupts received from downstream ports. both forwarded and internally gene rated interrupts are remapped and collapsed at the upstream port.
pex 8524 applications plx technology, inc. 18 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 this page intentionally left blank.
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 19 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 3 signal ball description 3.1 introduction this chapter provides descriptions of the 680 pe x 8524v and 644 pex 8524 signal balls. the signals are divided into the following groups. the signal name, type, location, and a brief de scription are provided for each signal ball, by package type. table 3-1. pex 8524 signal balls pex 8524vaa/bb/bc pex 8524bb/bc pci express signals ? 680-ball pbga pci express signals ? 644-ball pbga hot plug signals ? 680-ball pbga hot plug signals ? 644-ball pbga serial eeprom signals ? 680-ball pbga serial eeprom signa ls ? 644-ball pbga strapping signals ? 680-ball pbga strapping signals ? 644-ball pbga jtag interface signals ? 680-ball pbga jtag interface signals ? 644-ball pbga no connect signals ? 680-ball pbga no connect signals ? 644-ball pbga power and ground signals ? 680-ball pbga power and ground signals ? 644-ball pbga
signal ball description plx technology, inc. 20 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.2 abbreviations the following abbreviations are used in the signal tables provided in this chapter. table 3-2. ball assignment abbreviations abbreviation description # active-low signal apwr 1.15v 3% (pex 8524vaa) power (vdd10a) balls for serdes analog circuits 1.0v 5% (pex 8524vbb/bc, pex 8524bb/bc) power (vdd10a) balls for serdes analog circuits cmlclkn a a. for refclk input, cml source is recommend ed; however, lvds source is supported. differential low-voltage, high-s peed, cml negative clock inputs cmlclkp a differential low-voltage, high-s peed, cml positive clock inputs cmlrn differential low-voltage, high-s peed, cml negative receiver inputs cmlrp differential low-voltage, high-speed, cml positive receiver inputs cmltn differential low-voltage, high-speed, cml negative transmitter outputs cmltp differential low-voltage, high-speed, cml positive transmitter outputs cpwr 1.15v 3% (pex 8524vaa) power (vdd10) balls for low-voltage core circuits 1.0v 5% (pex 8524vbb/bc, pex 8524bb/bc) power ( vdd10) balls for low-voltage core circuits gnd common ground (vss) for all circuits; also a ssociated with vss_thermal (thermal ground) i input (signals with weak internal pull-up resistors) i/o bi-directional programmable signal (input or output) i/opwr 3.3v power (vdd33) balls for input and output interfaces o output pll_gnd pll ground connection pllpwr 3.3v power (vdd33a ) balls for pll circuits pu pull-up resistor (recommended value between 3k to 10k ohms) serdes differential low-voltage, high-speed , i/o signal pairs (negative and positive) spwr 1.15v 3% (pex 8524vaa) power (vdd10s) balls for serdes digital circuits 1.0v 5% (pex 8524vbb/bc, pex 8524bb/bc) power (vdd10s) balls for serd es digital circuits strap strapping balls cannot be left floating on the board
february, 2007 internal pull-up resistors expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 21 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.3 internal pull-up resistors the signals listed in table 3-3 have a weak internal pull-up resistor. if a listed signal is not used and no board trace is connected to the ball, the internal resi stor is normally sufficient to keep the signal from toggling. if a listed signal is not used, but is connected to a board trace, the inte rnal resistors might not be strong enough to hold the signal in the inactive state, and therefor e it is recommended that the signal be pulled high to vdd33 or low to vss (gnd), as appropriate, through a 3k- to 10k-ohm resistor. table 3-3. balls with internal pull-up resistors signal name ee_do hp_prsnt[1:0]# jtag_tck hp_button[1:0]# hp_prsnt[11:8]# jtag_tdi hp_button[11:8]# hp_pwrflt[1:0]# jtag_tms hp_mrl[1:0]# hp_pwrflt[11:8]# jtag_trst# hp_mrl[11:8]#
signal ball description plx technology, inc. 22 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.4 signal ball descriptions ? pex 8524v, 680-ball pbga 3.4.1 pci express signals ? 680-ball pbga the pci express serdes and co ntrol signals are defined in table 3-4 . note: the ball numbers are ordered in sequence to follow the signal name sequencing [n to 0]. table 3-4. pex 8524vaa/bb/bc pci express signals, 680-ball pbga ? 124 balls signal name type location description pex_lane_good[7:0]# o aa3, y3, w3, v3, u3, t3, r3, p3 active-low pci express lane status indicator outputs for lanes [7:0] and [31:16] (24 balls) these signal balls ca n directly drive common-anode led modules. pex_lane_good[31:16]# o ab31, aa31, y31, w31, v31, u31, t31, r31, p4, r4, t4, u4, v4, w4, y4, aa4 pex_nt_reset# o j1 active-low output used to propagate reset in nt mode pex_pern[7:0] cmlrn ak18, ak16, ak14, ak12, ak10, ak8, ak6, ak4 negative half of pci express receiver differential signal pairs for pex 8524 station 0 (8 balls) pex_pern[31:16] cmlrn e34, e32, e30, e28, e26, e24, e22, e20, e18, e16, e14, e12, e10, e8, e6, e1 negative half of pci express receiver differential signal pairs for pex 8524 station 1 (16 balls) pex_perp[7:0] cmlrp al18, al16, al14, al12, al10, al8, al6, al4 positive half of pci express receiver differential signal pairs for pex 8524 station 0 (8 balls) pex_perp[31:16] cmlrp d34, d32, d30, d28, d26, d24, d22, d20, d18, d16, d14, d12, d10, d8, d6, d1 positive half of pci express receiver differential signal pairs for pex 8524 station 1 (16 balls) pex_perst# i h1 pci express reset used to cause a fundamental reset. (refer to chapter 5, ?reset and initialization,? for further details.) pex_petn[7:0] cmltn ap18, ap16, ap14, ap12, ap10, ap8, ap6, ap4 negative half of pci express transmitter differential signal pairs for pex 8524 station 0 (8 balls) pex_petn[31:16] cmltn a34, a32, a30, a28, a26, a24, a22, a20, a18, a16, a14, a12, a10, a8, a6, a4 negative half of pci express transmitter differential signal pairs for pex 8524 station 1 (16 balls)
february, 2007 pci express signals ? 680-ball pbga expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 23 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 pex_petp[7:0] cmltp an18, an16, an14, an12, an10, an8, an6, an4 positive half of pci express transmitter differential signal pairs for pex 8524 station 0 (8 balls) pex_petp[31:16] cmltp b34, b32, b30, b28, b26, b24, b22, b20, b18, b16, b14, b12, b10, b8, b6, b4 positive half of pci express transmitter differential signal pairs for pex 8524 station 1 (16 balls) pex_refclkn cmlclkn al1 negative half of 100-mhz pci express reference clock input signal pair for pex 8524 pex_refclkp cmlclkp al2 positive half of 100-mhz pci express reference clock input signal pair for pex 8524 table 3-4. pex 8524vaa/bb/bc pci express signals, 680-ball pbga ? 124 balls (cont.) signal name type location description
signal ball description plx technology, inc. 24 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.4.2 hot plug signals ? 680-ball pbga the pex 8524 includes nine hot plug signals fo r each pci express port (6 ports x 9 signals/port = 54 total signals), defined in table 3-5 . these signals are active only fo r downstream ports that are configured at start-up. (refer to chapter 9, ?hot plug support,? for further details.) table 3-5. pex 8524vaa/bb/bc hot plug signals, 680-ball pbga ? 54 balls signal name type location description hp_atnled[1:0]# o l1, y1 hot plug attention led output for station 0 ports (2 balls) active-low slot control logic output us ed to drive the attention indicator. output is set low to turn on the led. enabled when the slot capabilities register attention indicator present bit is set (offset 7ch [3]=1) and controlled by the slot control register attention indicator control field (offset 80h [7:6]). when software writes any value other than 00b ( reserved ) to the attention indicator control field and an attention_indica tor message is sent to the downstream device, a command comple ted interrupt ca n be generated to notify the host that the command has been executed. when the following conditions exist: slot capabilities register attention indicator present bit is set (offset 7ch[3]=1), and slot control register command completed interrupt enable bit is not masked (offset 80h[4]=1), and slot control register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually ex clusive) can be generated to the host. an external current-limiti ng resistor is required. hp_atnled[11:8]# o ae33, t33, af2, u2 hot plug attention led output for station 1 ports (4 balls) refer to description for hp_atnled[1:0]#. hp_button[1:0]# i pu a k1, w1 hot plug attention button input for station 0 ports (2 balls) active-low slot control logic input, directly connected to the attention button, with input assertio n status latched in the slot status register attention button pressed field (offset 80h[16]). enabled when the slot capabilities register attention button present bit is set (offset 7ch[0]=1). when the following conditions exist: hp_button x # is not masked ( slot control register attention button pressed enable bit (offset 80h [0]=1), and slot capabilities register hot plug capable bit is set (offset 7ch[6]=1), and slot control register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated, to notify the host of intended board insertion or removal. note: hp_buttonx# is internally de- bounced, but must remain stable for at least 10 ms. hp_button[11:8]# i pu a af33, u33, ag2, v2 hot plug attention button input for station 1 ports (4 balls) refer to description for hp_button[1:0]#.
february, 2007 hot plug signals ? 680-ball pbga expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 25 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 hp_clken[1:0]# o v1, ag1 reference clock enable output for station 0 ports (2 balls) active-low output that, when enab led, allows external refclk to be provided to the slot. enabled when the slot capabilities register power controller present bit is set (offset 7ch [1]=1), and controlled by the slot control register power controller control bit (offset 80h [10]). the time delay from hp_pwren x # output assertion to hp_clken x # output assertion is program mable (through serial eeprom load) from 16 ms (default) to 128 ms, in the hpc tpepv delay field (offset 1e0h [4:3]). hp_clken[11:8]# o v33, j33, w2, k2 reference clock enable output for station 1 ports (4 balls) refer to description for hp_clken[1:0]#. hp_mrl[1:0]# i pu a m1, aa1 hot plug manually operated re tention latch sensor input for station 0 ports (2 balls) active-low input that tr iggers slot control logi c. directly connected to an optional mrl sensor that is logi c high when the latch is not closed. hp_mrl x # input assertion enables hot plug output sequencing to turn on the slot?s power (hp_pwren x # and hp_pwrled x #) and clock (hp_clken x #), and de-assert reset (hp_perst x #) after reset or under software control. a change in the hp_mrl x # input signal state is latched in the slot status register mrl sensor changed bit (offset 80h[18]), and the state change can assert an interrupt to notify the host of a change in the mrl sensor state. when the following conditions exist: hp_mrl x # is not masked ( slot control register mrl sensor changed enable bit, offset 80h[2]=1), and slot control register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated. if the associated hot plug-capable down stream port connects to a pci express board slot that does not imple ment an mrl sensor, hp_mrl x # is normally connected to hp_prsnt x # and a pull-up resistor, with the common node connected to the prsnt2# signal(s) at the slot. if the associated hot plug- capable downstream port instead connects directly to a device (in which case hot plug is not used), pull hp_mrl x # low. note: hp_mrlx# is internally de- bounced, but must remain stable for at least 10 ms. hp_mrlx#, if enabled, is not de-bounced when sampled immediately after reset. hp_mrl[11:8]# i pu a ad33, r33, ae2, t2 hot plug manually operated re tention latch sensor input for station 1 ports (4 balls) refer to descripti on for hp_mrl[1:0]#. hp_perst[1:0]# o t1, ae1 active-low reset output for station 0 ports (2 balls) active-low hot plug output used to reset the slot. controlled by the slot control register power controller control bit (offset 80h[10]). hp_perst[11:8]# o y33, l33, aa2, m2 active-low reset output for station 1 ports (4 balls) refer to description for hp_perst[1:0]#. table 3-5. pex 8524vaa/bb/bc hot plug signals, 680-ball pbga ? 54 balls (cont.) signal name type location description
signal ball description plx technology, inc. 26 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 hp_prsnt[1:0]# i pu a r1, ad1 combination of hot plug prsnt1# and prsnt2# input for station 0 ports (2 balls) active-low input connected to the slot ?s prsnt2# signal, which on the add-in board connects to the slot ?s prsnt1# signal, which is normally grounded on the prsnt2# signal at the motherboard slot. a change in the hp_prsnt x # input signal state is latched in the slot status register presence detect changed bit (offset 80h [19]), and the state change can assert an interrupt to notify the host of board presence or absence. when the following conditions exist: hp_prsnt x # is not masked ( slot control register presence detect changed enable bit (offset 80h[3]=1), and slot control register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated. note: hp_prsntx# is internally de-boun ced, but must remain stable for at least 10 ms. hp_prsnt[11:8]# i pu a aa33, m33, ab2, n2 combination of hot plug prsnt1# and prsnt2# input for station 1 ports (4 balls) refer to description for hp_prsnt[1:0]#. hp_pwren[1:0]# o p1, ac1 active-low hot plug power enable output for station 0 ports (2 balls) active-low slot control logic output th at controls the sl ot power state. when this signal is low, power is enabled to the slot. enabled when the slot capabilities register power controller present bit is set (offset 7ch [1]=1). when software turns the slot?s power controller on or off ( slot control register power controller control bit, offset 80h [10]), a command completed interrupt can be generated to notify the host that the command has been executed. when the following conditions exist: slot control register command completed interrupt enable bit is not masked (offset 80h[4]=1), and slot control register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually ex clusive) can be generated to the host. when hp_mrl x # is enabled [ slot capabilities register mrl sensor present bit is set (offset 7ch[2]=1)], hp_mrl x # input assertion enables hot plug output sequencing to turn on the sl ot?s power, by asserting hp_pwren x # after reset or under software control. hp_pwren[11:8]# o ab33, n33, ac2, p2 active-low hot plug power enable output for station 1 ports (4 balls) refer to description for hp_pwren[1:0]#. table 3-5. pex 8524vaa/bb/bc hot plug signals, 680-ball pbga ? 54 balls (cont.) signal name type location description
february, 2007 hot plug signals ? 680-ball pbga expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 27 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 hp_pwrflt[1:0]# i pu a n1, ab1 hot plug power fault input for station 0 ports (2 balls) active-low input that indicates the slot ?s external power controller detected a power fault on one or more supply rails. enabled when the slot capabilities register power controller present bit is set (offset 7ch [1]=1), and input assertion status is latched in the slot status register power fault detected bit (offset 80h [17]). when the following conditions exist: hp_pwrflt x # is not masked ( slot control register power fault detector enable bit (offset 80h[1]=1), and slot control register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated, to notify the host of a power fault. note: if hp_pwrenx# and hp_clkenx# are not used, hp_pwrfltx# can be used as a general-purpose i nput with status reflected in the slot status register power fault detected (offset 80h[17]), provided the slot capabilities register power controller present bit is set (offset 7ch[1]=1). hp_pwrflt[11:8]# i pu a ac33, p33, ad2, r2 hot plug power fault input for station 1 ports (4 balls) refer to description for hp_pwrflt[1:0]#. hp_pwrled[1:0]# o u1, af1 hot plug power led output for station 0 ports (2 balls) active-low slot control logic output us ed to drive the power indicator. this output is set low to turn on the led. enabled when the slot capabilities register power indicator present bit is set (offset 7ch[4]=1), and controlled by the slot status register power indicator control field (offset 80h[9:8]). when software writes any value other than 00b ( reserved ) to the power indicator control field and a power_indica tor message is sent to the downstream device, a command comp leted interrupt can be generated to notify the host that the command has been executed. when the following conditions exist: slot capabilities register power indicator present bit is set (offset 7ch[4]=1), and slot control register command completed interrupt enable bit is not masked (offset 80h[4]=1), and slot control register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually ex clusive) can be generated to the host. an external current-limit ing resistor is required. hp_pwrled[11:8]# o w33, k33, y2, l2 hot plug power led output for station 1 ports (4 balls) refer to description for hp_pwrled[1:0]#. a. if hot plug outputs (including hp_perstx#) are used an d hp_mrlx# input is not used, pull hp_mrlx# input low so that hot plug outputs (includi ng hp_perstx#) will properly sequ ence if the serial eeprom is blank or missing. default register values enable hp_mrlx#, which must then be asserted to cause hot plug outputs to toggle (for example, to de-assert hp_ perstx# and assert hp_pwrledx#). table 3-5. pex 8524vaa/bb/bc hot plug signals, 680-ball pbga ? 54 balls (cont.) signal name type location description
signal ball description plx technology, inc. 28 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.4.3 serial eeprom signals ? 680-ball pbga the pex 8524 includes five signals for interfacing to a serial eeprom, defined in table 3-6 . table 3-6. pex 8524vaa/bb/bc serial eeprom signals, 680-ball pbga ? 5 balls signal name type location description ee_cs# o ag32 serial eeprom active-low chip select output ee_di o ah34 pex 8524 output to serial eeprom data input ee_do i pu ag34 pex 8524 input from serial eeprom data output ee_pr# i ah33 serial eeprom present active-low input must be tied to vss to indica te serial eeprom presence. ee_sk o ag33 7.8 mhz serial eeprom clock output
february, 2007 strapping signals ? 680-ball pbga expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 29 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.4.4 strapping signals ? 680-ball pbga the pex 8524 strapping signals, defined in table 3-7 , set the configuration of upstream and nt port assignment, port width, and various setup and te st modes. these balls must be tied high to vdd33 or low to vss (gnd). after a fundamental reset, the link capabilities , debug control , and port configuration registers capture ball status. strapping ball configuration data can be changed by writing new data to these registers from the serial eeprom. table 3-7. pex 8524vaa/bb/bc strapping signals, 680-ball pbga ? 24 balls signal name type location description strap_factory_test1# i strap ah2 for factory test only must be tied high. strap_mode_sel[1:0] i strap h2, g1 mode selects (2 balls) register/bits ? debug control register mode select field (port 0, offset 1dch [ 19:18 ]) ll = reserved lh = intelligent adapter mode hl = dual-host mode hh = transparent mode (t mode) strap_nt_upstrm_portsel[3:0] i strap m31, l31, l32, k32 select non-transparent upstream port (4 balls) register/bits ? debug control register nt port number field (port 0, offset 1dch [ 27:24 ]) llll = port 0 lllh = port 1 llhl to lhhh = reserved hlll = port 8 hllh = port 9 hlhl = port 10 hlhh = port 11 hhll to hhhh = reserved if nt port is not used, set to hhhh. strap_stn0_portcfg[4:0] i strap ac32, ac31, ad32, ad31, ae32 strapping signals to select number of lanes in station 0, ports 0, 1 (5 balls) register/bits ? port configuration register port configuration field (port 0, offset 224h [ 4:0 ]) note: x0 indicates the port is not enabled. lllll = x4, x4 lllhl = x8 all other configurations are reserved and default to x4, x4.
signal ball description plx technology, inc. 30 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 strap_stn1_portcfg[3:0] i strap p31, n32, n31, m32 strapping signals to select number of lanes in station 1, ports 8, 9, 10, 11 (4 balls) register/bits ? port configuration register port configuration field (port 8, offset 224h [ 4:0 ]) note: x0 indicates the port is not enabled. llll = x4, x4, x4, x4 lllh = x16, x0, x0, x0 llhl = x8, x8, x0, x0 llhh = x8, x4, x4, x0 lhll = x8, x4, x2, x2 lhlh = x8, x2, x2, x4 lhhl = x8, x2, x4, x2 all other configurations are reserved and default to x4, x4, x4, x4. strap_testmode[3:0] i strap h33, h34, g33, g34 test mode selects (4 balls) factory test only register ? physical layer test (ports 0 and 8, offset 228h ) hhhh = default (test modes are disabled) strap_upstrm_portsel[3:0] i strap n4, m4, n3, m3 strapping signals to select upstream port (4 balls) register/bits ? debug control register upstream port number field (port 0, offset 1dch [ 11:8 ]) llll = port 0 lllh = port 1 llhl to lhhh = reserved hlll = port 8 hllh = port 9 hlhl = port 10 hlhh = port 11 hhll to hhhh = reserved table 3-7. pex 8524vaa/bb/bc strapping signals, 680-ball pbga ? 24 balls (cont.) signal name type location description
february, 2007 jtag interface signals ? 680-ball pbga expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 31 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.4.5 jtag interface signals ? 680-ball pbga the pex 8524 includes five signals for performing jtag boundary scan, defined in table 3-8 . (refer to chapter 17, ?test and debug,? for further details.) table 3-8. pex 8524vaa/bb/bc jtag interface signals, 680-ball pbga ? 5 balls signal name type location description jtag_tck i pu j2 jtag test clock input jtag test access port (tap) cont roller clock source. frequency can be from 0 to 10 mhz. jtag_tdi i pu k3 jtag test data input serial input to the tap controller for test instructions and data. jtag_tdo o j3 jtag test data output serial output from the tap controll er test instruct ions and data. jtag_tms i pu j4 jtag test mode select when high, jtag test mode is enabled. input decoded by the tap controller to control test operations. jtag_trst# i pu k4 jtag test reset active-low input used to re set the test access port. tie to ground through a 1.5k-ohm resistor, to hold the jtag tap controller in the test-l ogic-reset state, which enables standard logic operation. when jtag functionality is not us ed, the jtag_trst# input should be pulled or driven low, to place the tap controller into the test-logic-reset state, which disables th e test logic and enables standard logic operation. alternatively, if jtag_trst# input is high, the jtag tap controller can be placed into the test-logic-reset state by initializing the jtag tap controller?s instruction register to contain the idcode instruction, or by holding the jtag_tms input high for at least five rising edges of the jtag_tck input.
signal ball description plx technology, inc. 32 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.4.6 no connect signals ? 680-ball pbga caution: do not connect the following pex 8524 balls to board electrical paths, as these balls are not connected within the pex 8524. table 3-9. pex 8524vaa/bb/bc no connect signals, 680-ball pbga ? 92 balls signal name type location description n/c reserved a1, a2, b1, b2, d3, e3, f3, g2, g3, g32, h3, h4, j34, k34, l3, l4, l34, m34, n34, p34, r32, r34, t32, t34, u32, u34, v32, v34, w32, w34, y32, y34, aa32, aa34, ab3, ab4, ab32, ab34, ac3, ac4, ac34, ad3, ad4, ad34, ae3, ae4, ae31, ae34, af3, af4, af31, af32, af34, ag3, ah3, ah32, ak20, ak22, ak24, ak26, ak28, ak30, ak32, ak34, al20, al22, al24, al26, al28, al30, al32, al34, an1, an2, an20, an22, an24, an26, an28, an30, an32, an34, ap1, ap2, ap20, ap22, ap24, ap26, ap28, ap30, ap32, ap34 no connect (92 balls) do not connect these balls to board electrical paths.
february, 2007 power and ground signals ? 680-ball pbga expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 33 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.4.7 power and ground signals ? 680-ball pbga table 3-10. pex 8524vaa/bb/bc power and ground signals, 680-ball pbga ? 376 balls signal name type location description vdd10 cpwr e9, e11, e13, e17, e 19, e21, e25, e27, e29, f5, g5, g30, j30, k5, m5, m30, p30, t5, t30, v5, v30, aa5, aa30, ac5, ac30, ae5, ae30, ag5, ag30, aj30, ak9, ak11, ak13, ak17, ak19, ak21, ak23, ak25, ak27, ak29 1.15v 3% (pex 8524vaa) or 1.0v 5% (pex 8524vbb/bc) power for core logic (40 balls) vdd10a apwr e7, e15, e23, f30, aj5, ak7, ak15 1.15v 3% (pex 8524vaa) or 1.0v 5% (pex 8524vbb/bc) power for serdes analog circuits (7 balls) vdd10s spwr b3, b5, b7, b9, b11, b13, b15, b17, b19, b21, b23, b25, b27, b29, b31, b33, c3, c7, c11, c15, c19, c23, c27, c31, d4, e5, e31, e 33, f33, aj33, ak5, ak31, ak33, am3, am7, am11, am15, am19, am23, am27, am31, an3, an5, an7, an9, an11, an13, an15, an17, an19, an21, an23, an25, an27, an29, an31, an33 1.15v 3% (pex 8524vaa) or 1.0v 5% (pex 8524vbb/bc) power for serdes digital circuits (57 balls) vdd33 i/opwr h5, h32, j31, j32, k30, k31, l5, n5, n30, r5, u5, u30, y5, y30, ab5, ab30, af5, af30, ag31, ah1, ah30 3.3v power for i/ o logic functions (21 balls) vdd33a pllpwr ah5 3.3v power for pll circuits vss gnd a3, a7, a11, a15, a 19, a23, a27, a31, c1, c2, c4, c5, c6, c8, c9, c10, c12, c13, c14, c16, c17, c18, c20, c21, c22, c24, c25, c26, c28, c29, c30, c32, c33, c34, d2, d5, d7, d9, d11, d13, d15, d17, d19, d21, d23, d25, d27, d29, d31, d33, e2, e4, f1, f2, f4, f31, f32, f34, g4, g31, h30, h31, j5, l30, p5, p32, r30, w5, w30, ad5, ad30, ag4, ah31, aj1, aj2, aj3, aj4, aj31, aj32, aj34, ak1, ak2, ak3, al3, al5, al7, al9, al11, al13, al15, al17, al19, al21, al23, al25, al27, al29, al31, al33, am1, am2, am4, am5, am6, am8, am9, am10, am12, am13, am14, am16, am17, am18, am20, am21, am22, am24, am25, am26, am28, am29, am30, am32, am33, am34, ap3, ap7, ap11, ap15, ap19, ap23, ap27, ap31 ground connections (133 balls)
signal ball description plx technology, inc. 34 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 vss_thermal thermal-gnd n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, p13, p14, p15, p16, p17, p18, p19, p20, p21, p22, r13, r14, r15, r16, r17, r18, r19, r20, r21, r22, t13, t14, t15, t16, t17, t18, t19, t20, t21, t22, u13, u14, u15, u16, u17, u18, u19, u20, u21, u22, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, w13, w14, w15, w16, w17, w18, w19, w20, w21, w22, y13, y14, y15, y16, y17, y18, y19, y20, y21, y22, aa13, aa14, aa15, aa16, aa17, aa18, aa19, aa20, aa21, aa22, ab13, ab14, ab15, ab16, ab17, ab18, ab19, ab20, ab21, ab22 thermal-ball ground connections (100 balls) vssa_pll pll_gnd ah4 pll ground connection vtt_pex[7:0] supply ap33, ap29, ap25, ap21, ap17, ap13, ap9, ap5 serdes termination supply for station 0 a (8 balls) tied to serdes termination supply voltage (typically 1.5v). vtt_pex[15:8] supply a33, a29, a25, a21, a17, a13, a9, a5 serdes termination supply for station 1 a (8 balls) tied to serdes termination supply voltage (typically 1.5v). a. pex_petn/p[x] serdes termination voltage controls the transmitter common mode voltage (v tx?cm ) value and output voltage swing (v tx?diffp ), per the following formula: v tx-cm = v tt ? v tx?diffp table 3-10. pex 8524vaa/bb/bc power and ground signals, 680-ball pbga ? 376 balls (cont.) signal name type location description
february, 2007 signal ball descriptions ? pex 8524, 644-ball pbga expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 35 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.5 signal ball descriptions ? pex 8524, 644-ball pbga 3.5.1 pci express signals ? 644-ball pbga the pci express serdes and co ntrol signals are defined in table 3-11 . note: the ball numbers are ordered in sequence to follow the signal name sequencing [n to 0]. table 3-11. pex 8524bb/bc pci express signals, 644-ball pbga ? 124 balls signal name type location description pex_lane_good[7:0]# o w1, v2, u2, t1, r2, p2, n3, m3 active-low pci express lane status indicator outputs for lanes [7:0] and [31:16] (24 balls) these signal balls can directly drive common-anode led modules. pex_lane_good[31:16]# o ab27, aa27, y27, w27, v27, u30, t30, r30, m2, n2, ad2, r1, ad3, u3, ad1, w2 pex_nt_reset# o h3 active-low output used to propagate reset in nt mode pex_pern[7:0] cmlrn af20, af18, af16, af14, af12, ag10, af8, af6 negative half of pci express receiver differential signal pairs for pex 8524 station 0 (8 balls) pex_pern[31:16] cmlrn g26, e30, e28, e26, e24, e22, e20, e18, e16, e14, e12, e10, e8, e6, e4, e2 negative half of pci express receiver differential signal pairs for pex 8524 station 1 (16 balls) pex_perp[7:0] cmlrp ag20, ag18, ag16, ag14, ag12, af10, ag8, ag6 positive half of pci express receiver differential signal pairs for pex 8524 station 0 (8 balls) pex_perp[31:16] cmlrp g27, d30, d28, d26, d24, d22, d20, d18, d16, d14, d12, d10, d8, d6, d4, d2 positive half of pci express receiver differential signal pairs for pex 8524 station 1 (16 balls) pex_perst# i g3 pci express reset used to cause a fundamental reset. (refer to chapter 5, ?reset and initialization,? for further details.)
signal ball description plx technology, inc. 36 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 pex_petn[7:0] cmltn ak20, ak18, ak16, ak14, ak12, ak10, ak8, ak6 negative half of pci express transmitter differential signal pairs for pex 8524 station 0 (8 balls) pex_petn[31:16] cmltn g30, a30, a28, a26, a24, a22, a20, a18, a16, a14, a12, a10, a8, a6, a4, a2 negative half of pci express transmitter differential signal pairs for pex 8524 station 1 (16 balls) pex_petp[7:0] cmltp aj20, aj18, aj16, aj14, aj12, aj10, aj8, aj6 positive half of pci express transmitter differential signal pairs for pex 8524 station 0 (8 balls) pex_petp[31:16] cmltp g29, b30, b28, b26, b24, b22, b20, b18, b16, b14, b12, b10, b8, b6, b4, b2 positive half of pci express transmitter differential signal pairs for pex 8524 station 1 (16 balls) pex_refclkn cmlclkn ak4 negative half of 100-mhz pci express reference clock input signal pair for pex 8524 pex_refclkp cmlclkp aj4 positive half of 100-mhz pci express reference clock input signal pair for pex 8524 table 3-11. pex 8524bb/bc pci express signals, 644-ball pbga ? 124 balls (cont.) signal name type location description
february, 2007 hot plug signals ? 644-ball pbga expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 37 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.5.2 hot plug signals ? 644-ball pbga the pex 8524 includes nine hot plug signals for each pci express port (6 ports x 9 signals/port = 54 total signals), defined in table 3-12 . these signals are active only fo r downstream ports that are configured at start-up. (refer to chapter 9, ?hot plug support,? for further details.) table 3-12. pex 8524bb/bc hot plug signals, 644-ball pbga ? 54 balls signal name type location description hp_atnled[1:0]# o k1, u4 hot plug attention led output for station 0 ports (2 balls) active-low slot control logi c output used to drive the attention indicator. output is set low to turn on the led. enabled when the slot capabilities register attention indicator present bit is set (offset 7ch [3]=1) and controlled by the slot control register attention indicator control field (offset 80h [7:6]). when software writes any value other than 00b ( reserved ) to the attention indicator control field and an attention_indicator message is sent to the downstream device, a command completed interrupt can be generated to notify the host that the command has been executed. when the following conditions exist: slot capabilities register attention indicator present bit is set (offset 7ch[3]=1), and slotcontrol register command completed interrupt enable bit is not masked (offset 80h[4]=1), and slotcontrol register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated to the host. an external current-limiti ng resistor is required. hp_atnled[11:8]# o ae29, t28, ab2, r3 hot plug attention led output for station 1 ports (4 balls) refer to description for hp_atnled[1:0]#. hp_button[1:0]# i pu a j3, t4 hot plug attention button input for station 0 ports (2 balls) active-low slot cont rol logic input, directly connected to the attention button, with input assertion stat us latched in the slot status register attention button pressed field (offset 80h[16]). enabled when the slot capabilities register attention button present bit is set (offset 7ch[0]=1). when the following conditions exist: hp_button x # is not masked ( slot control register attention button pressed enable bit (offset 80h [0]=1), and slot capabilities register hot plug capable bit is set (offset 7ch[6]=1), and slotcontrol register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated, to notify the host of in tended board insertion or removal. note: hp_buttonx# is internally de-bounced, but must remain stable for at least 10 ms. hp_button[11:8]# i pu a af29, u28, ac1, t2 hot plug attention button input for station 1 ports (4 balls) refer to description for hp_button[1:0]#.
signal ball description plx technology, inc. 38 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 hp_clken[1:0]# o t3, ab4 reference clock enable output for station 0 ports (2 balls) active-low output that, when enab led, allows external refclk to be provided to the slot. enabled when the slot capabilities register power controller present bit is set (offset 7ch [1]=1), and controlled by the slot control register power controller control bit (offset 80h [10]). the time delay from hp_pwren x # output assertion to hp_clken x # output assertion is programmable (through serial eeprom load) from 16 ms (default) to 128 ms, in the hpc tpepv delay field (offset 1e0h [4:3]). hp_clken[11:8]# o v29, k30, u1, j2 reference clock enable output for station 1 ports (4 balls) refer to description for hp_clken[1:0]#. hp_mrl[1:0]# i pu a l1, v3 hot plug manually operated retention latch sensor input for station 0 ports (2 balls) active-low input that triggers slot control logic. directly connected to an optional mrl sensor that is logic high when the latch is not closed. hp_mrl x # input assertion enables hot plug output sequencing to turn on the slot?s power (hp_pwren x # and hp_pwrled x #) and clock (hp_clken x #), and de-assert reset (hp_perst x #) after reset or under software control. a change in the hp_mrl x # input signal state is latched in the slot status register mrl sensor changed bit (offset 80h[18]), and the state change can assert an interrupt to notify the host of a change in the mrl sensor state. when the following conditions exist: hp_mrl x # is not masked ( slot control register mrl sensor changed enable bit, offset 80h[2]=1), and slotcontrol register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated. if the associated hot plug-capabl e downstream por t connects to a pci express board slot that does not implement an mrl sensor, hp_mrl x # is normally connected to hp_prsnt x # and a pull-up resistor, with the common node conne cted to the prsnt2# signal(s) at the slot. if the associated hot plug-capable downstream port instead connects directly to a device (in which case hot plug is not used), pull hp_mrl x # low. note: hp_mrlx# is internally de-bounced, but must remain stable for at least 10 ms. hp_mrlx#, if e nabled, is not de-bounced when sampled immediately after reset. hp_mrl[11:8]# i pu a ad29, r28, aa4, p3 hot plug manually operated retention latch sensor input for station 1 ports (4 balls) refer to description for hp_mrl[1:0]#. hp_perst[1:0]# o p4, aa3 active-low reset output for station 0 ports (2 balls) active-low hot plug output used to reset the slot. controlled by the slot control register power controller control bit (offset 80h[10]). hp_perst[11:8]# o y29, l27, v4, k4 active-low reset output for station 1 ports (4 balls) refer to description for hp_perst[1:0]#. table 3-12. pex 8524bb/bc hot plug signals, 644-ball pbga ? 54 balls (cont.) signal name type location description
february, 2007 hot plug signals ? 644-ball pbga expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 39 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 hp_prsnt[1:0]# i pu a p1, y4 combination of hot plug prsnt1# and prsnt2# input for station 0 ports (2 balls) active-low input connected to the slot?s prsnt2# signal, which on the add-in board connects to the slot?s prsnt1# signal, which is normally grounded on the prsnt2# signal at th e motherboard slot. a change in the hp_prsnt x # input signal state is latched in the slot status register presence detect changed bit (offset 80h [19]), and the state change can assert an interrupt to notify the ho st of board presence or absence. when the following conditions exist: hp_prsnt x # is not masked ( slot control register presence detect changed enable bit (offset 80h[3]=1), and slotcontrol register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated. note: hp_prsntx# is internally de- bounced, but must remain stable for at least 10 ms. hp_prsnt[11:8]# i pu a aa29, m27, w4, l4 combination of hot plug prsnt1# and prsnt2# input for station 1 ports (4 balls) refer to description for hp_prsnt[1:0]#. hp_pwren[1:0]# o n1, y1 active-low hot plug power enable output for station 0 ports (2 balls) active-low slot control logic output th at controls the slot power state. when this signal is low, power is enabled to the slot. enabled when the slot capabilities register power controller present bit is set (offset 7ch [1]=1). when software turns the slot?s power controller on or off ( slot control register power controller control bit, offset 80h [10]), a command completed interrupt can be generated to notify the host that the command has been executed. when the following conditions exist: slotcontrol register command completed interrupt enable bit is not masked (offset 80h[4]=1), and slotcontrol register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated to the host. when hp_mrl x # is enabled [ slot capabilities register mrl sensor present bit is set (offset 7ch[2]=1)], hp_mrl x # input assertion enables hot plug output sequencing to turn on the slot?s power, by asserting hp_pwren x # after reset or under software control. hp_pwren[11:8]# o ab29, n27, y2, m4 active-low hot plug power enable output for station 1 ports (4 balls) refer to description for hp_pwren[1:0]#. table 3-12. pex 8524bb/bc hot plug signals, 644-ball pbga ? 54 balls (cont.) signal name type location description
signal ball description plx technology, inc. 40 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 hp_pwrflt[1:0]# i pu a m1, w3 hot plug power fault input for station 0 ports (2 balls) active-low input that indicates the slot?s external power controller detected a power fault on one or more supply rails. enabled when the slot capabilities register power controller present bit is set (offset 7ch [1]=1), and input assertion status is latched in the slot status register power fault detected (offset 80h [17]). when the following conditions exist: hp_pwrflt x # is not masked ( slot control register power fault detector enable bit (offset 80h[1]=1), and slotcontrol register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated, to notify the host of a power fault. note: if hp_pwrenx# and hp_clkenx# are not used, hp_pwrfltx# can be used as a ge neral-purpose input with status reflected in the slot status register power fault detected (offset 80h[17]), provided the slot capabilities register power controller present bit is set (offset 7ch[1]=1). hp_pwrflt[11:8]# i pu a ac29, p28, aa1, n4 hot plug power fault input for station 1 ports (4 balls) refer to description for hp_pwrflt[1:0]#. hp_pwrled[1:0]# o r4, ab1 hot plug power led output for station 0 ports (2 balls) active-low slot control logic output used to drive the power indicator. this output is set low to turn on the led. enabled when the slot capabilities register power indicator present bit is set (offset 7ch[4]=1), and controlled by the slot status register power indicator control field (offset 80h[9:8]). when software writes any value other than 00b ( reserved ) to the power indicator control field and a power_indicator message is sent to the downstream device, a command completed interrupt can be generated to notify the host that the command has been executed. when the following conditions exist: slot capabilities register power indicator present bit is set (offset 7ch[4]=1), and slotcontrol register command completed interrupt enable bit is not masked (offset 80h[4]=1), and slotcontrol register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated to the host. an external current-limiti ng resistor is required. hp_pwrled[11:8]# o w29, k27, v1, j4 hot plug power led output for station 1 ports (4 balls) refer to description for hp_pwrled[1:0]#. a. if hot plug outputs (including hp_perstx#) are used a nd hp_mrlx# input is not used, pull hp_mrlx# input low so that hot plug outputs (including hp_perstx#) will proper ly sequence if the serial eeprom is blank or missing. default register values enable hp_mrlx#, which must th en be asserted to cause hot plug outputs to toggle (for example, to de-assert hp_perstx# and assert hp_pwrledx#). table 3-12. pex 8524bb/bc hot plug signals, 644-ball pbga ? 54 balls (cont.) signal name type location description
february, 2007 serial eeprom signals ? 644-ball pbga expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 41 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.5.3 serial eeprom signals ? 644-ball pbga the pex 8524 includes five signals for interfacing to a serial eeprom, defined in table 3-13 . table 3-13. pex 8524bb/bc serial eeprom signals, 644-ball pbga ? 5 balls signal name type location description ee_cs# o ag28 serial eeprom active-low chip select output ee_di o ag27 pex 8524 output to serial eeprom data input ee_do i pu ag30 pex 8524 input from serial eeprom data output ee_pr# i ah28 serial eeprom present active-low input must be tied to vss to indica te serial eeprom presence. ee_sk o ag29 7.8 mhz serial eeprom clock output
signal ball description plx technology, inc. 42 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.5.4 strapping signals ? 644-ball pbga the pex 8524 strapping signals, defined in table 3-14 , set the configuration of upstream and nt port assignment, port width, and various setup and test modes. these balls must be tied high to vdd33 or low to vss (gnd). after a fundamental reset, the link capabilities , debug control , and port configuration registers capture ball status. strapping ball configuration data can be changed by writing new data to these registers from the serial eeprom. table 3-14. pex 8524bb/bc strapping signals, 644-ball pbga ? 24 balls signal name type location description strap_factory_test1# i strap ac3 for factory test only must be tied high. strap_mode_sel[1:0] i strap g2, g1 mode selects (2 balls) register/bits ? debug control register mode select field (port 0, offset 1dch [ 19:18 ]) ll = reserved lh = intelligent adapter mode hl = dual-host mode hh = transparent mode (t mode) strap_nt_upstrm_portsel[3:0] i strap m29, l29, l28, k28 select non-transparent upstream port (4 balls) register/bits ? debug control register nt port number field (port 0, offset 1dch [ 27:24 ]) llll = port 0 lllh = port 1 llhl to lhhh = reserved hlll = port 8 hllh = port 9 hlhl = port 10 hlhh = port 11 hhll to hhhh = reserved if nt port is not used, set to hhhh. strap_stn0_portcfg[4:0] i strap ac28, ac27, ad28, ad27, ae28 strapping signals to select number of lanes in station 0, ports 0, 1 (5 balls) register/bits ? port configuration register port configuration field (port 0, offset 224h [ 4:0 ]) lllll = x4, x4 lllhl = x8 all other configurations are reserved and default to x4, x4.
february, 2007 strapping signals ? 644-ball pbga expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 43 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 strap_stn1_portcfg[3:0] i strap p29, n28, n29, m28 strapping signals to select number of lanes in station 1, ports 8, 9, 10, 11 (4 balls) register/bits ? port configuration register port configuration field (port 8, offset 224h [ 4:0 ]) note: x0 indicates the port is not enabled. llll = x4, x4, x4, x4 llhl = x8, x8, x0, x0 llhh = x8, x4, x4, x0 lhll = x8, x4, x2, x2 lhlh = x8, x2, x2, x4 lhhl = x8, x2, x4, x2 all other configurations are reserved and default to x4, x4, x4, x4. strap_testmode[3:0] i strap j28, j27, j30, j29 test mode selects (4 balls) factory test only register ? physical layer test (ports 0 and 8, offset 228h ) hhhh = default (test modes are disabled) strap_upstrm_portsel[3:0] i strap l2, k2, l3, k3 strapping signals to select upstream port (4 balls) register/bits ? debug control register upstream port number field (port 0, offset 1dch [ 11:8 ]) llll = port 0 lllh = port 1 llhl to lhhh = reserved hlll = port 8 hllh = port 9 hlhl = port 10 hlhh = port 11 hhll to hhhh = reserved table 3-14. pex 8524bb/bc strapping signals, 644-ball pbga ? 24 balls (cont.) signal name type location description
signal ball description plx technology, inc. 44 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.5.5 jtag interface signals ? 644-ball pbga the pex 8524 includes five signals for performing jtag boundary scan, defined in table 3-15 . (refer to chapter 17, ?test and debug,? for further details.) 3.5.6 no connect signals ? 644-ball pbga caution: do not connect the following pex 8524 balls to board electrical paths, as these balls are not connected within the pex 8524. table 3-15. pex 8524bb/bc jtag interface signals, 644-ball pbga ? 5 balls signal name type location description jtag_tck i pu h2 jtag test clock input jtag test access port (tap) cont roller clock source. frequency can be from 0 to 10 mhz. jtag_tdi i pu j1 jtag test data input serial input to the tap controller for test instructions and data. jtag_tdo o h1 jtag test data output serial output from the tap controll er test instruct ions and data. jtag_tms i pu g4 jtag test mode select when high, jtag test mode is enabled. input decoded by the tap controller to control test operations. jtag_trst# i pu h4 jtag test reset active-low input used to re set the test access port. tie to ground through a 1.5k-ohm resistor, to hold the jtag tap controller in the test-l ogic-reset state, which enables standard logic operation. when jtag functionality is not us ed, the jtag_trst# input should be pulled or driven low, to place the tap controller into the test-logic-reset state, which disables th e test logic and enables standard logic operation. alternatively, if jtag_trst# input is high, the jtag tap controller can be placed into the test-logic-reset state by initializing the jtag tap controller?s instruction register to contain the idcode instruction, or by holding the jtag_tms input high for at least five rising edges of the jtag_tck input. table 3-16. pex 8524bb/bc no connect signals, 644-ball pbga ? 37 balls signal name type location description n/c reserved k29, l30, m30, n30, p27, p30, r27, r29, t27, t29, u27, u29, v28, v30, w28, w30, y3, y28, y30, aa2, aa28, aa30, ab3, ab28, ab30, ac2, ac30, ad30, ae1, ae2, ae27, ae30, af27, af28, af30, ah27 no connect (36 balls) do not connect these balls to board electrical paths. nc_procmon reserved af2 no connect do not connect this ball to board electrical paths.
february, 2007 power and ground signals ? 644-ball pbga expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 45 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.5.7 power and ground signals ? 644-ball pbga table 3-17. pex 8524bb/bc power and ground signals, 644-ball pbga ? 395 balls signal name type location description vdd10 cpwr k10, k11, k12, k13, k14, k15, k16, k17, k18, k19, k20, k21, l10, l21, m10, m21, n10, n21, p10, p21, r10, r21, t10, t21, u10, u21, v10, v21, w10, w21, y10, y21, aa10, aa11, aa12, aa13, aa14 , aa15, aa16, aa17, aa18, aa19, aa20, aa21 1.0v 5% (pex 8524bb/bc) power for core logic (44 balls) vdd10a apwr e7, e15, e23, f26, af11, af17, af21 1.0v 5% (pex 8524bb/bc) power for serdes analog circuits (7 balls) vdd10s spwr a7, a11, a15, a19, a23, a27, b1, b3, b5, b9, b13, b17, b21, b25, b29, c3, c5, c7, c11, c15, c19, c27, d1, d23, e3, e5, e13, e27, e 29, f2, f28, f30, h27, h29, af23, af25, ag2, ag9, ag13, ag17, ag22, ag24, ah1, ah3, ah7, ah11, ah15, ah19, ah21, ah23, ah25, aj2, aj5, aj9, aj13, aj22, aj24, ak1, ak3, ak7, ak11, ak15, ak17, ak19, ak21, ak23, ak25 1.0v 5% (pex 8524bb/bc) power for serdes digital circuits (67 balls) vdd33 i/opwr h5, j26, k5, l26, m5, n26, p5, r26, t5, u26, v5, w26, y5, aa26, ab5, ac26, ae3, ae26, af3, ag26, ah29, aj26, aj28, aj30, ak27, ak29 3.3v power for i/o logic functions (26 balls) vdd33a pllpwr af1 3.3v power for pll circuits vss gnd a1, a3, a5, a9, a13, a17, a21, a25, a29, b7, b11, b15, b19, b23, b27, c1, c2, c4, c6, c8, c9, c10, c12, c13, c14, c16, c17, c18, c20, c21, c22, c23, c24, c25, c26, c28, c29, c30, d3, d5, d7, d9, d11, d13, d15, d17, d19, d21, d25, d27, d29, e1, f1, f3, f5, f27, f29, g5, g28, h28, h30, j5, k26, l5, m26, n5, p26, r5, t26, u5, v26, w5, y26, aa5, ab26, ac5, ad4, ad5, ad26, ae4, ae5, af4, af5, af13, af22, af24, af26, ag1, ag3, ag4, ag5, ag7, ag11, ag15, ag19, ag21, ag23, ag25, ah2, ah4, ah5, ah6, ah8, ah9, ah10, ah12, ah13, ah14, ah16, ah17, ah18 , ah20, ah22, ah24, ah26, ah30, aj1, aj3, aj7, aj11, aj15, aj17, aj19, aj21, aj23, aj25, aj27, aj29, ak2, ak5, ak9, ak13, ak22, ak24, ak26, ak28, ak30 ground connections (137 balls) vssa_pll pll_gnd ac4 pll ground connection
signal ball description plx technology, inc. 46 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 vss_thermal thermal-gnd l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, m11, m12, m13, m14, m15, m16, m17, m18, m19, m20, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, p11, p12, p13, p14, p15, p16, p17, p18, p19, p20, r11, r12, r13, r14, r15, r16, r17, r18, r19, r20, t11, t12, t13, t14, t15, t16, t17, t18, t19, t20, u11, u12, u13, u14, u15, u16, u17, u18, u19, u20, v11, v12, v13, v14, v15, v16, v17, v18, v19, v20, w11, w12, w13, w14, w15, w16, w17, w18, w19, w20, y11, y12, y13, y14, y15, y16, y17, y18, y19, y20 thermal-ball ground connections (100 balls) not internally connected to the die. vtt_pex[3:0] supply af1 9, af15, af9, af7 serdes termination for station 0 a (4 balls) tied to serdes termination voltage (typically 1.5v). vtt_pex[15:8] supply h26, e25, e21, e19, e17, e11, e9, f4 serdes termination for station 1 a (8 balls) tied to serdes termination voltage (typically 1.5v). a. pex_petn/p[x] serdes termination voltage controls the transmitter common mode voltage (v tx ? cm ) value and output voltage swing (v tx ? diffp ), per the following formula: v tx-cm = v tt ? v tx?diffp table 3-17. pex 8524bb/bc power and ground signals, 644-ball pbga ? 395 balls (cont.) signal name type location description
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 47 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.6 ball assignments by number note: for ?type? definitions, refer to table 3-2 . table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga pex 8524 balls description num name type signal group a1 n/c reserved no connect a2 n/c reserved no connect a3 vss gnd ground a4 pex_petn16 cmltn serdes a5 vtt_pex8 supply power a6 pex_petn17 cmltn serdes a7 vss gnd ground a8 pex_petn18 cmltn serdes a9 vtt_pex9 supply power a10 pex_petn19 cmltn serdes a11 vss gnd ground a12 pex_petn20 cmltn serdes a13 vtt_pex10 supply power a14 pex_petn21 cmltn serdes a15 vss gnd ground a16 pex_petn22 cmltn serdes a17 vtt_pex11 supply power a18 pex_petn23 cmltn serdes a19 vss gnd ground a20 pex_petn24 cmltn serdes a21 vtt_pex12 supply power a22 pex_petn25 cmltn serdes a23 vss gnd ground a24 pex_petn26 cmltn serdes a25 vtt_pex13 supply power a26 pex_petn27 cmltn serdes a27 vss gnd ground a28 pex_petn28 cmltn serdes a29 vtt_pex14 supply power a30 pex_petn29 cmltn serdes a31 vss gnd ground a32 pex_petn30 cmltn serdes a33 vtt_pex15 supply power a34 pex_petn31 cmltn serdes
signal ball description plx technology, inc. 48 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 b1 n/c reserved no connect b2 n/c reserved no connect b3 vdd10s spwr power b4 pex_petp16 cmltp serdes b5 vdd10s spwr power b6 pex_petp17 cmltp serdes b7 vdd10s spwr power b8 pex_petp18 cmltp serdes b9 vdd10s spwr power b10 pex_petp19 cmltp serdes b11 vdd10s spwr power b12 pex_petp20 cmltp serdes b13 vdd10s spwr power b14 pex_petp21 cmltp serdes b15 vdd10s spwr power b16 pex_petp22 cmltp serdes b17 vdd10s spwr power b18 pex_petp23 cmltp serdes b19 vdd10s spwr power b20 pex_petp24 cmltp serdes b21 vdd10s spwr power b22 pex_petp25 cmltp serdes b23 vdd10s spwr power b24 pex_petp26 cmltp serdes b25 vdd10s spwr power b26 pex_petp27 cmltp serdes b27 vdd10s spwr power b28 pex_petp28 cmltp serdes b29 vdd10s spwr power b30 pex_petp29 cmltp serdes b31 vdd10s spwr power b32 pex_petp30 cmltp serdes b33 vdd10s spwr power b34 pex_petp31 cmltp serdes table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 49 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 c1 vss gnd ground c2 vss gnd ground c3 vdd10s spwr power c4 vss gnd ground c5 vss gnd ground c6 vss gnd ground c7 vdd10s spwr power c8 vss gnd ground c9 vss gnd ground c10 vss gnd ground c11 vdd10s spwr power c12 vss gnd ground c13 vss gnd ground c14 vss gnd ground c15 vdd10s spwr power c16 vss gnd ground c17 vss gnd ground c18 vss gnd ground c19 vdd10s spwr power c20 vss gnd ground c21 vss gnd ground c22 vss gnd ground c23 vdd10s spwr power c24 vss gnd ground c25 vss gnd ground c26 vss gnd ground c27 vdd10s spwr power c28 vss gnd ground c29 vss gnd ground c30 vss gnd ground c31 vdd10s spwr power c32 vss gnd ground c33 vss gnd ground c34 vss gnd ground table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 50 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 d1 pex_perp16 cmlrp serdes d2 vss gnd ground d3 n/c reserved no connect d4 vdd10s spwr power d5 vss gnd ground d6 pex_perp17 cmlrp serdes d7 vss gnd ground d8 pex_perp18 cmlrp serdes d9 vss gnd ground d10 pex_perp19 cmlrp serdes d11 vss gnd ground d12 pex_perp20 cmlrp serdes d13 vss gnd ground d14 pex_perp21 cmlrp serdes d15 vss gnd ground d16 pex_perp22 cmlrp serdes d17 vss gnd ground d18 pex_perp23 cmlrp serdes d19 vss gnd ground d20 pex_perp24 cmlrp serdes d21 vss gnd ground d22 pex_perp25 cmlrp serdes d23 vss gnd ground d24 pex_perp26 cmlrp serdes d25 vss gnd ground d26 pex_perp27 cmlrp serdes d27 vss gnd ground d28 pex_perp28 cmlrp serdes d29 vss gnd ground d30 pex_perp29 cmlrp serdes d31 vss gnd ground d32 pex_perp30 cmlrp serdes d33 vss gnd ground d34 pex_perp31 cmlrp serdes table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 51 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 e1 pex_pern16 cmlrn serdes e2 vss gnd ground e3 n/c reserved no connect e4 vss gnd ground e5 vdd10s spwr power e6 pex_pern17 cmlrn serdes e7 vdd10a apwr power e8 pex_pern18 cmlrn serdes e9 vdd10 cpwr power e10 pex_pern19 cmlrn serdes e11 vdd10 cpwr power e12 pex_pern20 cmlrn serdes e13 vdd10 cpwr power e14 pex_pern21 cmlrn serdes e15 vdd10a apwr power e16 pex_pern22 cmlrn serdes e17 vdd10 cpwr power e18 pex_pern23 cmlrn serdes e19 vdd10 cpwr power e20 pex_pern24 cmlrn serdes e21 vdd10 cpwr power e22 pex_pern25 cmlrn serdes e23 vdd10a apwr power e24 pex_pern26 cmlrn serdes e25 vdd10 cpwr power e26 pex_pern27 cmlrn serdes e27 vdd10 cpwr power e28 pex_pern28 cmlrn serdes e29 vdd10 cpwr power e30 pex_pern29 cmlrn serdes e31 vdd10s spwr power e32 pex_pern30 cmlrn serdes e33 vdd10s spwr power e34 pex_pern31 cmlrn serdes table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 52 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 f1 vss gnd ground f2 vss gnd ground f3 n/c reserved no connect f4 vss gnd ground f5 vdd10 cpwr power f30 vdd10a apwr power f31 vss gnd ground f32 vss gnd ground f33 vdd10s spwr power f34 vss gnd ground g1 strap_mode_sel0 i strap strapping ball ? tie high or low, as defined in strap_mode_sel[1:0] g2 n/c reserved no connect g3 n/c reserved no connect g4 vss gnd ground g5 vdd10 cpwr power g30 vdd10 cpwr power g31 vss gnd ground g32 n/c reserved no connect g33 strap_testmode1 i strap strapping ball ? tie high or low, as defined in strap_testmode[3:0] g34 strap_testmode0 i strap h1 pex_perst# i pex control h2 strap_mode_sel1 i strap strapping ball ? tie high or low, as defined in strap_mode_sel[1:0] h3 n/c reserved no connect h4 n/c reserved no connect h5 vdd33 i/opwr power h30 vss gnd ground h31 vss gnd ground h32 vdd33 i/opwr power h33 strap_testmode3 i strap strapping ball ? tie high or low, as defined in strap_testmode[3:0] h34 strap_testmode2 i strap table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 53 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 j1 pex_nt_reset# o pex control j2 jtag_tck i, pu jtag j3 jtag_tdo o jtag j4 jtag_tms i, pu jtag j5 vss gnd ground j30 vdd10 cpwr power j31 vdd33 i/opwr power j32 vdd33 i/opwr power j33 hp_clken10# o hot plug j34 n/c reserved no connect k1 hp_button1# i, pu hot plug k2 hp_clken8# o hot plug k3 jtag_tdi i, pu jtag k4 jtag_trst# i, pu jtag k5 vdd10 cpwr power k30 vdd33 i/opwr power k31 vdd33 i/opwr power k32 strap_nt_upstrm_portsel0 i strap strapping ball ? tie high or low, as defined in strap_nt_upstrm_portsel[3:0] k33 hp_pwrled10# o hot plug k34 n/c reserved no connect l1 hp_atnled1# o hot plug l2 hp_pwrled8# o hot plug l3 n/c reserved no connect l4 n/c reserved no connect l5 vdd33 i/opwr power l30 vss gnd ground l31 strap_nt_upstrm_portsel2 i strap strapping ball ? tie high or low, as defined in strap_nt_upstrm_portsel[3:0] l32 strap_nt_upstrm_portsel1 i strap l33 hp_perst10# o hot plug l34 n/c reserved no connect m1 hp_mrl1# i, pu hot plug m2 hp_perst8# o hot plug m3 strap_upstrm_portsel0 i strap strapping ball ? tie high or low, as defined in strap_upstrm_portsel[3:0] m4 strap_upstrm_portsel2 i strap m5 vdd10 cpwr power m30 vdd10 cpwr power table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 54 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 m31 strap_nt_upstrm_portsel3 i strap strapping ball ? tie high or low, as defined in strap_nt_upstrm_portsel[3:0] m32 strap_stn1_portcfg0 i strap strapping ball ? tie high or low, as defined in strap_stn1_portcfg[3:0] m33 hp_prsnt10# i, pu hot plug m34 n/c reserved no connect n1 hp_pwrflt1# i, pu hot plug n2 hp_prsnt8# i, pu hot plug n3 strap_upstrm_portsel1 i strap strapping ball ? tie high or low, as defined in strap_upstrm_portsel[3:0] n4 strap_upstrm_portsel3 i strap n5 vdd33 i/opwr power n13 vss_thermal thermal-gnd ground n14 vss_thermal thermal-gnd ground n15 vss_thermal thermal-gnd ground n16 vss_thermal thermal-gnd ground n17 vss_thermal thermal-gnd ground n18 vss_thermal thermal-gnd ground n19 vss_thermal thermal-gnd ground n20 vss_thermal thermal-gnd ground n21 vss_thermal thermal-gnd ground n22 vss_thermal thermal-gnd ground n30 vdd33 i/opwr power n31 strap_stn1_portcfg1 i strap strapping ball ? tie high or low, as defined in strap_stn1_portcfg[3:0] n32 strap_stn1_portcfg2 i strap n33 hp_pwren10# o hot plug n34 n/c reserved no connect p1 hp_pwren1# o hot plug p2 hp_pwren8# o hot plug p3 pex_lane_good0# o lane status p4 pex_lane_good23# o lane status p5 vss gnd ground p13 vss_thermal thermal-gnd ground p14 vss_thermal thermal-gnd ground p15 vss_thermal thermal-gnd ground p16 vss_thermal thermal-gnd ground p17 vss_thermal thermal-gnd ground p18 vss_thermal thermal-gnd ground p19 vss_thermal thermal-gnd ground table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 55 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 p20 vss_thermal thermal-gnd ground p21 vss_thermal thermal-gnd ground p22 vss_thermal thermal-gnd ground p30 vdd10 cpwr power p31 strap_stn1_portcfg3 i strap strapping ball ? tie high or low, as defined in strap_stn1_portcfg[3:0] p32 vss gnd ground p33 hp_pwrflt10# i, pu hot plug p34 n/c reserved no connect r1 hp_prsnt1# i, pu hot plug r2 hp_pwrflt8# i, pu hot plug r3 pex_lane_good1# o lane status r4 pex_lane_good22# o lane status r5 vdd33 i/opwr power r13 vss_thermal thermal-gnd ground r14 vss_thermal thermal-gnd ground r15 vss_thermal thermal-gnd ground r16 vss_thermal thermal-gnd ground r17 vss_thermal thermal-gnd ground r18 vss_thermal thermal-gnd ground r19 vss_thermal thermal-gnd ground r20 vss_thermal thermal-gnd ground r21 vss_thermal thermal-gnd ground r22 vss_thermal thermal-gnd ground r30 vss gnd ground r31 pex_lane_good24# o lane status r32 n/c reserved no connect r33 hp_mrl10# i, pu hot plug r34 n/c reserved no connect t1 hp_perst1# o hot plug t2 hp_mrl8# i, pu hot plug t3 pex_lane_good2# o lane status t4 pex_lane_good21# o lane status t5 vdd10 cpwr power t13 vss_thermal thermal-gnd ground t14 vss_thermal thermal-gnd ground t15 vss_thermal thermal-gnd ground t16 vss_thermal thermal-gnd ground table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 56 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 t17 vss_thermal thermal-gnd ground t18 vss_thermal thermal-gnd ground t19 vss_thermal thermal-gnd ground t20 vss_thermal thermal-gnd ground t21 vss_thermal thermal-gnd ground t22 vss_thermal thermal-gnd ground t30 vdd10 cpwr power t31 pex_lane_good25# o lane status t32 n/c reserved no connect t33 hp_atnled10# o hot plug t34 n/c reserved no connect u1 hp_pwrled1# o hot plug u2 hp_atnled8# o hot plug u3 pex_lane_good3# o lane status u4 pex_lane_good20# o lane status u5 vdd33 i/opwr power u13 vss_thermal thermal-gnd ground u14 vss_thermal thermal-gnd ground u15 vss_thermal thermal-gnd ground u16 vss_thermal thermal-gnd ground u17 vss_thermal thermal-gnd ground u18 vss_thermal thermal-gnd ground u19 vss_thermal thermal-gnd ground u20 vss_thermal thermal-gnd ground u21 vss_thermal thermal-gnd ground u22 vss_thermal thermal-gnd ground u30 vdd33 i/opwr power u31 pex_lane_good26# o lane status u32 n/c reserved no connect u33 hp_button10# i, pu hot plug u34 n/c reserved no connect v1 hp_clken1# o hot plug v2 hp_button8# i, pu hot plug v3 pex_lane_good4# o lane status v4 pex_lane_good19# o lane status v5 vdd10 cpwr power v13 vss_thermal thermal-gnd ground table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 57 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 v14 vss_thermal thermal-gnd ground v15 vss_thermal thermal-gnd ground v16 vss_thermal thermal-gnd ground v17 vss_thermal thermal-gnd ground v18 vss_thermal thermal-gnd ground v19 vss_thermal thermal-gnd ground v20 vss_thermal thermal-gnd ground v21 vss_thermal thermal-gnd ground v22 vss_thermal thermal-gnd ground v30 vdd10 cpwr power v31 pex_lane_good27# o lane status v32 n/c reserved no connect v33 hp_clken11# o hot plug v34 n/c reserved no connect w1 hp_button0# i, pu hot plug w2 hp_clken9# o hot plug w3 pex_lane_good5# o lane status w4 pex_lane_good18# o lane status w5 vss gnd ground w13 vss_thermal thermal-gnd ground w14 vss_thermal thermal-gnd ground w15 vss_thermal thermal-gnd ground w16 vss_thermal thermal-gnd ground w17 vss_thermal thermal-gnd ground w18 vss_thermal thermal-gnd ground w19 vss_thermal thermal-gnd ground w20 vss_thermal thermal-gnd ground w21 vss_thermal thermal-gnd ground w22 vss_thermal thermal-gnd ground w30 vss gnd ground w31 pex_lane_good28# o lane status w32 n/c reserved no connect w33 hp_pwrled11# o hot plug w34 n/c reserved no connect y1 hp_atnled0# o hot plug y2 hp_pwrled9# o hot plug y3 pex_lane_good6# o lane status table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 58 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 y4 pex_lane_good17# o lane status y5 vdd33 i/opwr power y13 vss_thermal thermal-gnd ground y14 vss_thermal thermal-gnd ground y15 vss_thermal thermal-gnd ground y16 vss_thermal thermal-gnd ground y17 vss_thermal thermal-gnd ground y18 vss_thermal thermal-gnd ground y19 vss_thermal thermal-gnd ground y20 vss_thermal thermal-gnd ground y21 vss_thermal thermal-gnd ground y22 vss_thermal thermal-gnd ground y30 vdd33 i/opwr power y31 pex_lane_good29# o lane status y32 n/c reserved no connect y33 hp_perst11# o hot plug y34 n/c reserved no connect aa1 hp_mrl0# i, pu hot plug aa2 hp_perst9# o hot plug aa3 pex_lane_good7# o lane status aa4 pex_lane_good16# o lane status aa5 vdd10 cpwr power aa13 vss_thermal thermal-gnd ground aa14 vss_thermal thermal-gnd ground aa15 vss_thermal thermal-gnd ground aa16 vss_thermal thermal-gnd ground aa17 vss_thermal thermal-gnd ground aa18 vss_thermal thermal-gnd ground aa19 vss_thermal thermal-gnd ground aa20 vss_thermal thermal-gnd ground aa21 vss_thermal thermal-gnd ground aa22 vss_thermal thermal-gnd ground aa30 vdd10 cpwr power aa31 pex_lane_good30# o lane status aa32 n/c reserved no connect aa33 hp_prsnt11# i, pu hot plug aa34 n/c reserved no connect table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 59 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 ab1 hp_pwrflt0# i, pu hot plug ab2 hp_prsnt9# i, pu hot plug ab3 n/c reserved no connect ab4 n/c reserved no connect ab5 vdd33 i/opwr power ab13 vss_thermal thermal-gnd ground ab14 vss_thermal thermal-gnd ground ab15 vss_thermal thermal-gnd ground ab16 vss_thermal thermal-gnd ground ab17 vss_thermal thermal-gnd ground ab18 vss_thermal thermal-gnd ground ab19 vss_thermal thermal-gnd ground ab20 vss_thermal thermal-gnd ground ab21 vss_thermal thermal-gnd ground ab22 vss_thermal thermal-gnd ground ab30 vdd33 i/opwr power ab31 pex_lane_good31# o lane status ab32 n/c reserved no connect ab33 hp_pwren11# o hot plug ab34 n/c reserved no connect ac1 hp_pwren0# o hot plug ac2 hp_pwren9# o hot plug ac3 n/c reserved no connect ac4 n/c reserved no connect ac5 vdd10 cpwr power ac30 vdd10 cpwr power ac31 strap_stn0_portcfg3 i strap strapping ball ? tie high or low, as defined in strap_stn0_portcfg[4:0] ac32 strap_stn0_portcfg4 i strap ac33 hp_pwrflt11# i, pu hot plug ac34 n/c reserved no connect table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 60 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 ad1 hp_prsnt0# i, pu hot plug ad2 hp_pwrflt9# i, pu hot plug ad3 n/c reserved no connect ad4 n/c reserved no connect ad5 vss gnd ground ad30 vss gnd ground ad31 strap_stn0_portcfg1 i strap strapping ball ? tie high or low, as defined in strap_stn0_portcfg[4:0] ad32 strap_stn0_portcfg2 i strap ad33 hp_mrl11# i, pu hot plug ad34 n/c reserved no connect ae1 hp_perst0# o hot plug ae2 hp_mrl9# i, pu hot plug ae3 n/c reserved no connect ae4 n/c reserved no connect ae5 vdd10 cpwr power ae30 vdd10 cpwr power ae31 n/c reserved no connect ae32 strap_stn0_portcfg0 i strap strapping ball ? tie high or low, as defined in strap_stn0_portcfg[4:0] ae33 hp_atnled11# o hot plug ae34 n/c reserved no connect af1 hp_pwrled0# o hot plug af2 hp_atnled9# o hot plug af3 n/c reserved no connect af4 n/c reserved no connect af5 vdd33 i/opwr power af30 vdd33 i/opwr power af31 n/c reserved no connect af32 n/c reserved no connect af33 hp_button11# i, pu hot plug af34 n/c reserved no connect ag1 hp_clken0# o hot plug ag2 hp_button9# i, pu hot plug ag3 n/c reserved no connect ag4 vss gnd ground ag5 vdd10 cpwr power ag30 vdd10 cpwr power table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 61 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 ag31 vdd33 i/opwr power ag32 ee_cs# o serial eeprom ag33 ee_sk o serial eeprom ag34 ee_do i, pu serial eeprom connecte d to data output of serial eeprom ah1 vdd33 i/opwr power ah2 strap_factory_test1# i strap strapping ball ? tie high ah3 n/c reserved no connect ah4 vssa_pll pll_gnd ground anal og gnd for pll circuit ah5 vdd33a pllpwr power ah30 vdd33 i/opwr power ah31 vss gnd ground ah32 n/c reserved no connect ah33 ee_pr# i serial eeprom ah34 ee_di o serial eeprom connected to data input of serial eeprom aj1 vss gnd ground aj2 vss gnd ground aj3 vss gnd ground aj4 vss gnd ground aj5 vdd10a apwr power aj30 vdd10 cpwr power aj31 vss gnd ground aj32 vss gnd ground aj33 vdd10s spwr power aj34 vss gnd ground table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 62 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 ak1 vss gnd ground ak2 vss gnd ground ak3 vss gnd ground ak4 pex_pern0 cmlrn serdes ak5 vdd10s spwr power ak6 pex_pern1 cmlrn serdes ak7 vdd10a apwr power ak8 pex_pern2 cmlrn serdes ak9 vdd10 cpwr power ak10 pex_pern3 cmlrn serdes ak11 vdd10 cpwr power ak12 pex_pern4 cmlrn serdes ak13 vdd10 cpwr power ak14 pex_pern5 cmlrn serdes ak15 vdd10a apwr power ak16 pex_pern6 cmlrn serdes ak17 vdd10 cpwr power ak18 pex_pern7 cmlrn serdes ak19 vdd10 cpwr power ak20 n/c reserved no connect ak21 vdd10 cpwr power ak22 n/c reserved no connect ak23 vdd10 cpwr power ak24 n/c reserved no connect ak25 vdd10 cpwr power ak26 n/c reserved no connect ak27 vdd10 cpwr power ak28 n/c reserved no connect ak29 vdd10 cpwr power ak30 n/c reserved no connect ak31 vdd10s spwr power ak32 n/c reserved no connect ak33 vdd10s spwr power ak34 n/c reserved no connect table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 63 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 al1 pex_refclkn cmlclkn serdes / clock al2 pex_refclkp cmlclkp serdes / clock al3 vss gnd ground al4 pex_perp0 cmlrp serdes al5 vss gnd ground al6 pex_perp1 cmlrp serdes al7 vss gnd ground al8 pex_perp2 cmlrp serdes al9 vss gnd ground al10 pex_perp3 cmlrp serdes al11 vss gnd ground al12 pex_perp4 cmlrp serdes al13 vss gnd ground al14 pex_perp5 cmlrp serdes al15 vss gnd ground al16 pex_perp6 cmlrp serdes al17 vss gnd ground al18 pex_perp7 cmlrp serdes al19 vss gnd ground al20 n/c reserved no connect al21 vss gnd ground al22 n/c reserved no connect al23 vss gnd ground al24 n/c reserved no connect al25 vss gnd ground al26 n/c reserved no connect al27 vss gnd ground al28 n/c reserved no connect al29 vss gnd ground al30 n/c reserved no connect al31 vss gnd ground al32 n/c reserved no connect al33 vss gnd ground al34 n/c reserved no connect table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 64 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 am1 vss gnd ground am2 vss gnd ground am3 vdd10s spwr power am4 vss gnd ground am5 vss gnd ground am6 vss gnd ground am7 vdd10s spwr power am8 vss gnd ground am9 vss gnd ground am10 vss gnd ground am11 vdd10s spwr power am12 vss gnd ground am13 vss gnd ground am14 vss gnd ground am15 vdd10s spwr power am16 vss gnd ground am17 vss gnd ground am18 vss gnd ground am19 vdd10s spwr power am20 vss gnd ground am21 vss gnd ground am22 vss gnd ground am23 vdd10s spwr power am24 vss gnd ground am25 vss gnd ground am26 vss gnd ground am27 vdd10s spwr power am28 vss gnd ground am29 vss gnd ground am30 vss gnd ground am31 vdd10s spwr power am32 vss gnd ground am33 vss gnd ground am34 vss gnd ground table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 65 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 an1 n/c reserved no connect an2 n/c reserved no connect an3 vdd10s spwr power an4 pex_petp0 cmltp serdes an5 vdd10s spwr power an6 pex_petp1 cmltp serdes an7 vdd10s spwr power an8 pex_petp2 cmltp serdes an9 vdd10s spwr power an10 pex_petp3 cmltp serdes an11 vdd10s spwr power an12 pex_petp4 cmltp serdes an13 vdd10s spwr power an14 pex_petp5 cmltp serdes an15 vdd10s spwr power an16 pex_petp6 cmltp serdes an17 vdd10s spwr power an18 pex_petp7 cmltp serdes an19 vdd10s spwr power an20 n/c reserved no connect an21 vdd10s spwr power an22 n/c reserved no connect an23 vdd10s spwr power an24 n/c reserved no connect an25 vdd10s spwr power an26 n/c reserved no connect an27 vdd10s spwr power an28 n/c reserved no connect an29 vdd10s spwr power an30 n/c reserved no connect an31 vdd10s spwr power an32 n/c reserved no connect an33 vdd10s spwr power an34 n/c reserved no connect table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 66 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 ap1 n/c reserved no connect ap2 n/c reserved no connect ap3 vss gnd ground ap4 pex_petn0 cmltn serdes ap5 vtt_pex0 supply power ap6 pex_petn1 cmltn serdes ap7 vss gnd ground ap8 pex_petn2 cmltn serdes ap9 vtt_pex1 supply power ap10 pex_petn3 cmltn serdes ap11 vss gnd ground ap12 pex_petn4 cmltn serdes ap13 vtt_pex2 supply power ap14 pex_petn5 cmltn serdes ap15 vss gnd ground ap16 pex_petn6 cmltn serdes ap17 vtt_pex3 supply power ap18 pex_petn7 cmltn serdes ap19 vss gnd ground ap20 n/c reserved no connect ap21 vtt_pex4 supply power ap22 n/c reserved no connect ap23 vss gnd ground ap24 n/c reserved no connect ap25 vtt_pex5 supply power ap26 n/c reserved no connect ap27 vss gnd ground ap28 n/c reserved no connect ap29 vtt_pex6 supply power ap30 n/c reserved no connect ap31 vss gnd ground ap32 n/c reserved no connect ap33 vtt_pex7 supply power ap34 n/c reserved no connect table 3-18. pex 8524vaa/bb/bc switch ball assignments by number ? 680-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 67 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga pex 8524 balls description num name type signal group a1 vss gnd ground a2 pex_petn16 cmltn serdes a3 vss gnd ground a4 pex_petn17 cmltn serdes a5 vss gnd ground a6 pex_petn18 cmltn serdes a7 vdd10s spwr power a8 pex_petn19 cmltn serdes a9 vss gnd ground a10 pex_petn20 cmltn serdes a11 vdd10s spwr power a12 pex_petn21 cmltn serdes a13 vss gnd ground a14 pex_petn22 cmltn serdes a15 vdd10s spwr power a16 pex_petn23 cmltn serdes a17 vss gnd ground a18 pex_petn24 cmltn serdes a19 vdd10s spwr power a20 pex_petn25 cmltn serdes a21 vss gnd ground a22 pex_petn26 cmltn serdes a23 vdd10s spwr power a24 pex_petn27 cmltn serdes a25 vss gnd ground a26 pex_petn28 cmltn serdes a27 vdd10s spwr power a28 pex_petn29 cmltn serdes a29 vss gnd ground a30 pex_petn30 cmltn serdes b1 vdd10s spwr power b2 pex_petp16 cmltp serdes b3 vdd10s spwr power b4 pex_petp17 cmltp serdes b5 vdd10s spwr power b6 pex_petp18 cmltp serdes b7 vss gnd ground
signal ball description plx technology, inc. 68 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 b8 pex_petp19 cmltp serdes b9 vdd10s spwr power b10 pex_petp20 cmltp serdes b11 vss gnd ground b12 pex_petp21 cmltp serdes b13 vdd10s spwr power b14 pex_petp22 cmltp serdes b15 vss gnd ground b16 pex_petp23 cmltp serdes b17 vdd10s spwr power b18 pex_petp24 cmltp serdes b19 vss gnd ground b20 pex_petp25 cmltp serdes b21 vdd10s spwr power b22 pex_petp26 cmltp serdes b23 vss gnd ground b24 pex_petp27 cmltp serdes b25 vdd10s spwr power b26 pex_petp28 cmltp serdes b27 vss gnd ground b28 pex_petp29 cmltp serdes b29 vdd10s spwr power b30 pex_petp30 cmltp serdes c1 vss gnd ground c2 vss gnd ground c3 vdd10s spwr power c4 vss gnd ground c5 vdd10s spwr power c6 vss gnd ground c7 vdd10s spwr power c8 vss gnd ground c9 vss gnd ground c10 vss gnd ground c11 vdd10s spwr power c12 vss gnd ground c13 vss gnd ground c14 vss gnd ground table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 69 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 c15 vdd10s spwr power c16 vss gnd ground c17 vss gnd ground c18 vss gnd ground c19 vdd10s spwr power c20 vss gnd ground c21 vss gnd ground c22 vss gnd ground c23 vss gnd ground c24 vss gnd ground c25 vss gnd ground c26 vss gnd ground c27 vdd10s spwr power c28 vss gnd ground c29 vss gnd ground c30 vss gnd ground d1 vdd10s spwr power d2 pex_perp16 cmlrp serdes d3 vss gnd ground d4 pex_perp17 cmlrp serdes d5 vss gnd ground d6 pex_perp18 cmlrp serdes d7 vss gnd ground d8 pex_perp19 cmlrp serdes d9 vss gnd ground d10 pex_perp20 cmlrp serdes d11 vss gnd ground d12 pex_perp21 cmlrp serdes d13 vss gnd ground d14 pex_perp22 cmlrp serdes d15 vss gnd ground d16 pex_perp23 cmlrp serdes d17 vss gnd ground d18 pex_perp24 cmlrp serdes d19 vss gnd ground d20 pex_perp25 cmlrp serdes d21 vss gnd ground table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 70 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 d22 pex_perp26 cmlrp serdes d23 vdd10s spwr power d24 pex_perp27 cmlrp serdes d25 vss gnd ground d26 pex_perp28 cmlrp serdes d27 vss gnd ground d28 pex_perp29 cmlrp serdes d29 vss gnd ground d30 pex_perp30 cmlrp serdes e1 vss gnd ground e2 pex_pern16 cmlrn serdes e3 vdd10s spwr power e4 pex_pern17 cmlrn serdes e5 vdd10s spwr power e6 pex_pern18 cmlrn serdes e7 vdd10a apwr power e8 pex_pern19 cmlrn serdes e9 vtt_pex9 supply power e10 pex_pern20 cmlrn serdes e11 vtt_pex10 supply power e12 pex_pern21 cmlrn serdes e13 vdd10s spwr power e14 pex_pern22 cmlrn serdes e15 vdd10a apwr power e16 pex_pern23 cmlrn serdes e17 vtt_pex11 supply power e18 pex_pern24 cmlrn serdes e19 vtt_pex12 supply power e20 pex_pern25 cmlrn serdes e21 vtt_pex13 supply power e22 pex_pern26 cmlrn serdes e23 vdd10a apwr power e24 pex_pern27 cmlrn serdes e25 vtt_pex14 supply power e26 pex_pern28 cmlrn serdes e27 vdd10s spwr power e28 pex_pern29 cmlrn serdes table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 71 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 e29 vdd10s spwr power e30 pex_pern30 cmlrn serdes f1 vss gnd ground f2 vdd10s spwr power f3 vss gnd ground f4 vtt_pex8 supply power f5 vss gnd ground f26 vdd10a apwr power f27 vss gnd ground f28 vdd10s spwr power f29 vss gnd ground f30 vdd10s spwr power g1 strap_mode_sel0 i strap strapping ball ? tie high or low, as defined in strap_mode_sel[1:0] g2 strap_mode_sel1 i strap g3 pex_perst# i pex control g4 jtag_tms i, pu jtag g5 vss gnd ground g26 pex_pern31 cmlrn serdes g27 pex_perp31 cmlrp serdes g28 vss gnd ground g29 pex_petp31 cmltp serdes g30 pex_petn31 cmltn serdes h1 jtag_tdo o jtag h2 jtag_tck i, pu jtag h3 pex_nt_reset# o pex control h4 jtag_trst# i, pu jtag h5 vdd33 i/opwr power h26 vtt_pex15 supply power h27 vdd10s spwr power h28 vss gnd ground h29 vdd10s spwr power h30 vss gnd ground j1 jtag_tdi i, pu jtag j2 hp_clken8# o hot plug j3 hp_button1# i, pu hot plug j4 hp_pwrled8# o hot plug j5 vss gnd ground table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 72 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 j26 vdd33 i/opwr power j27 strap_testmode2 i strap strapping ball ? tie high or low, as defined in strap_testmode[3:0] j28 strap_testmode3 i strap j29 strap_testmode0 i strap j30 strap_testmode1 i strap k1 hp_atnled1# o hot plug k2 strap_upstrm_portsel2 i strap strapping ball ? tie high or low, as defined in strap_upstrm_portsel[3:0] k3 strap_upstrm_portsel0 i strap k4 hp_perst8# o hot plug k5 vdd33 i/opwr power k10 vdd10 cpwr power k11 vdd10 cpwr power k12 vdd10 cpwr power k13 vdd10 cpwr power k14 vdd10 cpwr power k15 vdd10 cpwr power k16 vdd10 cpwr power k17 vdd10 cpwr power k18 vdd10 cpwr power k19 vdd10 cpwr power k20 vdd10 cpwr power k21 vdd10 cpwr power k26 vss gnd ground k27 hp_pwrled10# o hot plug k28 strap_nt_upstrm_portsel0 i strap strapping ball ? tie high or low, as defined in strap_nt_upstrm_portsel[3:0] k29 n/c reserved no connect k30 hp_clken10# o hot plug l1 hp_mrl1# i, pu hot plug l2 strap_upstrm_portsel3 i strap strapping ball ? tie high or low, as defined in strap_upstrm_portsel[3:0] l3 strap_upstrm_portsel1 i strap l4 hp_prsnt8# i, pu hot plug l5 vss gnd ground l10 vdd10 cpwr power l11 vss_thermal thermal-gnd ground l12 vss_thermal thermal-gnd ground l13 vss_thermal thermal-gnd ground table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 73 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 l14 vss_thermal thermal-gnd ground l15 vss_thermal thermal-gnd ground l16 vss_thermal thermal-gnd ground l17 vss_thermal thermal-gnd ground l18 vss_thermal thermal-gnd ground l19 vss_thermal thermal-gnd ground l20 vss_thermal thermal-gnd ground l21 vdd10 cpwr power l26 vdd33 i/opwr power l27 hp_perst10# o hot plug l28 strap_nt_upstrm_portsel1 i strap strapping ball ? tie high or low, as defined in strap_nt_upstrm_portsel[3:0] l29 strap_nt_upstrm_portsel2 i strap l30 n/c reserved no connect m1 hp_pwrflt1# i, pu hot plug m2 pex_lane_good23# o lane status m3 pex_lane_good0# o lane status m4 hp_pwren8# o hot plug m5 vdd33 i/opwr power m10 vdd10 cpwr power m11 vss_thermal thermal-gnd ground m12 vss_thermal thermal-gnd ground m13 vss_thermal thermal-gnd ground m14 vss_thermal thermal-gnd ground m15 vss_thermal thermal-gnd ground m16 vss_thermal thermal-gnd ground m17 vss_thermal thermal-gnd ground m18 vss_thermal thermal-gnd ground m19 vss_thermal thermal-gnd ground m20 vss_thermal thermal-gnd ground m21 vdd10 cpwr power m26 vss gnd ground m27 hp_prsnt10# i, pu hot plug m28 strap_stn1_portcfg0 i strap strapping ball ? tie high or low, as defined in strap_stn1_portcfg[3:0] m29 strap_nt_upstrm_portsel3 i strap strapping ball ? tie high or low, as defined in strap_nt_upstrm_portsel[3:0] m30 n/c reserved no connect n1 hp_pwren1# o hot plug table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 74 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 n2 pex_lane_good22# o lane status n3 pex_lane_good1# o lane status n4 hp_pwrflt8# i, pu hot plug n5 vss gnd ground n10 vdd10 cpwr power n11 vss_thermal thermal-gnd ground n12 vss_thermal thermal-gnd ground n13 vss_thermal thermal-gnd ground n14 vss_thermal thermal-gnd ground n15 vss_thermal thermal-gnd ground n16 vss_thermal thermal-gnd ground n17 vss_thermal thermal-gnd ground n18 vss_thermal thermal-gnd ground n19 vss_thermal thermal-gnd ground n20 vss_thermal thermal-gnd ground n21 vdd10 cpwr power n26 vdd33 i/opwr power n27 hp_pwren10# o hot plug n28 strap_stn1_portcfg2 i strap strapping ball ? tie high or low, as defined in strap_stn1_portcfg[3:0] n29 strap_stn1_portcfg1 i strap n30 n/c reserved no connect p1 hp_prsnt1# i, pu hot plug p2 pex_lane_good2# o lane status p3 hp_mrl8# i, pu hot plug p4 hp_perst1# o hot plug p5 vdd33 i/opwr power p10 vdd10 cpwr power p11 vss_thermal thermal-gnd ground p12 vss_thermal thermal-gnd ground p13 vss_thermal thermal-gnd ground p14 vss_thermal thermal-gnd ground p15 vss_thermal thermal-gnd ground p16 vss_thermal thermal-gnd ground p17 vss_thermal thermal-gnd ground p18 vss_thermal thermal-gnd ground p19 vss_thermal thermal-gnd ground p20 vss_thermal thermal-gnd ground table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 75 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 p21 vdd10 cpwr power p26 vss gnd ground p27 n/c reserved no connect p28 hp_pwrflt10# i, pu hot plug p29 strap_stn1_portcfg3 i strap strapping ball ? tie high or low, as defined in strap_stn1_portcfg[3:0] p30 n/c reserved no connect r1 pex_lane_good20# o lane status r2 pex_lane_good3# o lane status r3 hp_atnled8# o hot plug r4 hp_pwrled1# o hot plug r5 vss gnd ground r10 vdd10 cpwr power r11 vss_thermal thermal-gnd ground r12 vss_thermal thermal-gnd ground r13 vss_thermal thermal-gnd ground r14 vss_thermal thermal-gnd ground r15 vss_thermal thermal-gnd ground r16 vss_thermal thermal-gnd ground r17 vss_thermal thermal-gnd ground r18 vss_thermal thermal-gnd ground r19 vss_thermal thermal-gnd ground r20 vss_thermal thermal-gnd ground r21 vdd10 cpwr power r26 vdd33 i/opwr power r27 n/c reserved no connect r28 hp_mrl10# i, pu hot plug r29 n/c reserved no connect r30 pex_lane_good24# o lane status t1 pex_lane_good4# o lane status t2 hp_button8# i, pu hot plug t3 hp_clken1# o hot plug t4 hp_button0# i, pu hot plug t5 vdd33 i/opwr power t10 vdd10 cpwr power t11 vss_thermal thermal-gnd ground t12 vss_thermal thermal-gnd ground t13 vss_thermal thermal-gnd ground table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 76 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 t14 vss_thermal thermal-gnd ground t15 vss_thermal thermal-gnd ground t16 vss_thermal thermal-gnd ground t17 vss_thermal thermal-gnd ground t18 vss_thermal thermal-gnd ground t19 vss_thermal thermal-gnd ground t20 vss_thermal thermal-gnd ground t21 vdd10 cpwr power t26 vss gnd ground t27 n/c reserved no connect t28 hp_atnled10# o hot plug t29 n/c reserved no connect t30 pex_lane_good25# o lane status u1 hp_clken9# o hot plug u2 pex_lane_good5# o lane status u3 pex_lane_good18# o lane status u4 hp_atnled0# o hot plug u5 vss gnd ground u10 vdd10 cpwr power u11 vss_thermal thermal-gnd ground u12 vss_thermal thermal-gnd ground u13 vss_thermal thermal-gnd ground u14 vss_thermal thermal-gnd ground u15 vss_thermal thermal-gnd ground u16 vss_thermal thermal-gnd ground u17 vss_thermal thermal-gnd ground u18 vss_thermal thermal-gnd ground u19 vss_thermal thermal-gnd ground u20 vss_thermal thermal-gnd ground u21 vdd10 cpwr power u26 vdd33 i/opwr power u27 n/c reserved no connect u28 hp_button10# i, pu hot plug u29 n/c reserved no connect u30 pex_lane_good26# o lane status v1 hp_pwrled9# o hot plug table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 77 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 v2 pex_lane_good6# o lane status v3 hp_mrl0# i, pu hot plug v4 hp_perst9# o hot plug v5 vdd33 i/opwr power v10 vdd10 cpwr power v11 vss_thermal thermal-gnd ground v12 vss_thermal thermal-gnd ground v13 vss_thermal thermal-gnd ground v14 vss_thermal thermal-gnd ground v15 vss_thermal thermal-gnd ground v16 vss_thermal thermal-gnd ground v17 vss_thermal thermal-gnd ground v18 vss_thermal thermal-gnd ground v19 vss_thermal thermal-gnd ground v20 vss_thermal thermal-gnd ground v21 vdd10 cpwr power v26 vss gnd ground v27 pex_lane_good27# o lane status v28 n/c reserved no connect v29 hp_clken11# o hot plug v30 n/c reserved no connect w1 pex_lane_good7# o lane status w2 pex_lane_good16# o lane status w3 hp_pwrflt0# i, pu hot plug w4 hp_prsnt9# i, pu hot plug w5 vss gnd ground w10 vdd10 cpwr power table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 78 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 w11 vss_thermal thermal-gnd ground w12 vss_thermal thermal-gnd ground w13 vss_thermal thermal-gnd ground w14 vss_thermal thermal-gnd ground w15 vss_thermal thermal-gnd ground w16 vss_thermal thermal-gnd ground w17 vss_thermal thermal-gnd ground w18 vss_thermal thermal-gnd ground w19 vss_thermal thermal-gnd ground w20 vss_thermal thermal-gnd ground w21 vdd10 cpwr power w26 vdd33 i/opwr power w27 pex_lane_good28# o lane status w28 n/c reserved no connect w29 hp_pwrled11# o hot plug w30 n/c reserved no connect y1 hp_pwren0# o hot plug y2 hp_pwren9# o hot plug y3 n/c reserved no connect y4 hp_prsnt0# i, pu hot plug y5 vdd33 i/opwr power y10 vdd10 cpwr power y11 vss_thermal thermal-gnd ground y12 vss_thermal thermal-gnd ground y13 vss_thermal thermal-gnd ground y14 vss_thermal thermal-gnd ground y15 vss_thermal thermal-gnd ground y16 vss_thermal thermal-gnd ground y17 vss_thermal thermal-gnd ground y18 vss_thermal thermal-gnd ground y19 vss_thermal thermal-gnd ground y20 vss_thermal thermal-gnd ground y21 vdd10 cpwr power y26 vss gnd ground y27 pex_lane_good29# o lane status y28 n/c reserved no connect y29 hp_perst11# o hot plug table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 79 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 y30 n/c reserved no connect aa1 hp_pwrflt9# i, pu hot plug aa2 n/c reserved no connect aa3 hp_perst0# o hot plug aa4 hp_mrl9# i, pu hot plug aa5 vss gnd ground aa10 vdd10 cpwr power aa11 vdd10 cpwr power aa12 vdd10 cpwr power aa13 vdd10 cpwr power aa14 vdd10 cpwr power aa15 vdd10 cpwr power aa16 vdd10 cpwr power aa17 vdd10 cpwr power aa18 vdd10 cpwr power aa19 vdd10 cpwr power aa20 vdd10 cpwr power aa21 vdd10 cpwr power aa26 vdd33 i/opwr power aa27 pex_lane_good30# o lane status aa28 n/c reserved no connect aa29 hp_prsnt11# i, pu hot plug aa30 n/c reserved no connect ab1 hp_pwrled0# o hot plug ab2 hp_atnled9# o hot plug ab3 n/c reserved no connect ab4 hp_clken0# o hot plug ab5 vdd33 i/opwr power ab26 vss gnd ground ab27 pex_lane_good31# o lane status ab28 n/c reserved no connect ab29 hp_pwren11# o hot plug ab30 n/c reserved no connect ac1 hp_button9# i, pu hot plug ac2 n/c reserved no connect table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 80 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 ac3 strap_factory_test1# i stra p strapping ball ? tie high ac4 vssa_pll pll_gnd ground an alog gnd for pll circuit ac5 vss gnd ground ac26 vdd33 i/opwr power ac27 strap_stn0_portcfg3 i strap strapping ball ? tie high or low, as defined in strap_stn0_portcfg[4:0] ac28 strap_stn0_portcfg4 i strap ac29 hp_pwrflt11# i, pu hot plug ac30 n/c reserved no connect ad1 pex_lane_good17# o lane status ad2 pex_lane_good21# o lane status ad3 pex_lane_good19# o lane status ad4 vss gnd ground ad5 vss gnd ground ad26 vss gnd ground ad27 strap_stn0_portcfg1 i strap strapping ball ? tie high or low, as defined in strap_stn0_portcfg[4:0] ad28 strap_stn0_portcfg2 i strap ad29 hp_mrl11# i, pu hot plug ad30 n/c reserved no connect ae1 n/c reserved no connect ae2 n/c reserved no connect ae3 vdd33 i/opwr power ae4 vss gnd ground ae5 vss gnd ground ae26 vdd33 i/opwr power ae27 n/c reserved no connect ae28 strap_stn0_portcfg0 i strap strapping ball ? tie high or low, as defined in strap_stn0_portcfg[4:0] ae29 hp_atnled11# o hot plug ae30 n/c reserved no connect af1 vdd33a pllpwr power af2 nc_procmon reserved no connect af3 vdd33 i/opwr power af4 vss gnd ground af5 vss gnd ground af6 pex_pern0 cmlrn serdes af7 vtt_pex0 supply power table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 81 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 af8 pex_pern1 cmlrn serdes af9 vtt_pex1 supply power af10 pex_perp2 cmlrp serdes af11 vdd10a apwr power af12 pex_pern3 cmlrn serdes af13 vss gnd ground af14 pex_pern4 cmlrn serdes af15 vtt_pex2 supply power af16 pex_pern5 cmlrn serdes af17 vdd10a apwr power af18 pex_pern6 cmlrn serdes af19 vtt_pex3 supply power af20 pex_pern7 cmlrn serdes af21 vdd10a apwr power af22 vss gnd ground af23 vdd10s spwr power af24 vss gnd ground af25 vdd10s spwr power af26 vss gnd ground af27 n/c reserved no connect af28 n/c reserved no connect af29 hp_button11# i, pu hot plug af30 n/c reserved no connect ag1 vss gnd ground ag2 vdd10s spwr power ag3 vss gnd ground ag4 vss gnd ground ag5 vss gnd ground ag6 pex_perp0 cmlrp serdes ag7 vss gnd ground ag8 pex_perp1 cmlrp serdes ag9 vdd10s spwr power ag10 pex_pern2 cmlrn serdes ag11 vss gnd ground ag12 pex_perp3 cmlrp serdes ag13 vdd10s spwr power ag14 pex_perp4 cmlrp serdes table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 82 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 ag15 vss gnd ground ag16 pex_perp5 cmlrp serdes ag17 vdd10s spwr power ag18 pex_perp6 cmlrp serdes ag19 vss gnd ground ag20 pex_perp7 cmlrp serdes ag21 vss gnd ground ag22 vdd10s spwr power ag23 vss gnd ground ag24 vdd10s spwr power ag25 vss gnd ground ag26 vdd33 i/opwr power ag27 ee_di o serial eeprom connected to data input of serial eeprom ag28 ee_cs# o serial eeprom ag29 ee_sk o serial eeprom ag30 ee_do i, pu serial eeprom connected to data output of serial eeprom ah1 vdd10s spwr power ah2 vss gnd ground ah3 vdd10s spwr power ah4 vss gnd ground ah5 vss gnd ground ah6 vss gnd ground ah7 vdd10s spwr power ah8 vss gnd ground ah9 vss gnd ground ah10 vss gnd ground ah11 vdd10s spwr power ah12 vss gnd ground ah13 vss gnd ground ah14 vss gnd ground ah15 vdd10s spwr power ah16 vss gnd ground ah17 vss gnd ground ah18 vss gnd ground ah19 vdd10s spwr power ah20 vss gnd ground ah21 vdd10s spwr power table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 ball assignments by number expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 83 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 ah22 vss gnd ground ah23 vdd10s spwr power ah24 vss gnd ground ah25 vdd10s spwr power ah26 vss gnd ground ah27 n/c reserved no connect ah28 ee_pr# i serial eeprom ah29 vdd33 i/opwr power ah30 vss gnd ground aj1 vss gnd ground aj2 vdd10s spwr power aj3 vss gnd ground aj4 pex_refclkp cmlclkp serdes aj5 vdd10s spwr power aj6 pex_petp0 cmltp serdes aj7 vss gnd ground aj8 pex_petp1 cmltp serdes aj9 vdd10s spwr power aj10 pex_petp2 cmltp serdes aj11 vss gnd ground aj12 pex_petp3 cmltp serdes aj13 vdd10s spwr power aj14 pex_petp4 cmltp serdes aj15 vss gnd ground aj16 pex_petp5 cmltp serdes aj17 vss gnd ground aj18 pex_petp6 cmltp serdes aj19 vss gnd ground aj20 pex_petp7 cmltp serdes aj21 vss gnd ground aj22 vdd10s spwr power aj23 vss gnd ground aj24 vdd10s spwr power aj25 vss gnd ground aj26 vdd33 i/opwr power aj27 vss gnd ground aj28 vdd33 i/opwr power table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
signal ball description plx technology, inc. 84 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 aj29 vss gnd ground aj30 vdd33 i/opwr power ak1 vdd10s spwr power ak2 vss gnd ground ak3 vdd10s spwr power ak4 pex_refclkn cmlclkn serdes / clock ak5 vss gnd ground ak6 pex_petn0 cmltn serdes ak7 vdd10s spwr power ak8 pex_petn1 cmltn serdes ak9 vss gnd ground ak10 pex_petn2 cmltn serdes ak11 vdd10s spwr power ak12 pex_petn3 cmltn serdes ak13 vss gnd ground ak14 pex_petn4 cmltn serdes ak15 vdd10s spwr power ak16 pex_petn5 cmltn serdes ak17 vdd10s spwr power ak18 pex_petn6 cmltn serdes ak19 vdd10s spwr power ak20 pex_petn7 cmltn serdes ak21 vdd10s spwr power ak22 vss gnd ground ak23 vdd10s spwr power ak24 vss gnd ground ak25 vdd10s spwr power ak26 vss gnd ground ak27 vdd33 i/opwr power ak28 vss gnd ground ak29 vdd33 i/opwr power ak30 vss gnd ground table 3-19. pex 8524bb/bc switch ball assignments by number ? 644-ball pbga (cont.) pex 8524 balls description num name type signal group
february, 2007 pex 8524 physical layouts expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 85 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 3.7 pex 8524 physical layouts figure 3-1. pex 8524vaa/bb/bc 680-ball physical ball assignment (see-through top view) 12345678910111213141516171819202122232425262728293031323334 a n/c n/c vss pex_petn 16 vtt_pex8 pex_petn 17 vss pex_petn 18 vtt_pex9 pex_petn 19 vss pex_petn 20 vtt_pex1 0 pex_petn 21 vss pex_petn 22 vtt_pex1 1 pex_petn 23 vss pex_petn 24 vtt_pex1 2 pex_petn 25 vss pex_petn 26 vtt_pex1 3 pex_petn 27 vss pex_petn 28 vtt_pex1 4 pex_petn 29 vss pex_petn 30 vtt_pex1 5 pex_petn 31 a b n/c n/c vdd10s pex_petp 16 vdd10s pex_petp 17 vdd10s pex_petp 18 vdd10s pex_petp 19 vdd10s pex_petp 20 vdd10s pex_petp 21 vdd10s pex_petp 22 vdd10s pex_petp 23 vdd10s pex_petp 24 vdd10s pex_petp 25 vdd10s pex_petp 26 vdd10s pex_petp 27 vdd10s pex_petp 28 vdd10s pex_petp 29 vdd10s pex_petp 30 vdd10s pex_petp 31 b c vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss c d pex_perp 16 vss n/c vdd10s vss pex_perp 17 vss pex_perp 18 vss pex_perp 19 vss pex_perp 20 vss pex_perp 21 vss pex_perp 22 vss pex_perp 23 vss pex_perp 24 vss pex_perp 25 vss pex_perp 26 vss pex_perp 27 vss pex_perp 28 vss pex_perp 29 vss pex_perp 30 vss pex_perp 31 d e pex_pern 16 vss n/c vss vdd10s pex_pern 17 vdd10a pex_pern 18 vdd10 pex_pern 19 vdd10 pex_pern 20 vdd10 pex_pern 21 vdd10a pex_pern 22 vdd10 pex_pern 23 vdd10 pex_pern 24 vdd10 pex_pern 25 vdd10a pex_pern 26 vdd10 pex_pern 27 vdd10 pex_pern 28 vdd10 pex_pern 29 vdd10s pex_pern 30 vdd10s pex_pern 31 e f vss vss n/c vss vdd10 vdd10a vss vss vdd10s vss f g strap_m ode_sel0 n/c n/c vss vdd10 vdd10 vss n/c strap_te stmode1 strap_te stmode0 g h pex_pers t# strap_m ode_sel1 n/c n/c vdd33 vss n/c vdd33 strap_te stmode3 strap_te stmode2 h j pex_nt_r eset# jtag_tck jtag_tdo jtag_tms vss vdd10 vdd33 vdd33 hp_clken 10# n/c j k hp_butto n1# hp_clken 8# jtag_tdi jtag_trs t# vdd10 vdd33 vdd33 strap_nt _upstrm_ portsel0 hp_pwrl ed10# n/c k l hp_atnle d1# hp_pwrl ed8# n/c n/c vdd33 vss strap_nt _upstrm_ portsel2 strap_nt _upstrm_ portsel1 hp_perst 10# n/c l m hp_mrl1# hp_perst 8# strap_up strm_po rtsel0 strap_up strm_po rtsel2 vdd10 vdd10 strap_nt _upstrm_ portsel3 strap_st n1_portc fg0 hp_prsnt 10# n/c m n hp_pwrf lt1# hp_prsnt 8# strap_up strm_po rtsel1 strap_up strm_po rtsel3 vdd33 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd33 strap_st n1_portc fg1 strap_st n1_portc fg2 hp_pwre n10# n/c n p hp_pwre n1# hp_pwre n8# pex_lane _good0# pex_lane _good23# vss vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd10 strap_st n1_portc fg3 vss hp_pwrf lt10# n/c p r hp_prsnt 1# hp_pwrf lt8# pex_lane _good1# pex_lane _good22# vdd33 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss pex_lane _good24# n/c hp_mrl10 # n/c r t hp_perst 1# hp_mrl8# pex_lane _good2# pex_lane _good21# vdd10 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd10 pex_lane _good25# n/c hp_atnle d10# n/c t u hp_pwrl ed1# hp_atnle d8# pex_lane _good3# pex_lane _good20# vdd33 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd33 pex_lane _good26# n/c hp_butto n10# n/c u v hp_clken 1# hp_butto n8# pex_lane _good4# pex_lane _good19# vdd10 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd10 pex_lane _good27# n/c hp_clken 11# n/c v w hp_butto n0# hp_clken 9# pex_lane _good5# pex_lane _good18# vss vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss pex_lane _good28# n/c hp_pwrl ed11# n/c w y hp_atnle d0# hp_pwrl ed9# pex_lane _good6# pex_lane _good17# vdd33 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd33 pex_lane _good29# n/c hp_perst 11# n/c y aa hp_mrl0# hp_perst 9# pex_lane _good7# pex_lane _good16# vdd10 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd10 pex_lane _good30# n/c hp_prsnt 11# n/c aa ab hp_pwrf lt0# hp_prsnt 9# n/c n/c vdd33 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd33 pex_lane _good31# n/c hp_pwre n11# n/c ab ac hp_pwre n0# hp_pwre n9# n/c n/c vdd10 vdd10 strap_st n0_portc fg3 strap_st n0_portc fg4 hp_pwrf lt11# n/c ac ad hp_prsnt 0# hp_pwrf lt9# n/c n/c vss vss strap_st n0_portc fg1 strap_st n0_portc fg2 hp_mrl11 # n/c ad ae hp_perst 0# hp_mrl9# n/c n/c vdd10 vdd10 n/c strap_st n0_portc fg0 hp_atnle d11# n/c ae af hp_pwrl ed0# hp_atnle d9# n/c n/c vdd33 vdd33 n/c n/c hp_butto n11# n/c af ag hp_clken 0# hp_butto n9# n/c vss vdd10 vdd10 vdd33 ee_cs# ee_sk ee_do ag ah vdd33 strap_fa ctory_te st1# n/c vssa_pll vdd33a vdd33 vss n/c ee_pr# ee_di ah aj vss vss vss vss vdd10a vdd10 vss vss vdd10s vss aj ak vss vss vss pex_pern 0 vdd10s pex_pern 1 vdd10a pex_pern 2 vdd10 pex_pern 3 vdd10 pex_pern 4 vdd10 pex_pern 5 vdd10a pex_pern 6 vdd10 pex_pern 7 vdd10 n/c vdd10 n/c vdd10 n/c vdd10 n/c vdd10 n/c vdd10 n/c vdd10s n/c vdd10s n/c ak al pex_refc lkn pex_refc lkp vss pex_perp 0 vss pex_perp 1 vss pex_perp 2 vss pex_perp 3 vss pex_perp 4 vss pex_perp 5 vss pex_perp 6 vss pex_perp 7 vss n/c vss n/c vss n/c vss n/c vss n/c vss n/c vss n/c vss n/c al am vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss am an n/c n/c vdd10s pex_petp 0 vdd10s pex_petp 1 vdd10s pex_petp 2 vdd10s pex_petp 3 vdd10s pex_petp 4 vdd10s pex_petp 5 vdd10s pex_petp 6 vdd10s pex_petp 7 vdd10s n/c vdd10s n/c vdd10s n/c vdd10s n/c vdd10s n/c vdd10s n/c vdd10s n/c vdd10s n/c an ap n/c n/c vss pex_petn 0 vtt_pex0 pex_petn 1 vss pex_petn 2 vtt_pex1 pex_petn 3 vss pex_petn 4 vtt_pex2 pex_petn 5 vss pex_petn 6 vtt_pex3 pex_petn 7 vss n/c vdd10 n/c vss n/c vdd10 n/c vss n/c vdd10 n/c vss n/c vdd10 n/c ap 12345678910111213141516171819202122232425262728293031323334 <= pad 1 die up <= pad 1 die up
signal ball description plx technology, inc. 86 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 figure 3-2. pex 8524bb/bc 644-ball pbga physical layout (see-through top view) 123456789101112131415161718192021222324252627282930 a vss pex_petn1 6 vss pex_petn1 7 vss pex_petn1 8 vdd10s pex_petn1 9 vss pex_petn2 0 vdd10s pex_petn2 1 vss pex_petn2 2 vdd10s pex_petn2 3 vss pex_petn2 4 vdd10s pex_petn2 5 vss pex_petn2 6 vdd10s pex_petn2 7 vss pex_petn2 8 vdd10s pex_petn2 9 vss pex_petn3 0 a b vdd10s pex_petp1 6 vdd10s pex_petp1 7 vdd10s pex_petp1 8 vss pex_petp1 9 vdd10s pex_petp2 0 vss pex_petp2 1 vdd10s pex_petp2 2 vss pex_petp2 3 vdd10s pex_petp2 4 vss pex_petp2 5 vdd10s pex_petp2 6 vss pex_petp2 7 vdd10s pex_petp2 8 vss pex_petp2 9 vdd10s pex_petp3 0 b c vss vss vdd10s vss vdd10s vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss vss vss vss vss vdd10s vss vss vss c d vdd10s pex_perp 16 vss pex_perp 17 vss pex_perp 18 vss pex_perp 19 vss pex_perp 20 vss pex_perp 21 vss pex_perp 22 vss pex_perp 23 vss pex_perp 24 vss pex_perp 25 vss pex_perp 26 vdd10s pex_perp 27 vss pex_perp 28 vss pex_perp 29 vss pex_perp 30 d e vss pex_pern 16 vdd10s pex_pern 17 vdd10s pex_pern 18 vdd10a pex_pern 19 vtt_pex9 pex_pern 20 vtt_pex10 pex_pern 21 vdd10s pex_pern 22 vdd10a pex_pern 23 vtt_pex11 pex_pern 24 vtt_pex12 pex_pern 25 vtt_pex13 pex_pern 26 vdd10a pex_pern 27 vtt_pex14 pex_pern 28 vdd10s pex_pern 29 vdd10s pex_pern 30 e f vss vdd10s vss vtt_pex8 vss vdd10a vss vdd10s vss vdd10s f g strap_mo de_sel0 strap_mo de_sel1 pex_pers t# jtag_tms vss pex_pern 31 pex_perp 31 vss pex_petp3 1 pex_petn3 1 g h jtag_tdo jtag_tck pex_nt_r eset# jtag_trs t# vdd33 vtt_pex15 vdd10s vss vdd10s vss h j jtag_tdi hp_clken 8# hp_butto n1# hp_pwrl ed8# vss vdd33 strap_te stmode2 strap_te stmode3 strap_te stmode0 strap_te stmode1 j k hp_atnle d1# strap_up strm_por tsel2 strap_up strm_por tsel0 hp_perst 8# vdd33 vdd10 vdd10 vdd10 vdd10 vdd10 vdd10 vdd10 vdd10 vdd10 vdd10 vdd10 vdd10 vss hp_pwrl ed10# strap_nt _upstrm_ portsel0 n/c hp_clken 10# k l hp_mrl1# strap_up strm_por tsel3 strap_up strm_por tsel1 hp_prsnt 8# vss vdd10 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd10 vdd33 hp_perst 10# strap_nt _upstrm_ portsel1 strap_nt _upstrm_ portsel2 n/c l m hp_pwrfl t1# pex_lane _good23# pex_lane _good0# hp_pwre n8# vdd33 vdd10 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd10 vss hp_prsnt 10# strap_st n1_portc fg0 strap_nt _upstrm_ portsel3 n/c m n hp_pwre n1# pex_lane _good22# pex_lane _good1# hp_pwrfl t8# vss vdd10 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd10 vdd33 hp_pwre n10# strap_st n1_portc fg2 strap_st n1_portc fg1 n/c n p hp_prsnt 1# pex_lane _good2# hp_mrl8# hp_perst 1# vdd33 vdd10 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd10 vss n/c hp_pwrfl t10# strap_st n1_portc fg3 n/c p r pex_lane _good20# pex_lane _good3# hp_atnle d8# hp_pwrl ed1# vss vdd10 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd10 vdd33 n/c hp_mrl10 # n/c pex_lane _good24# r t pex_lane _good4# hp_butto n8# hp_clken 1# hp_butto n0# vdd33 vdd10 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd10 vss n/c hp_atnle d10# n/c pex_lane _good25# t u hp_clken 9# pex_lane _good5# pex_lane _good18# hp_atnle d0# vss vdd10 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd10 vdd33 n/c hp_butto n10# n/c pex_lane _good26# u v hp_pwrl ed9# pex_lane _good6# hp_mrl0# hp_perst 9# vdd33 vdd10 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd10 vss pex_lane _good27# n/c hp_clken 11# n/c v w pex_lane _good7# pex_lane _good16# hp_pwrfl t0# hp_prsnt 9# vss vdd10 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd10 vdd33 pex_lane _good28# n/c hp_pwrl ed11# n/c w y hp_pwre n0# hp_pwre n9# n/c hp_prsnt 0# vdd33 vdd10 vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vss_ther mal vdd10 vss pex_lane _good29# n/c hp_perst 11# n/c y aa hp_pwrfl t9# n/c hp_perst 0# hp_mrl9# vss vdd10 vdd10 vdd10 vdd10 vdd10 vdd10 vdd10 vdd10 vdd10 vdd10 vdd10 vdd10 vdd33 pex_lane _good30# n/c hp_prsnt 11# n/c aa ab hp_pwrl ed0# hp_atnle d9# n/c hp_clken 0# vdd33 vss pex_lane _good31# n/c hp_pwre n11# n/c ab ac hp_butto n9# n/c strap_fa ctory_te st1# vssa_pll vss vdd33 strap_st n0_portc fg3 strap_st n0_portc fg4 hp_pwrfl t11# n/c ac ad pex_lane _good17# pex_lane _good21# pex_lane _good19# vss vss vss strap_st n0_portc fg1 strap_st n0_portc fg2 hp_mrl11 # n/c ad ae n/c n/c vdd33 vss vss vdd33 n/c strap_st n0_portc fg0 hp_atnle d11# n/c ae af vdd33a nc_proc mon vdd33 vss vss pex_pern 0 vtt_pex0 pex_pern 1 vtt_pex1 pex_perp 2 vdd10a pex_pern 3 vss pex_pern 4 vtt_pex2 pex_pern 5 vdd10a pex_pern 6 vtt_pex3 pex_pern 7 vdd10a vss vdd10s vss vdd10s vss n/c n/c hp_butto n11# n/c af ag vss vdd10s vss vss vss pex_perp 0 vss pex_perp 1 vdd10s pex_pern 2 vss pex_perp 3 vdd10s pex_perp 4 vss pex_perp 5 vdd10s pex_perp 6 vss pex_perp 7 vss vdd10s vss vdd10s vss vdd33 ee_di ee_cs# ee_sk ee_do ag ah vdd10s vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vss vss vdd10s vss vdd10s vss vdd10s vss vdd10s vss n/c ee_pr# vdd33 vss ah aj vss vdd10s vss pex_refc lkp vdd10s pex_petp0 vss pex_petp1 vdd10s pex_petp2 vss pex_petp3 vdd10s pex_petp4 vss pex_petp5 vss pex_petp6 vss pex_petp7 vss vdd10s vss vdd10s vss vdd33 vss vdd33 vss vdd33 aj ak vdd10s vss vdd10s pex_refc lkn vss pex_petn0 vdd10s pex_petn1 vss pex_petn2 vdd10s pex_petn3 vss pex_petn4 vdd10s pex_petn5 vdd10s pex_petn6 vdd10s pex_petn7 vdd10s vss vdd10s vss vdd10s vss vdd33 vss vdd33 vss ak 123456789101112131415161718192021222324252627282930 <= pad 1 die up
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 87 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 4 functional overview 4.1 pex 8524 architecture the pex 8524 switch is designed with a flexible, modular architecture. the two main building blocks of this architecture are the non-blocking crossbar switch fabric (internal fabric) and protocol-specific i/o module, termed station . figure 4-1 illustrates a block diagram of the pex 8524. figure 4-1. pex 8524 block diagram 4.1.1 ingress and egress functions the crossbar switch ingress queue interfaces the pci express station to the internal fabric. the queue contains a centralized packet bu ffer for incoming ports, ingress port scheduler, and internal fabric scheduler. the crossbar switch egress queue interfaces the n on-blocking internal fabric to the pci express station. the queue contains a cen tralized packet buffer for al l outgoing ports and the egress port scheduler. all ingress traffic flows from the pci express stat ion by way of the crossbar switch ingress queue, internal fabric, crossbar switch eg ress queue, and finally to the outgoing pci express station. ingress and egress scheduler modules contain a virtual channel (vc) scheduler for each port. the ingress scheduler supports a port-width-based arbitra tion scheme. the egress scheduler supports a device-specific port arbitration scheme, to avoid port starvation. pci express upstream station 0 crossbar switch ingress crossbar switch egress internal fabric pci express downstream station 1 crossbar switch egress crossbar switch ingress port 0 ingress scheduler egress scheduler ingress scheduler egress scheduler station 0 lanes lanes station 1
functional overview plx technology, inc. 88 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4.1.2 station and port functions each port implements the pci express base r1.0a physical, data link, and transaction layers. station 0 can support up to 8 inte grated serializer/de-serializer (serdes) modules, and station 1 can support up to 16. the serdes modules provid e the 24 pci express hardware interface lanes. the lanes can be combined, for a total of one to two pci express ports in station 0, and one to four pci express ports in station 1. if the upstream port is in the other stati on, all enabled ports in the current station are downstream ports. lanes from different stations cannot be combined to form ports. from the system model viewpoint, each pci express po rt is a virtual pci-to-p ci bridge device with its own set of pci express configuration registers. th e bios enumerates the pe x 8524 ports, using either conventional pci configuration acces s or pci express enhanced access. the pex 8524 port width is configurable by way of strapped signal balls, or serial eeprom after reset. the final port width can be made narrower by auto-lane width negotiation, as described in the pci express base r1.0a . 4.1.2.1 port combinations the pex 8524 supports a wide variety of configurations per station (as defined in table 4-1 ) and supports two stations and up to two ports on station 0 and four ports on station 1, providing an extensive set of possible port/station configurations. ports th at are not configured or enabled are invisible to software. there are 8 lanes [0-7] for station 0 and 16 lanes [16-31] for station 1. the configuration value defines the levels set by strap_stn0_portcfg[4:0] and strap_stn1_portcfg[3:0] . the equivalent system model cont ains an upstream port pci-to-pci bridge and five downstream port pci-to-pci bridges, as illustrated in figure 4-2 . the upstream station cont ains one upstream pci-to-pci bridge and one downstream pci-to-pci bridge. the upstream port and downstream ports? lane widths are initially set by the strapping balls, which must be tied high to vdd33 or low to vss (gnd). (refer to section 3.4.4, ?strappi ng signals ? 680-ball pbga,? or section 3.5.4, ?strapping signals ? 644-ball pbga.? ) the serial eeprom option is used to reconfigure the ports by using the options defined in table 4-1 . serial eeprom configuration occurs following a fundamental reset, and overrides the configuration set by the strapping balls at that time. (refer to section 5.3.3, ?setting port configuration using serial eeprom.? ) the narrowest port on one end of the link determines the maximum link width. additionally, if a connection is broken on one of the lanes, the training sequence removes the broken lane and negotiates to a narrower width. a x16 port can negotiate down to x8, x4, x2, or x1. if the port cannot train to x1 (lane 0 is broken), it reverses its lanes and attempts to train again. fo r ex a m p l e , a x16 port that cannot train to x16 attempts to negotiate down to x8, x4, x2, or x1; if x1 linkup fails, the port then reverses its lanes and a ttempts again to negotiate link up. either the lowest lane (lane 0) or highest lane (if lanes are reversed ) of the programmed link width must connect to the other device?s lane 0.
february, 2007 station and port functions expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 89 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: p-p is used to represent pci-to-pci in the illustrations provided in this data book. figure 4-2. equivalent system model with maximum number of ports and lanes table 4-1. pex 8524 port configurations port configuration register value a (port 0 or 8, offset 224h [4:0]) a. the pex 8524 can be re-configured by link-width negotiation to smal ler widths of x4, x2, or x1. station 0 [lanes/serdes]/ port b b. the lanes are assigned to each enabled por t in sequence, as indicated in [brackets]. station 1 [lanes/serdes]/port b port 0 port 1 port 8 port 9 port 10 port 11 0h x4 [0-3] x4 [4-7] x4 [16-19] x4 [20-23] x4 [24-27] x4 [28-31] 1h ? c c. configuration value and port combinations with ??? (no data) are reserved . ? x16 [16-31] d d. ports 8 and 9 can be combined to create a 16-lane (x16) port. ??? 2h x8 [0-7] ? x8 [16-23] x8 [24-31] ?? 3h ? ? x8 [16-23] x4 [24-27] x4 [28-31] ? 4h ? ? x8 [16-23] x4 [24-27] x2 [28-29] x2 [30-31] 5h ? ? x8 [16-23] x2 [24-25] x2 [26-27] x4 [28-31] 6h ? ? x8 [16-23] x2 [24-25] x4 [26-29] x2 [30-31] p-p p-p p-p p-p p-p p-p pci express x4 pci express x4 pci express x4 pci express x4 pci express x4 pci express x4 upstream station downstream station internal fabric upstream port downstream ports downstream p-p bridges upstream p-p bridge
functional overview plx technology, inc. 90 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4.1.2.2 port numbering the pex 8524 port numbers are 0, 1 (station 0) and 8, 9, 10, 11 (station 1). ports 2, 3, 4, 5, 6, 7 and 12, 13, 14, 15 are reserved for future use. (refer to table 4-1 and figure 4-3 .) the port number and device number are the same (in the type 1 headers) that map to all ports, with an exception for a non-zero upstream port. all downstream device numbers matc h their corresponding port number. for example , if port 0 is the upstream port, ports 1, 8, 9, 10, and 11 are the downstream ports. the device numbers for the pci-to- pci bridges implemented on the downstream ports ar e 1, 8, 9, 10, and 11, respectively. (refer to figure 4-3 .) any pex 8524 port can be configured as the upstream port. the pci-to-pci bridge implemented on the upstream port does not assume a device number ? it accepts the device number assigned by the upstream device. generally, the upstream devi ce assigns device number 0, according to the pci express base r1.0a . figure 4-3. plx port numbering convention example (when port 0 is upstream port) (upstream port) pci express upstream station 0 internal fabric port/device 0 port/device 1 port 2 port 3 port 4 port 5 port 6 port 7 reserved pci express downstream station 1 port/device 8 port/device 9 port/device 10 port/device 11 port 12 port 13 port 14 port 15 reserved for future expansion for future expansion
february, 2007 pci-compatible software model expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 91 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4.2 pci-compatible software model the pex 8524 can be thought of as a hierarchy of pc i-to-pci bridges, with one upstream pci-to-pci bridge and one or more downstream pci-to-pci bridges connected by a virtual internal bus. (refer to figure 4-4 .) pci-to-pci bridges are compliant with the pci and pci express system models. figure 4-4 illustrates the concept of hierarchical pci-to-pci bridges, with the bus in the middle being the virtual pci bus. the configuration space registers (csrs) in the upstream pci-to-p ci bridge are accessible by type 0 configuration requests targeting the upstr eam bus interface. the upstream port captures the type 0 configuration write target bus number and device number. the upstream port uses this captured bus number and captured device number as part of the requester id and completer id for the requests and completions generated by the upstream port. the csrs in the downstream port pci-to-pci br idges are accessible by type 1 configuration requests received at the upstream port that target the virtual internal bus, by having a bus number value that matches the upstream bridge?s secondary bus number value. each downstream bridge is associated with a unique device nu mber, as explained in section 4.1.2 . the csrs of downstream devices are hit in two ways. if the configuration request matches the pex 8524 downstream port secondary bus number, the pex 8524 converts the type 1 configuration request into a type 0 configuration requ est. however, if the bus number does not match the secondary bus number, but falls within the subordinate bus number range, the type 1 configuration request is forwarded out of the pex 8524, unchanged. after all pci devices have been located and assi gned bus and device numbers, software can assign a memory map and i/o map. requests (memory or i/o) go downstream if they fall within a bridge?s base and limit range. in the pex 8524, each downst ream bridge has its own base and limit. the request (memory or i/o) goes upstream if it does not target anything within the upstream bridge?s base and limit range. completions route by the bus number established in the configuration registers. if the bus number is in the secondary or subordinate range, the packet goes downstream; otherwise, the packet goes upstream. figure 4-4. pex 8524 system configuration propagation p-p p-p p-p p-p p-p p-p upstream station downstream station configuration propagation virtual pci bus upstream port downstream ports downstream p-p bridges upstream p-p bridge
functional overview plx technology, inc. 92 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4.2.1 system reset the pex 8524 can be reset by four different mechanisms (refer to section 5.1, ?reset overview,? for details): fundamental reset input, through the pex_perst# signal in-band reset propagates from upstream, through the physi cal layer mechanism, which communicates a reset through a trai ning sequence (ts1/ts2 ordered-set hot reset or disable link bit is set) pci express link enters the dl_d own state on the upstream port upstream port bridge control register secondary bus reset bit is set (offset 3ch [ 22 ]=1) reset is propagated from upstream to downstream. reset is propagated to the downstream pci express device, through the pci express link by the phys ical layer mechanism (the ts1/ts2 ordered-set hot reset bit is set), or when the upstream port link enters the dl_down state. (refer to section 5.1, ?reset overview,? for further details.) an example of reset propagation is illustrated in figure 4-5 . upon receiving a reset from the upstream pci express link, the upstream por t pci-to-pci bridge propagates the reset to the downstream port pci-to-pci bridges in the upstream station, as well as to the downstream port pci-to-pci bridges in its downstream station. figure 4-5. pex 8524 system reset propagation p-p p-p p-p p-p p-p p-p upstream station downstream station reset propagation upstream port downstream ports downstream p-p bridges upstream p-p bridge
february, 2007 interrupts expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 93 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4.2.2 interrupts generated interrupts are int x interrupt message-type (compatible with the pci r2.3 -defined interrupt signals) or message signaled interrupt s (msi), when enabled. msi and int x are mutually exclusive; either can be enabled in a system (depending on which interrupt type the system software supports), but never both. [refer to the message signaled in terrupt capability register (offset 48h ) and command register interrupt disable bit (offset 04h [ 10 ]).] the pex 8524 does not convert received int x messages to msi messages. refer to chapter 6, ?interrupts,? for complete details. 4.2.2.1 interrupt sources or events the pex 8524-generated interrupt/message sources include: hot plug events device-specific error events int x 4.2.2.2 int x switch mapping the pex 8524 remaps and collapses the int x virtual wires , based on downstream port device number and received int x message requester id device number. each virtual pci-to-pci bridge of a downstream port specifies the port number associated with the int x (interrupt) messages received or generated, and forwards the interrupt messages in the upstream direction. refer to section 6.2.1, ?intx-type interrupt message remapping and collapsing,? for interrupt routing information.
functional overview plx technology, inc. 94 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4.3 pci express station functional description the pex 8524 groups 8 serdes together into station 0, and 16 serdes together into station 1. a station can have one or two ports (station 0) or one to four ports (station 1), as defined in table 4-1 . the station forwards ingress packets to the internal fa bric, to be routed to the egress station. each station implements the pci express physical (phy) layer and data link layer (dll) functions for each of its ports, and aggregates traffic from these ports on to a transaction-based, non-blocking internal fabric. the pci express station also perf orms many transaction layer functions, while the packet queuing and ordering aspects of this layer are handled by the crossb ar switch control blocks. during system initialization, software initiates configuration requests that set up the pci express interfaces, device numbers, and address maps across the various ports. these maps are used to direct traffic between ports during standard system operation. a pci express station can contain multiple ports (one upstream and multiple downstream). traffic fl ow between different ports of the same station, or ports on different stations, is suppor ted by the central internal fabric.
february, 2007 pex 8524 functional blocks expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 95 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4.3.1 pex 8524 functional blocks at the top level, each station has a layered organi zation consisting of the ph ysical (phy), data link layer (dll), and transaction layer control (tlc) blocks, as illustrated in figure 4-6 . the phy and dll blocks have port-specific data paths (one pe r pci express port) that operate independently of one another. the tlc ingress aggregates traffic for all i ngress ports in the station, then sends the traffic to the internal fabric. the tlc egress accepts packets, by way of the internal fabr ic, from all ingress ports, and schedules them to be sent out the appropriate egress port. figure 4-6. pci express station block diagram (station 1) dll ingress 0-3 port enum. logic tlc ingress 16 serial lanes port receive logic link receive and transmit logic physical layer data link layer transaction layer control ingress credit unit tlc egress egress credit unit csr handling non-blocking internal fabric dll egress 0-3
functional overview plx technology, inc. 96 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4.3.1.1 physical layer the physical layer module interfaces to the pci express lanes and implements the phy layer functions. the number of ports per station can vary fr om one to two for station 0, and one to four for station 1, with a cumulative lane-bandwidth of x8 (station 0) or x16 (station 1). when there are fewer than two (station 0) or four (station 1) configured/e nabled ports, the x8 (station 0) or x16 (station 1) bandwidth can be shared by the remaining active ports, as defined in table 4-1 . phy layer functions include: establishing port configurations and serdes-to-port assignments establishing internal bandwidth division among ports supporting cross-linked upstream and downstream ports 8b/10b encoding/decoding data scrambling/unscrambling packet framing loop-back master and slave support pseudo-random bit sequence (prbs) data generation and checking user-defined test pattern with skip ordered-set insertion and return data checking driver and input buffers parallel-to-serial and se rial-to-parallel conversion plls and clock circuitry impedance-matching circuitry interface initialization a nd maintenance functions physical layer command and status registers the physical layer operating conditions are defined in section 11.13.2, ?physical layer registers.? the system host can track the link operating status and re-configure link parameters, by way of these registers. hardware link interface configuration the pex 8524 physical layer of each station can in clude up to four integr ated quad serializer/ de-serializer (serdes) modules, which provide th e pci express hardware interface lanes. the serdes modules provide all physical communication controls and functions required by the pci express base r1.0a . serdes modules are clustered into ports , to provide the links that connect to other pci express devices.
february, 2007 pex 8524 functional blocks expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 97 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4.3.1.2 data link layer the data link layer (dll) serves as an intermed iate stage between the transaction layer and the physical layer. the primary responsibility of the data link layer includes link management and data integrity, including erro r detection and correction. the transmission side of the data link layer accepts transaction layer packets (tlps) assembled by the transaction layer, calculates and applies da ta protection code and tlp sequence number, and submits them to the physical layer for transmission across the link. the receiving data link layer is re sponsible for checking the integrity of received tlps and submitting them to the transaction layer for further processi ng. on detection of tlp error(s), this layer is responsible for requesting re-transmi ssion of tlps until the information is correctly received, or the link is determined to have failed. data link layer packet (dllp) the data link layer also generates and consumes packets used for link management functions. to differentiate these packets from the tlps used by the transaction layer, the term data link layer packet ( dllp ) is used when referring to packets generate d and consumed at the data link layer. the rules governing the identification and format ion of these packets are defined in the pci express base r1.0a , section 3.4.1. fc credits the initial number of flow control credits adve rtised for virtual channel 0 is listed in section 8.4.2.1, ?ingress side.? the flow control credits are also prog rammable through the serial eeprom. the transaction layer must schedule an update fc dllp for transmission, to replenish the number of advertised credits or to meet an updated vc timer. when enabled, the transaction layer initiates flow credit initialization for vc1, following vc0 initialization. packet arbiter the packet arbiter determines what t ype of packet to forward to the phy layer, on a per port basis. the priority algorithm implemented by the packet arbiter is discussed in section 8.4.5.1, ?arbitration between dllp and tlp,? and follows the recommended priority provided in the pci express base r1.0a , section 3.5.2.1.
functional overview plx technology, inc. 98 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4.3.1.3 transaction layer the upper layer of the architecture is the tran saction layer. the transaction layer?s primary responsibility is the assembly and disassembly of transaction layer packets (tlps). tlps are used to communicate transactions, such as read and write, as well as certa in types of events. the transaction layer is also responsible for managing credit-based flow control for tlps. request packets requiring a response packet are implemented as split tr ansactions. each packet contains a unique identifier that enables response p ackets to be directed to the correct originator. the packet format supports diff erent forms of addressing, depending on the transaction type ? memory , i/o , configuration , or message . the packets can also have attributes, such as no snoop and relaxed ordering . the transaction layer supports four address spaces ? it includ es the three pci address spaces (memory, i/o, and confi guration) and adds a message space. (refer to table 4-2 .) this specification uses message space to support all prior sideband signals, such as interrupts and power management requests, as in-band message transactions. pci express message transactions are considered virtual wires , because their effect is to eliminate the wide arra y of sideband signals currently used in a platform. functions provided by the transaction layer include: decoding and check ing incoming tlp memory-mapped csr access checking the incoming packets for malformed packets or unsupported requests (ur) ecrc checking the incoming packets error signaling for incoming packets destination lookup and tc-vc mapping virtual channel management tlp packet scheduling pci/pci-x-compatible ordering qos support external credit control power management support hot plug support message signal interrupt or int x generation ordering egress and ingress credit management table 4-2. address spaces support different transaction types address space transaction types transaction functions configuration read/write devic e configuration or setup. input/output read/write transfer data from/to an i/o-mapped location. memory read/write transfer data from/to a memory location. message baseline/ virtual wires general-purpose messages. event signaling ( such as status, interrupts, and so forth).
february, 2007 pex 8524 functional blocks expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 99 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 transaction layer receive/ingress protocol the ingress side transaction layer collects and stor es inbound tlp traffic in virtual channel buffers. the incoming data is checked for ecrc errors, valid type field, length matching the header transfer size field, and other tlp-specific errors defined by the pci express base r1.0a . header and data payload are forwarded to the source scheduler, to be routed to the switch outgoing port. transaction layer transmit/egress protocol the egress side transaction layer receives informat ion from other switch por ts and generates outbound requests and completion tlps, which it stores in virtual channel buffers. this layer assembles transaction layer packets, which consist of identification headers, data payloads, and ecrc. details for these fields are defined in the pci express base r1.0a , section 2.2. the pex 8524 implements an egress flow control (fc) protocol that ensures it does not transmit a tlp over a link to a remote receiver unless the recei ving device contains suffic ient virtual channel (vc) buffer space to accommodate the packet. this flow control is automatically managed by the hardware and is transparent to software. software is used on ly to enable additional buffers, to supplement the initial default buffer assignment. 4.3.1.4 virtual channels and traffic classes the pex 8524 supports two virtual channels ? vc0 and vc1 ? and up to eight traffic classes ? tc[7:0]). vc0 and tc0 are required by the pci express base r1.0a , and configured at device start-up. the second virtual channel (vc1) is enabled by the pex 8524 default configuration procedure, but can be disabled by using serial eeprom configuration to clear the port vc capability 1 register extended vc count bit (offset 14ch [ 0 ]). 4.3.1.5 non-blocking crossbar switch architecture the non-blocking crossbar switch is an on-chip interconnect switch-fabric module (internal fabric) used to link multiple stations. the physical topology of the crossbar switch interconnect is a packet beat-based internal fabric designed to simultaneously connect multiple on-chip logic stations. the crossbar switch protocol is sufficiently flexible and robust to support a variety of embedded system needs. the protocol is specifically designed to ease chip integratio n by strongly enforcing station boundaries and standardizing communication between stations. the crossbar switch ar chitecture incorporates the following functions: multiple concurrent data transfers with maximum throughput global ordering within the switch internal credit guarantees pack et forward progress once scheduled deadlock avoidance priority preemption two independent virtual channels (vc0 and vc1) pci express ordering rules packet fair queuing oldest first scheduling
functional overview plx technology, inc. 100 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4.3.2 relaxed ordering the pex 8524 does not support the optional relaxed ordering capability defined in the pci express base r1.0a . however, is does support two plx-specific relaxed ordering modes: pex 8524 relaxed ordering pex 8524 relaxed completion ordering ? silicon revisions bb/bc only 4.3.2.1 pex 8524 relaxed ordering the pex 8524 does not support the tlp optional relaxed ordering bit, as specified in the pci express base r1.0a , table 2-23. by default, all packets en tering from a specific port are dispatched to their respective destinatio ns, based on strict ordering. however, to remove unnecessary head-of-line blocking caused by pci ordering in applications where ordering is not important, the pex 8524 offers a plx-specific relaxed ordering mode. plx-specific relaxed ordering mode is enabled when any bit within a plx-specific relaxed ordering mode register enable plx relaxed ordering field is set to 1: port 0 or 8 ? offset bfch [7:0] port 1 or 9 ? offset bfch [15:8] port 10 ? offset bfch [23:16] port 11 ? offset bfch [31:24] in general, each port has 8 tcs to which it can map. the ingress scheduler on a specific port (for a speci fic traffic class) selects packets without using ordering requirements and dispatch es the packets to the egress ports. if using the relaxed ordering feature, ensure that it is used on ly for packets of a specific traffic cl ass. this allows those packets to be distinguished from packets on other traffic classes in which the relaxed ordering feature is not enabled. after the packets reach the egress ports , strict ordering is used in these queues, irrespective of the bits set on the ingress port. refer to section 8.3.2.3, ?plx-specific relaxed ordering,? for further details. 4.3.2.2 pex 8524 relaxed completion ordering ? silicon revisions bb/bc only the pex 8524 provides a relaxed completion ordering feature that enables completion transactions to pass enqueued posted transactions th at are blocked. this feature is available on vc0, and is enabled by setting the following b its in the device-specific configuration space: plx-specific relaxed ordering enable register plx-specific relaxed ordering enable bit (ports 0, 1, 8, 9, 10, and/or 11, offset 1f0h [20]) is set to 1, and plx-specific relaxed comple tion ordering (ingress) register enable plx-specific relaxed completion ordering bit (port 0 or 8, offset bech [0]) is set to 1, and any bit within a plx-specific relaxed ordering mode register enable plx relaxed ordering field is set to 1 ? port 0 or 8 ? offset bfch [7:0] ? port 1 or 9 ? offset bfch [15:8] ? port 10 ? offset bfch [23:16] ? port 11 ? offset bfch [31:24] in general, each port has 8 tcs to which it can map.
february, 2007 non-transparent bridging implementation expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 101 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4.3.2.3 no snoop enable ? silicon revisions bb/bc only in nt mode, the pex 8524 provides a no snoop disable feature to force the no snoop attribute bit in the packet header to 0, for all p ackets transferred between the nt link and virtual interfaces (across the nt boundary, in both directions). this capability can be used to handle cache coherency-related issues in a system. to enable this feature, set the ingress control register no snoop disable bit (offset 660h [24]) to 1. 4.4 non-transparent bridging implementation the pex 8524 supports non-transparent (nt) bridge functionality, which is used to implement high- availability systems or intelligent i/o modules using pci express technology. the following discusses the basic non-transparent bridging concept, as it applies to a pci express system. nt bridges allow systems to isol ate address spaces by appearing as an endpoint to the host. an nt bridge exposes a type 0 csr header and forw ards transactions from one domain to the other, using address translation. an nt bridge is used to connect two independent address/host domains. the nt bridge includes doorbell registers for transmitting interrupts from one side of the bridge to the other. the bridge also includes scratchpad registers, accessible from both domains for inter-host communication. the pex 8524 pci express switch, with a single port configured to operate in nt bridge mode, supports two system models: intelligent adapter mode dual-host mode the pex 8524 switch initial operating mode is determined by the strap_mode_sel[1:0] balls. the mode can later be changed by the serial eeprom, by writing to the debug control register mode select field.
functional overview plx technology, inc. 102 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4.4.1 intelligent adapter mode the use of non-transparent bridge s in pci systems is well established for supporting intelligent adapters in enterprise and multi-host systems. th e same concept is used in pci express bridges and switches. in figure 4-7 , there are two type 0 csr headers in the non-transparent pci-to-pci bridge. the one nearer the internal virtual bus is referred to as the virtual interface . the one nearer the pci express link is referred to as the link interface . in intelligent adapter mo de, the nt port link interface is connect ed to the system domain. the system host manages only the nt port link interface type 0 function. the local host manages all pex 8524 transparent port type 1 and nt port virtual interface type 0 functions. cross-domain traffic is routed through an address translat ion mechanism. (refer to section 12.1.6, ?address translation.? ) after power-up, the pex 8524 non-transparent type 1 ports, including the nt port virtual interface, are enumerated by the local host connected to the pex 8524 upstream port. the local host enables and resizes the base address registers (bars) by programming the nt port link interface bar setup/limit registers, before the system host assigns resources for these bars. this behavior is changed with serial eeprom initialization. after the local host finishes its e numeration, it enables the nt port li nk interface to be enumerated by the system host connected to the interface. the nt port link interface retries the system host configuration transaction until the local host enables the nt port li nk interface to process the system host configuration transaction. the debug control register virtual interface access enable bit (offset 1dch [28]) enables access to the virtual in terface configuration registers. the link interface access enable bit (offset 1dch [29]) enables access to the link in terface configuration registers. these bits do not affect normal memory, memory-mapped csrs, nor i/o-mapped csr transactions. intelligent adapter mode does not support host-failover applications. figure 4-7. pex 8524 intelligent adapter software model p-p p-p p-p primary p-p bridge transparent upstream port transparent downstream ports transparent downstream p-p bridges transparent upstream p-p bridge non-transparent upstream port non-transparent downstream p-p bridge csr bar local host i/o fabric link interface fabric/ system host csr / bar virtual interface address translation csr / bar pex 8524
february, 2007 dual-host mode expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 103 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4.4.2 dual-host mode the pex 8524 can concurrently support two ho sts. the pex 8524 transparent upstream port is connected to the active host, and the nt port link interface is connected to the backup host. after power-up, the active and backup hosts can enumerate their domain at the same time, which is modified using the serial eeprom. the serial eeprom is necessary to enable or resize the bar setup/limit registers. dual-host mode supports host-failover applications, described in section 4.4.2.1 . figure 4-8. dual-host model 4.4.2.1 host-failover application the host-failover application is based on the basic dual-host configuration. the active host periodically transmits heartbeat messages, by way of the switch, to the backup host to indicate that it remains active. when the backup host fails to receive heartbeat message s before its fail detect timer expires, it starts the failover process. the backup host halts cross-domain traffic before it starts the failover. the backup host uses the memory-mapped access to the pci express capability list and capabilities register (offset 68h ) to execute the failover. the b ackup host performs the following procedure to take control: 1. failover detected. 2. upstream port demotion. 3. nt port (self-) promotion as a new upstream port. note: refer to section 14.2.4, ?host-failover application,? for further details. dynamic swapping of the upstream and nt ports is supported on ports 0 and 8.
functional overview plx technology, inc. 104 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 this page intentionally left blank.
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 105 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 5 reset and initialization 5.1 reset overview reset is a mechanism that returns a device to its ini tial state. hardware or software mechanisms can trigger a reset. the re-initialized states following a reset vary, depending on the reset type and condition. the pci express base r1.0a , section 6.6, defines the hardware mechanism as fundamental reset . two actions can trigger a fundamental reset: cold reset warm reset there is also a type of reset triggered by an in-b and signal from an upstream pci express link to all its downstream ports, which is called a hot reset . there is also a secondary bus reset . any pci-to-pci bridge can re set its downstream hierarchy by setting the bridge control register ( bcr ) secondary bus reset bit (offset 3ch [ 22 ]=1). upon exit from a cold or warm reset, all port conf igurations, port registers, and state machines are set to initial (start-up) values, as specified in section 5.2, ?initia lization procedure.? 5.1.1 cold reset a cold reset is a fundamental reset that occurs following a proper pex 8524 power-on. when the pex_perst# signal is held low following the proper application of power to the device, a fundamental reset occurs. a fundamental reset initializes the entire pex 8524 device ( such as configuration information, clocks, state machines, regist ers, and so forth). when power is removed from the device, or travels outside the required ranges, all settings and configuration information is lost. the device must cycle through the entire initialization procedure after power is accurately re-applied. 5.1.2 warm reset the fundamental reset mechanism can also be tr iggered by driving the pex 8524 hardware reset signal ( pex_perst# ) low, without the removal and re-application (recycling) of power. this is considered a warm reset. pex_perst# can be controlled by on-board toggle switches or other external hardware resets to the device. the device must cy cle through the entire initialization procedure after the pex_perst# input signal is returned to high.
reset and initialization plx technology, inc. 106 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 5.1.3 hot reset a hot reset is equivalent to a traditional software reset. triggered by an in-band signal from an upstream pci express link to all downstream ports, a hot reset causes all po rts that are downstream from the initiating port to set their registers and state machines to initial values. this type of reset does not require power cycling, nor does it cause pex 8524 port re-configuration. however, a hot reset: causes all tlps held in the pex 8524 to be dropped returns all state machines to their initial (default) values returns all non-sticky register bits to their initial (default) conditions (refer to table 11-3, ?register types, grouped by user accessibility,? for further details regarding sticky register bit types) a hot reset is triggered by the following actions: physical layer (at the upstr eam port) receives a reset through a training sequence leading to a hot reset upstream pci express port enters the dl_inactive state, which has the same effect as a hot reset note: in the following sections, the terms ?virtual pci-to-pci bridge? and ?port? refer to a given station port. 5.1.3.1 hot reset propagation reset is propagated to a downstream pci expre ss device through the pci express link, using the physical layer hot reset mechanism ( that is , a reset bit in the training sequence ordered-set from the upstream device is set). pci express views a switch as a hierarchy of virt ual pci-to-pci bridges. an example of reset propagation across the pex 8524 switch is illustrated in figure 5-1 . upon receiving a hot reset from the upstream pci express link, the vi rtual primary pci-to-pci bridge propagates the reset to virtual secondary pci-to-p ci bridges in the upstream and downstream ports. each virtual secondary pci-to-pci br idge propagates the reset to its downstream links, and initializes its internal states to initial/default conditions. a hot reset does not impact clock logic, port configuration, nor sticky register bits. figure 5-1. pex 8524 system reset propagation example p-p p-p p-p p-p p-p p-p upstream station downstream station reset propagation upstream port downstream ports downstream p-p bridges upstream p-p bridge
february, 2007 secondary bus reset expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 107 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 5.1.3.2 hot reset disable the pex 8524 includes a configuration option ? debug control register upstream port hot reset and link down reset propagation disable bit (port 0, offset 1dch [20]) ? to ignore the hot reset sequence from the upstream pci express link. setting this bit enables the upstream po rt to ignore a hot reset training sequence, blocks the switch from manifest ing an internal reset due a dl_down event, and prevents the downstream ports from issuing a hot rese t to downstream devices when either a hot reset or dl_down event occurs on the upstream link. 5.1.4 secondary bus reset when the upstream pci-to-pci bridge bridge control register ( bcr ) secondary bus reset bit (offset 3ch [ 22 ]) is set to 1, all ports that are downstream from that port are rese t to their initial/default states. the downstream ports propagate an in-band hot reset to their respective downstream links. in addition, the downstream ports? configuration space registers (csrs) are re-initialized. the upstream pci-to-pci bridge (upstream port) and its csrs are not affected; however, the queues to/from all downstream ports are drained, because thei r upstream-to-downstr eam virtual connections are re-initialized. when the downstream pci-to-pci bridge bcr secondary bus reset bit is set to 1, a hot reset is transmitted to its single downstream port, which rese ts all devices downstream from that port to their initial/default states. the reset port drops any incomi ng traffic. all other pex 8524 traffic not flowing to the reset port is unaffected. the downstream links are held in reset until software removes the condition by clearing the bcr secondary bus reset bit. the phy layer of the downstream port in question propagates the reset condition in-band to its downstream link, and remains in the hot reset state until the reset condition (bcr) is cleared. the transaction layer draining of non-empty queues to/from the affected port(s) is handled in a manner similar to the case of that port proceeding to the dl_inactive state, as defined in the pci express base r1.0a , section 2.9.
reset and initialization plx technology, inc. 108 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 5.2 initialization procedure upon exit from a fundamental reset, the pex 8524 in itialization process is started. there are two or three steps in the process, depending on the availabi lity of an external initialization serial eeprom. the initialization sequence executed is as follows: 1. pex 8524 reads the strapping signal balls to determine system mode, upstream port, and lane configuration of all ports. 2. if the serial eeprom is present ( ee_pr# ball is low), serial eeprom data is downloaded to the pex 8524 configuration registers. the configuration from the strapping signal balls can be changed by serial eeprom data. 3. after the configuration from the strapping signal balls and/or serial eeprom completes, the physical layer of the configured ports attempts to bring up the links. after both components on a link enter the initial link training state, they proceed through phys ical layer link initialization and then through flow control initialization for vc0, preparing the data link and transaction layers to use the link. following flow control initialization for vc0, it is possible for vc0 transaction layer packets (tlps) and data link layer packets (dllps) to be transmitted across the link. 5.2.1 default port configuration the default upstream port select ion and overall port lane-width configuration is determined by strapping signal ball levels. all strapping balls must be tied high to vdd33 or low to vss (gnd), which sets the default device configuration. (refer to section 3.4.4, ?strappi ng signals ? 680-ball pbga,? or section 3.5.4, ?strapping signals ? 644-ball pbga.? ) some of these settings can be changed by downloading serial eeprom data, or through initial port negotiation. 5.2.2 default register initialization each pex 8524 port defined in the port configuration process has a set of assigned registers that control port activities and status during normal operation. th ese registers are set to default/initial settings, as defined in: chapter 11, ?pex 8524 transpar ent mode port registers? chapter 15, ?nt port virtual interface registers? chapter 16, ?nt port link interface registers? following a fundamental reset, the basic pci expres s support registers are initially set to the values specified in the pci express base r1.0a . the plx-specific registers are set to the values specified in their register description tables. these registers can be changed by loading new data with the attached serial eeprom, or by way of transaction laye r configuration space register (csr) accesses using configuration or memory writes; however, registers identified as read-only (ro) cannot be modified by configuration nor memory write requests. the pex 8524 supports three mech anisms for accessing registers by way of the transaction layer, as described in the following sections: section 11.4.1, ?pci r2.3-compa tible configuration mechanism? section 11.4.2, ?pci express e nhanced configuration mechanism? section 11.4.3, ?plx-specific memo ry-mapped configuration mechanism?
february, 2007 serial eeprom initialization expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 109 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 5.2.3 serial eeprom initialization note: for further details, refer to the pex 85xx eeprom ? pex 8532/8524/8516 design note . the on-chip serial eeprom controller is integrated in pex 8524 station 0, as illustrated in figure 5-2 . the controller performs a serial eeprom download wh en a serial eeprom is present, as indicated by the ee_pr# strapping ball = low, and when one of the following events occur: pex_perst# is returned high, following a fundamental reset ( such as, a cold or warm reset) hot reset is received at the upstream por t (downloading upon this event can be optionally disabled), by setting the port 0 register at offset 1dch [16, 17 , and/or 20] upstream port exits a dl_down condition (downloading upon this event can be optionally disabled), by setting the port 0 register at offset 1dch[16, 17, and/or 20] figure 5-2. pex 8524 serial eeprom connections initialization serial eeprom port 1 port 8 port 9 port 10 port 11 port 0 station 1 serial eeprom controller pex 8524 ee_cs# ee_do ee_di ee_sk ee_pr# configuration data station 0
reset and initialization plx technology, inc. 110 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 5.2.3.1 configuration data download serial data is downloaded from th e serial eeprom and converted to pa rallel data, which is then routed to the pex 8524 ports. the serial eeprom controller generates a 7.8-mhz ee_sk signal and reads a total of 3,044 dwords from the serial eeprom, which represents the data necessary to initialize the pex 8524 registers. the serial eeprom memory map reflects the basic pex 8524 register map, for registers discussed in the following chapters: chapter 11, ?pex 8524 transpar ent mode port registers? chapter 15, ?nt port virtual interface registers? chapter 16, ?nt port link interface registers? because these registers are duplicated for each port , the serial eeprom data starts with station 0, port 0, offset 00h , and progresses through the registers for al l six ports, in sequence. certain general device registers are appended at the end of the space for port 0, and various address spaces are skipped due to unused / reserved register space. a detailed description of the serial eeprom memory map is provided in appendix a . while downloading the data, the pex 8524 generates a crc value from the read data. when the serial eeprom download is complete, the generated crc valu e is compared to a crc value stored in the last dword location of the serial eeprom. if th e crc values match, the pex 8524 sets the serial eeprom status register serial eeprom present field (port 0, offset 260h [ 17:16 ]) to 01b (serial eeprom download complete and serial eeprom crc is validated). if the crc fails: the serial eeprom status register serial eeprom present field is set to 11b to indicate that the serial eeprom is present but a crc error was detected, and, if the serial eeprom status register crc disable bit (port 0, offset 260h[ 21 ]) value is 0 (default), all registers that ar e serial eeprom-programmable ar e reset/initialized to default values, or, if the serial eeprom status register crc disable bit value is 1, the crc error is ignored and all registers that are seri al eeprom-programmable are init ialized with the values that were downloaded from the serial eeprom. caution: setting the crc disable bit is strongly discouraged because a corrupted serial eeprom download could rend er the pex 8524 inoperable until a fundamental reset is applied (by asserting pex_perst# input). during the serial eeprom download, the class code 060400h is monitored. if the correct code is not found, the download is terminated. note: it is the system software?s responsibility to verify whether the serial eeprom download completes without error.
february, 2007 pci express configuration, control, and status registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 111 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 5.3 pci express configuration, control, and status registers the pci express configuration, contro l, and status registers that can be initialized are discussed in the following sections. however, this is not a complete list of programmable registers. for a complete list, refer to chapter 11, ?pex 8524 transpar ent mode port registers,? and appendix a, ?serial eeprom memory map.? section 5.3.1, ?selecting configur ation values using serial eeprom? section 5.3.2, ?selecting upstr eam port using serial eeprom? section 5.3.3, ?setting port configuration using serial eeprom? section 5.3.4, ?power management parameters using serial eeprom? section 5.3.5, ?message signaled interrupt capability using serial eeprom? section 5.3.6, ?pci express capability using serial eeprom? section 5.3.7, ?device seri al number extended capability using serial eeprom? section 5.3.8, ?power budgeting extended capability using serial eeprom? section 5.3.9, ?virtual channel extended capability using serial eeprom? section 5.3.10, ?advanced error reporting capability using serial eeprom? the device-specific registers cannot be accessed by configuration requests; however, software can access these registers with memory requests.
reset and initialization plx technology, inc. 112 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 5.3.1 selecting configuration values using serial eeprom configuration values, for the registers defined in section 11.6, ?configuration header registers,? can be changed using the serial eeprom, with the exception of those fixed by the pci express base r1.0a or not supported by the pex 8524. 5.3.2 selecting upstream port using serial eeprom the debug control register upstream port number field (offset 1dch [ 11:8 ]) values defined in table 5-1 determine the upst ream port selection. table 5-1. debug control register upstream port number field (offset 1dch[11:8]) values station 0 station 1 0h = port 0 8h = port 8 1h = port 1 9h = port 9 2h to 7h = reserved ah = port 10 bh = port 11 ch to fh = reserved
february, 2007 setting port c onfiguration using serial eeprom expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 113 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 5.3.3 setting port configuration using serial eeprom to use the serial eeprom to set the port co nfiguration, program the following registers: port configuration register port configuration field ? sets the port configuration (ports 0 and 8, offset 224h [ 4:0 ]) debug control register ? sets the port number and parameters for the upstream port the port configuration register port configuration field value determines the number of enabled ports per station, as well as the maximum link widths of those ports, as defined in table 5-2 . table 5-2. pex 8524 port configurations port configuration register value a (port 0 or 8, offset 224h [4:0]) a. the pex 8524 can be re-configured by link-width negotiation to smal ler widths of x4, x2, or x1. station 0 [lanes/serdes]/ port b b. the lanes are assigned to each enabled por t in sequence, as indicated in [brackets]. station 1 [lanes/serdes]/port b port 0 port 1 port 8 port 9 port 10 port 11 0h x4 [0-3] x4 [4-7] x4 [16-19] x4 [20-23] x4 [24-27] x4 [28-31] 1h ? c c. configuration value and port combinations with ??? (no data) are reserved . ? x16 [16-31] d d. ports 8 and 9 can be combined to create a 16-lane (x16) port. ??? 2h x8 [0-7] ? x8 [16-23] x8 [24-31] ?? 3h ? ? x8 [16-23] x4 [24-27] x4 [28-31] ? 4h ? ? x8 [16-23] x4 [24-27] x2 [28-29] x2 [30-31] 5h ? ? x8 [16-23] x2 [24-25] x2 [26-27] x4 [28-31] 6h ? ? x8 [16-23] x2 [24-25] x4 [26-29] x2 [30-31]
reset and initialization plx technology, inc. 114 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 5.3.4 power management parameters using serial eeprom power management parameters, for the registers defined in section 11.7, ?power management capability registers,? can be changed using the serial eepro m, with the exception of those fixed by the pci express base r1.0a or not supported by the pex 8524. 5.3.5 message signaled interrupt capability using serial eeprom message signaled interrupt (msi) capability parameters, for the registers defined in section 11.8, ?message signaled interr upt capability registers,? can be changed using the serial eeprom, with the exception of those fixed by the pci express base r1.0a or not supported by the pex 8524. 5.3.6 pci express capability using serial eeprom pci express capability parameters, for the registers defined in section 11.9, ?pci express capability registers,? can be changed using the serial eeprom, with the exception of those fixed by the pci express base r1.0a or not supported by the pex 8524. 5.3.6.1 configuring hot plug controller slot power-up sequence features with serial eeprom refer to section 9.4.1.1, ?configuring hot plug controll er slot power-up se quence features with serial eeprom,? for details. 5.3.7 device serial number ex tended capability using serial eeprom device serial number extended capability parameters, for the registers defined in section 11.10, ?device serial number exte nded capability registers,? can be changed using the serial eeprom. 5.3.8 power budgeting extended capability using serial eeprom power budgeting extended capability parameters, for the registers defined in section 11.11, ?power budgeting extended capability registers,? can be changed using the serial eeprom. 5.3.9 virtual channel extended capability using serial eeprom virtual channel extended capability parameters, for the registers defined in section 11.12, ?virtual channel extended capability registers,? can be changed using the serial eeprom. 5.3.10 advanced error reporting capability using serial eeprom the pex 8524 supports advanced er ror reporting, as defined in the pci express base r1.0a . advanced error reporting capability parameters, for the registers defined in section 11.14, ?advanced error reporting capability registers,? can be changed using the serial eeprom.
february, 2007 plx-specific registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 115 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 5.3.11 plx-specific registers the following registers are unique to the pex 8524 device, and are not referenced in pci express documentation. the plx-specifi c registers are organized into the following sections: section 11.13.1, ?error checking and debug registers? section 11.13.2, ?physical layer registers? section 11.13.3, ?cam routing registers? section 11.13.4, ?ingr ess control registers? section 11.13.5, ?i/o cam base and limit upper 16 bits registers? section 11.13.6, ?base address registers (bars)? section 11.13.7, ?shadow virtual channel (vc) capability registers? section 11.13.8, ?ingress cred it handler (inch) registers? section 11.13.9, ?ingress one- bit ecc error count register? section 11.13.10, ?relaxed completion ordering (ingress) register ? silicon revisions bb/bc only? section 11.13.11, ?relaxed orde ring mode (ingress) register? section 11.13.12, ?internal credit handl er (itch) vc&t threshold registers? the device-specific registers cannot be accessed by configuration requests; however, software can access these registers with memory requests.
reset and initialization plx technology, inc. 116 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 5.3.12 reset and clock initialization timing figure 5-3. reset and clock initialization timing table 5-3. reset and clock initialization timing symbol description typical delay td1 ref clock stable to pex_reset release time 100 s td2 pex_reset release to pll cloc k stable and reset de-bounce 1.32 ms td3 clock and reset stable to pll lock 125 s td4 pll lock to bist done time, which causes core reset release 4.5 ms td5 core reset release to serdes resets active delay 10 s td6 serdes reset active time 60 s td7 serial eeprom load time 12.6 ms pex_refclk pex_perst# pll_lock bist_done core_reset# serdes_reset serdes_ serial eeprom clock load active inactive inactive 100 mhz td6 td5 td4 clock stable td7 td3 td1 pll/sclk 250 mhz clock stable clock stable td2
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 117 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 6 interrupts 6.1 interrupt support the pex 8524 supports the pci express interr upt model, which uses two mechanisms: int x emulation message signaled interrupt (msi) for conventional pci compatibility, the pci int x emulation mechanism is used to signal interrupts to the system interrupt controller. this mechanism is compatible with existing pci software, provides the same level of service as the corresponding pci interrupt signaling mechanism, and is independent of system interrupt controlle r specifics. the pci int x emulation mechanism virtualizes pci physical interrupt signals by using an in-band signaling mechanism. in addition to pci int x -compatible interrupt emulation, the pex 8524 supports the message signaled interrupt (msi) mechanism. the pci express msi m echanism is compatible with the msi capability defined in the pci r2.3 . the following events are supported for interrupts: hot plug ? attention button pressed ? power fault detected ? mrl sensor changed ? presence detect changed ? command completed device-specific errors ? ecc error detected in internal packet ram ? ingress credit underrun ? internal error fifo overflow 6.1.1 pex 8524 interrupt handling the pex 8524 provides an interrupt generation modu le with each port. the module reads the request for interrupts from different sources and gene rates an msi or pci- compatible assert_int x / deassert_int x interrupt message. the msi supports a pci express edge-triggered interrupt, whereas assert_int x and deassert_int x message transactions emulate pci level-triggered interrupt signaling. the system interrupt cont roller functions include: sensing interrupt events signaling the interrupt, by way of the int x mechanism, and setting the interrupt status bit signaling interrupt by way of the msi mechanism handling int x -type interrupt messages from downstream devices
interrupts plx technology, inc. 118 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 6.2 int x emulation support the pex 8524 supports pci int x emulation, to signal interrupts to the system interrupt controller. this mechanism is compatible with existing pci software. pci int x emulation virtualizes pci physical interrupt signals, by using the in-band signaling mechanism. pci interrupt registers (the interrupt registers defined in the pci r2.3 ) are supported. the pci r2.3 command register interrupt disable and status register interrupt status bits are also supported (offset 04h [ 10 , 19 ], respectively). although the pci express base r1.0a provides inta#, intb#, intc#, and intd# for int x signaling, the pex 8524 uses only inta# for in ternal interrupt message generation, because it is a single-function device. however, incoming messages from downstream devices can be of inta#, intb#, intc#, or intd# type. internally generated inta# messages from the downstream port are also remapped and collapsed at the upstream port, according to the do wnstream port?s device number, with its own device number and received device number from the downstream device. when an interrupt is requested, the status register interrupt status bit is set. if int x interrupts are enabled [ command register interrupt disable and message control register msi enable bits (offsets 04h [ 10 ] and 48h [ 16 ], respectively) are cleared to 0], an assert_int x message is generated and transmitted upstream to indicate the port interrupt status. for each interrupt event, there is a corresponding mask bit. th e interrupt request can be generated only when the mask bit is not set. software reads and clears the event and interrupt status bit after servicing the interrupt.
february, 2007 intx-type interrupt message remapping and collapsing expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 119 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 6.2.1 int x -type interrupt message remapping and collapsing int x -type interrupt messages from downstream devices are directly forwarded to the upstream port , rather than being terminated and regenerated by the downstream port. the upstream port remaps and collapses the int x message type received at the downstream port, based upon the downstream port?s device number and received int x message requester id device number, and generates a new interrupt message, according to the mapping defined in table 6-1 . a downstream port transmits an assert_inta/deas sert_inta message to the upstream port, due to a device-specific error. internally generated int x messages always originate as type inta messages, because the pex 8524 is a single-function device. internally generated in terrupt inta messages from downstream ports are remapped at the upstream port to inta, intb, intc, or intd messages, according to the mapping defined in table 6-1 . int x messages from downstream de vices and from internally generated interrupt messages are ored together to generate inta, intb, intc, or intd le vel-sensitive signals, and edge-detection circuitry in the upstream port generates the assert_int x and deassert_int x messages. the upstream port then forwards the new messages upstream, by way of its link. table 6-1. downstream/upstream port int x interrupt message mapping device number at downstream port by upstream port 0, 8 inta inta intb intb intc intc intd intd 1, 9 inta intb intb intc intc intd intd inta 10 inta intc intb intd intc inta intd intb 11 inta intd intb inta intc intb intd intc
interrupts plx technology, inc. 120 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 6.3 message signaled interrupt (msi) support one of the interrupt schemes supported by the pex 8 524 is the msi mechanism, which is required for pci express devices. the msi method uses memory wr ite transactions to deliver interrupts. msis are edge-triggered interrupts. note: msi and intx are mutually exclusive. these interrupt mechanisms cannot be simultaneously enabled. 6.3.1 msi operation at configuration time, system software traverses the function capability list. if a capability id of 05h is found, the function implements msi. system softwa re reads the msi capability structure registers to determine function capabilities. the pex 8524 supports only one message for msi; therefore, the message control register multiple message enable and multiple message capable fields (offset 48h [ 22:20 , 19:17 ], respectively) are always cleared to 000b. the message control register msi 64-bit address capable bit is enabled (offset 48h[ 23 ]=1), by default. system software initializes the msi capability structure registers with a system-specified message. if the msi function is enabled, after an interrupt event occurs, the interrupt generation module generates a dword memory write to the address specified by the message address[31:0] register (offset 4ch ) contents. data written is the contents of the message data register (offset 54h ) lower two bytes and zeros (0) in the upper two bytes. because the message control register multiple message enable field (offset 48h[22:20]) field is always cleared to 000b, the interrupt generation module is not allowed to change the low-order bits of message data. when the hot plug and/or device-sp ecific error events that caused th e interrupt are se rviced, the device can generate a new msi memory write as a result of new events. 6.3.2 msi capability registers msi capability registers are described in section 11.8, ?message signaled interrupt capability registers.?
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 121 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 7 software architecture 7.1 pex 8524 software model the pex 8524 requires software support in the following areas: switch configuration and configuration of all switch downstream links moving data forward and back through the links monitoring and servicing interrupts throughout the connected fabric monitoring and adjusting pe rformance-rela ted mechanisms the configuration mechanisms are straightforward and use conven tional pci software structures and procedures to set up and identify all ports an d links connected through the pex 8524. the pex 8524 supports an optional serial eeprom interface, to simplify downloading of confi guration data to the switch. (refer to section 7.3 .) after the pex 8524 and its links are set up, data can be routed through the pex 8524, from one port to another. responses and other communications are returned, by way of the same links, to the initiator. the pex 8524 is transparent to th ese data transfers. (refer to section 7.3.1.3 .) when errors occur during data transf er due to data corruption in the in ternal ram, or an external device violates its credits, an interrupt is returned, thr ough the internal fabric to the host, identifying the problem. it is the responsibility of the host softwa re to implement interrupt-service routines to handle the problem. (refer to chapter 6, ?interrupts,? for further details.)
software architecture plx technology, inc. 122 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 7.2 configuration mechanisms the pex 8524 supports the two configuration mechanisms described in the pci express base r1.0a : pci r2.3-compatible co nfiguration mechanism this mechanism supports 100% binary compatibility with the pci r2.3 and its corresponding bus enumeration and configuration software. the mechanism allows access to the lower 256 bytes (64 dwords) of the 4- kb configuration space of each port. access to the entire 4-kb configuration space requires 10 address bits, which are defined in a pci express configuration request pack et to include a 6-bit register number field and a 4-bit extended register number field. the mechanism maps all six of its address bits into the register number field, and clears the extended register number field in the packet to 0h . therefore, the mechanism cannot access the upper 960 dwords (pci expr ess extended configuration space) that are implemented in each port. pci express enhanced configuration mechanism this mechanism increases the si ze of available configuration sp ace and optimizes configuration mechanisms. the mechanism allows access to th e entire 4-kb confi guration space defined by the pci express base r1.0a . registers within the pex 8524 that are defined by the pci express base r1.0a can be accessed by this mechanism. pex 8524 device-specific registers (which are not defined by the pci express base r1.0a ) cannot be accessed by this mechanism. the pex 8524 also supports a third configuration mechanism: plx-specific memory-mapped configuration mechanism this mechanism supports access to all pex 8524 registers, with the use of memory read and memory write commands and a 128-kb address sp ace that includes the 4-kb register sets of all ports, that is located at the base address assigned to the upstream port?s base address 0 and base address 1 registers ( bar0 and bar1 , offsets 10h and 14h , respectively). from a software point of view, each pex 8524 port is a pc i-to-pci bridge. a pc i-to-pci bridge must have uniquely assigned bus and device numbers. the upstream port has its own primary bus number, while all downstream ports share the same (int ernal) bus number and different device numbers. for further details, refer to section 11.4, ?register access.? note: when enumerating the pex 8524v, the bios detects eight, rather than six, pci-to-pci bridges. the downstream ports of two of these bridges (ports 2 and 3) are not connected to pci express serdes lanes. hence, the ports associated with these bridges cannot be connected to endpoints.
february, 2007 software configuration and routing expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 123 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 7.2.1 software configuration and routing configuration requests must be routed from the ho st, through the pex 8524?s upstream port. all type 0 configuration requests access the pex 8524?s upstream port conf iguration registers. the upstream port?s pci-to-pci br idge forwards type 1 configuration requests from its upstream interface to its downstream interface. the secondary bus number of the upstream port matches the primary bus number of every downst ream port. if the bus number va lue encoded in the configuration request matches the upstream port?s secondary bus number, the configuration request is targeting a downstream port?s registers, and therefore the upstream port conver ts the type 1 configuration request to a type 0 configuration request. to access the pci- to-pci bridge registers of a specific downstream port, the device number value encoded in this configuration request (which the upstream port converted to type 0) must match the device number (port number) of the downstream port (the device number of a downstream port is always the same value as the desi gnated port number). if the bus number value encoded in the co nfiguration request matches the upstream port?s secondary bus number, the configuration request is targeting a do wnstream port?s register s, and therefore, the upstream port converts the type 1 c onfiguration request to a type 0 configuration request. to access the pci-to-pci bridge registers of a specific downstream port, the type 1 configuration request bus number value must match the upstream port?s s econdary bus number, and the device number must match the enabled downstream port?s device numb er. all other device numbers are non-existent devices, and the configuration request terminates with an unsupported request (ur) completion. to configure additional devices in the pci hierarchy, the switc h downstream ports must have their secondary and subordinate bus numbers set. any match on a downstream port pci-to-pci bridge?s secondary bus numbers results in the pex 8524 converting the incoming type 1 configuration request to an outgoing type 0 configuration request, and the device number must be 0. figure 7-1. pex 8524 system configuration propagation p-p p-p p-p p-p p-p p-p upstream station downstream station configuration propagation virtual pci bus upstream port downstream ports downstream p-p bridges upstream p-p bridge
software architecture plx technology, inc. 124 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 7.3 sample configuration procedure consideration must be given to the configuration procedure when setting up and initializing a pex 8524 switch. certain items are processed by initial ha rdware configuration, connections, and operating selections. the pci/pci-express conf iguration software can be written from the host, by way of the upstream port to all downstream ports and their links , or from a serial eeprom, by way of the serial eeprom interface. figure 7-2 illustrates an example of pex 8524 system configuration. figure 7-2. pex 8524 system configuration example note: in figure 7-2 , port 0 is designated as the upstream port; however, any port can be designated as the upstream port. port 1 port 8 port 9 port 10 port 11 port 0 upstream port downstream ports upstream station 0 downstream station 1 type 1 configuration accesses virtual pci bus type 0 configuration access p-p
february, 2007 sample configuration procedure expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 125 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 the sequence executed to set up and initi alize a pex 8524 switch is as follows: 1. ports and lanes, per port: refer to section 4.1.2.1, ?port combinations,? for options pex 8524 must be connected to pci express-compatible devices strapping balls must be set to identify the selected port configuration ? for station 0, refer to strap_stn0_portcfg[4:0] ? for station 1, refer to strap_stn1_portcfg[3:0] serial eeprom overrides the strapping ball selections 2. select the upstream port ? set strapping balls strap_upstrm_portsel[3:0] . 3. software/serial eeprom programs the following registers for the upstream port : primary bus number ? identifies the upstream link ( bus number register, offset 18h[ 7:0 ]) secondary bus number ? identifies the switch internal virtual pci bus ( bus number register, offset 18h[ 15:8 ]) subordinate bus number ? must be the last (largest) bus number in the downstream hierarchy of this upstream port ( bus number register, offset 18h[ 23:16 ]) set the command register bus master enable and memory access enable bits (offset 04h [2:1], respectively) base and limit registers ? combines the memory of all downstream devices into one large space, with the total size given by limit - base, and the start address given by base base address 0 and base address 1 registers ( bar0 and bar1 , offsets 10h and 14h , respectively) (base address for memory-mapped csr access on the pex 8524) 4. software/serial eeprom programs the following registers for the downstream ports : primary bus number ? all downstream port nu mbers are the device numbers on the internal virtual pci bus ( bus number register, offset [7:0]) secondary bus number ? identifies the port?s downstream link ( bus number register, offset [15:8]) subordinate bus number ? must be the last (largest) bus number in the downstream hierarchy of each downstream port ( bus number register, offset 18h[23:16]) set the command register bus master enable and memory access enable bits (offset 04h[2:1], respectively) base and limit registers ? combines the memory of all downstream devices into one large space, with the total size given by limit - base, and the start address given by base on the upstream port, the primary side is accessed by a type 0 configura tion access. the downstream ports are accessed with a type 1 c onfiguration access on the primary side of the upstream port, with the bus number of each transaction equal to the upstr eam port secondary bus nu mber (virtual pci bus).
software architecture plx technology, inc. 126 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 7.3.1 switch device number assignment example the following is an example of how to access th e pex 8524?s upstream port and downstream ports. assume that the pex 8524 consists of six ports, with one x4 upstream (default is port 0) and five x4 downstream ports (ports 1, 8, 9, 10, 11). further assume that the upstream bus number is 1, and that each downstream port uses only one bus nu mber, and that bus numbering is linear. a diagram of the system is illustrated in figure 7-2 . the upstream port (which is configured as port 0 with 8 lanes for this example), by default, and is assigned a primary bus number of 1 and a secondary bus number of 2. with four of the downstream ports each having one bus and a fifth downstream port having two buses, the subordinate bus number is 2 + (4 * 1) + (1 * 2) = 8. the device number, regardless of which port is the upstream port, is always 00h. port 1 registers are accessed with a type 1 configuration transaction: ? bus number is the internal virtual pci bus (upstream port secondary bus number, 2) ? device number is 01h ? function number to be 000b port 8 registers are accessed with a type 1 configuration transaction: ? bus number is 2 ? device number is 08h ? function number is 000b port 9 registers are accessed with a type 1 configuration transaction: ? bus number is 2 ? device number is 09h ? function number is 000b port 10 registers are accessed with a type 1 configuration transaction: ? bus number is 2 ? device number is 0ah ? function number is 000b port 11 registers are accessed with a type 1 configuration transaction: ? bus number is 2 ? device number is 0bh ? function number is 000b
february, 2007 switch device number assignment example expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 127 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 7.3.1.1 configuration regi ster programming sequence registers that are defined by pci-sig specificatio ns can be accessed by configuration mechanisms or memory command; device-specific registers can be accessed by memory command, but not by configuration mechanisms (except for limited, indirect access through the nt port cursor mechanism control registers , when non-transparent mode is enabled). upstream port base address 0 and base address 1 registers ( bar0 and bar1 , offsets 10h and 14h , respectively) map internal regist ers for memory-mapped i/o access. bar0 , is a 128-kb, non-prefetchable bar [the prefetchable bit (bit 3 ) with default value 0 is not programmable]. because bar0 maps to non-prefetchable address space and the address space is relatively small, it is recommended that bar0 be configured as a 32-bit bar (default, with bits [ 2:1 ]=00b), rather than as a 64-bit bar, to be mapped below the 4-gb address boundary space. with bar0 configured as a 32-bit bar, bar1 (which contains the upper 32 bits of address if bar0 is configured as a 64-bit bar) must remain the default value 0h. if bar0 is configured as a 64-bit bar and the bar1 value is 0h, a 64-bit access to bar0 / 1 returns an unsupported request (ur) error. bar0 and bar1 can be disabled by setting the ingress control register disable upstream port bar0 and bar1 registers bit (ports 0 and 8, offset 660h [25]). ( note: this feature is not available in silicon revision aa.) register access must be 1 dword (byte enables can sel ect individual bytes). if a memory read requests more than 1 dword, the pex 8524 returns the first dword, with a completion status of completer abort . this error is flagged in the upstream port device status register (offset 70h ) and uncorrectable error status register completer abort status bit (offset fb8h [15]). to program access to internal registers: 1. program the bus number register in the upstream port (offset 18h ). 2. program the bus number registers in all downstream ports (offset 18h). 3. program the memory base and limit address register (offset 20h ) in all downstream ports. 4. program bar0/1 on the upstream port. (optional, but necessary for memory-mapped access to internal registers.) 5. program the memory base and limit address register (offset 20h) in th e upstream port, ensuring the values claim all the space reque sted by all downstream ports. 6. program the command register bus master enable and memory access enable bits on all ports (offset 04h [2:1], respectively). figure 7-3. programming base and limit values port 1 port 8 port 9 port 10 port 11 port 0 upstream station 0 downstream station virtual pci the base and limit values of the upstream port must include the cumula- tive base and limit values of all the downstream ports, which in turn include the cumulative base and limit values of their downstream upstream port p-p
software architecture plx technology, inc. 128 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 7.3.1.2 sample pseudo code the following sample pseudo code demonstrates how to configure the pex 8524?s upstream and downstream ports after they are previously discovered by system enumeration software. cfgtype0 write busnum 01,devicenum 00 function 0 address 18h data 0009_0201h // primary bus number 01, secondary bus number 02 and subordinate bus number 09. at this step, the virtual pci bus in the pex 8524 gets the bus number 02. after this, any access to bus number 02 from the upstream port would refer to this bus. cfgtype1 write busnum 02,devicenum 01 function 0 address 18h data 0003_0302h // primary bus number 02, secondary bus number 03 and subordinate bus number 03. an endpoint is attached to port 1. cfgtype1 write busnum 02,devicenum 08 function 0 address 18h data 0005_0502h // primary bus number 02,secondary bus number 05 and subordinate bus number 05. an endpoint attached to port 8. cfgtype1 write busnum 02,devicenum 09 function 0 address 18h data 0006_0602h // primary bus number 02,secondary bus number 06 and subordinate bus number 06. an endpoint attached to port 9. cfgtype1 write busnum 02,devicenum 10 function 0 address 18h data 0007_0702h // primary bus number 02,secondary bus number 07 and subordinate bus number 07. an endpoint attached to port 10. cfgtype1 write busnum 02,devicenum 11 function 0 address 18h data 0008_0802h // primary bus number 02,secondary bus number 08 and subordinate bus number 09. this means that we have a p2p bridge attached to port 11 of pex 8524 and only 1 more level of pci hierarchy. cfgtype1 write busnum 02,devicenum 01 function 0 address 20h data 02ff_0200h // need 0200_0000h to 02ff_ffffh memory space for port 1. cfgtype1 write busnum 02,devicenum 08 function 0 address 20h data 04ff_0400h // need 0400_0000h to 04ff_ffffh memory space for port 8. cfgtype1 write busnum 02,devicenum 09 function 0 address 20h data 05ff_0500h // need 0500_0000h to 05ff_ffffh memory space for port 9. cfgtype1 write busnum 02,devicenum 10 function 0 address 20h data 06ff_0600h // need 0600_0000h to 06ff_ffffh memory space for port 10. cfgtype1 write busnum 02,devicenum 11 function 0 address 20h data 07ff_0700h // need 0700_0000h to 07ff_ffffh memory space for port 11. cfgtype0 write busnum 01,devicenum 00 function 0 address 20h data 07ff_0200h // the pex 8524 will claim all memory accesses from 0200_0000h to 07ff_ffffh and would send it to the appropriate port. any memory address not within any of the downstream address spaces will go to the upstream port. // now set the bus master enable and memory access enable bits on the upstream port and all downstream ports. cfgtype0 write busnum 01,devicenum 00 function 0 address 04h data 0000_0006h cfgtype1 write busnum 02,devicenum 01 function 0 address 04h data 0000_0006h cfgtype1 write busnum 02,devicenum 08 function 0 address 04h data 0000_0006h cfgtype1 write busnum 02,devicenum 09 function 0 address 04h data 0000_0006h cfgtype1 write busnum 02,devicenum 10 function 0 address 04h data 0000_0006h cfgtype1 write busnum 02,devicenum 11 function 0 address 04h data 0000_0006h // for each port configured above, registers 24h, 28h, and 2ch can be programmed to enable a 64-bit device prefetchable memory space for downstream devices. // memory-mapped access of all configuration registers listed above can also be performed by programming the bar0 and bar1 registers (for 64-bit memory spaces) for busnum 01, devicenum 00.
february, 2007 using base address re gisters (bars) to access registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 129 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 7.3.1.3 sample packet transfer when all ports are conf igured using the sample code provided in section 7.3.1.2 , the following occurs: 32-bit memory transactions from the upstream port, destined between addresses 0200_0000h to 07ff_ffffh, advance to the appropriate downstream port 32-bit memory transactions from a downstream port, between addresses 0200_0000h to 07ff_ffffh, advance to the appropriate downstream port (if the transactions are not within the base-limit range of that port) transactions from a downstream port, outsid e the range of addresses 0200_0000h to 07ff_ffffh and outside pex 8524 memory-mapped register space (refer to section 7.3.2 for details regarding register space), ad vance to the upstream port 7.3.2 using base address regist ers (bars) to access registers configuration requests can access only thos e registers that are defined by the pci express base r1.0a . these registers and the device-specif ic registers can all be accessed by memory requests that target the memory space defined by the upstream port base address 0 and base address 1 ( bar0 and bar1 ) registers (offsets 10h and 14h , respectively). upstream port bar0 register requests 128-kb memo ry space set aside for internal pex 8524 registers. optionally, the upstream port bar1 register can be used to place this internal register memory space anywhere in 64-bit system memory space. after the upstream port bar0 (and optionally, bar1 ) register is programmed, all register locations inside the pex 8524 can be accessed fr om any port, using either memory requests or configuration requests. each port consumes 4 kb of memory space for inte rnal registers. port 0 is at 0000h to 0fffh, port 1 is at 1000h to 1fffh, port 8 is at 8000h to 8fffh, and so forth. for example , if the upstream port bar0 register is programmed to 0100_0000h (using a type 0 configuration transaction) and the upstream port command register memory access enable bit is set (offset 04h [1]=1; again, programmed using a type 0 configuration transaction), then all pex 8524 registers can be accessed using memory-mapped register accesses. the following sections describe information sp ecific to transparent and non-transparent modes.
software architecture plx technology, inc. 130 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 7.3.2.1 transparent mode registers the formula to locate regist er addresses for transparent ports is as follows: bar0 + (port * 1000h) + register_offset for example , to hit the memory base and limit address (offset 20h ) for each port, refer to table 7-1 and figure 7-4 . table 7-1 defines how the registers in each port can be reached. all re gisters for all ports sit in the same bar. using the formula 1000h x port number provides the start address for the first register in a port. figure 7-4 provides a graphical view of the bar memory space. note: for a complete listing of memory-mapped register accesses, refer to section a.1, ?serial eeprom memory map.? figure 7-4. using memory-mapped access for pex 8524 in transparent mode table 7-1. pex 8524 memory-mapped register access register location address port 0 base and limit 0100_0020h port 1 base and limit 0100_1020h port 8 base and limit 0100_8020h port 9 base and limit 0100_9020h port 10 base and limit 0100_a020h port 11 base and limit 0100_b020h bar0 = 0100_0000h base and limit for port 0 = 0100_0020h base and limit for port 8 = 0100_8020h port 0 port 1 reserved port 8 port 9 port 10 port 11 reserved pex 8524 0 kb 4 kb 8 kb 12 kb 16 kb 32 kb 36 kb 40 kb 44 kb 48 kb 64 kb 72 kb 68 kb 128 kb
february, 2007 using base address re gisters (bars) to access registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 131 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 7.3.2.2 non-transparent mode registers in nt mode, there are additional registers represen ting the nt virtual and link interface endpoints. these exist at the fixed offsets of (refer to figure 7-5 ): virtual endpoint ? bar0 + 10000h link endpoint ? bar0 + 11000h note: for a complete listing of memory-mapp ed register accesses, refer to section a.1, ?serial eeprom memory map.? figure 7-5. using memory-mapped access for pex 8524 in non-transparent mode bar0 = 0100_0000h base and limit for port 0 = 0100_0020h base and limit for port 8 = 0100_8020h port 0 port 1 reserved port 8 port 9 port 10 port 11 reserved reserved pex 8524 nt port virtual interface nt port link interface 0 kb 4 kb 8 kb 12 kb 16 kb 32 kb 36 kb 40 kb 44 kb 48 kb 64 kb 72 kb 68 kb 128 kb
software architecture plx technology, inc. 132 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 7.4 interrupt support the pex 8524 supports the pci express interr upt model, which uses two mechanisms: int x emulation message signaled interrupt (msi) these interrupt mechanisms are discussed in chapter 6, ?interrupts.? 7.5 hot plug support the pex 8524 supports the standard hot plug controller (hpc) on all downstream ports. hot plug mechanisms are discussed in chapter 9, ?hot plug support.? note: refer to the pex 85xx eeprom ? pex 8532/8524/8516 design note for additional register programming information.
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 133 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 8 performance metrics 8.1 overview the pex 8524 includes features that optimize pe rformance under several application scenarios. this chapter discusses the four major performance metrics: internal fabric non-blocking nature quality of service (qos) sustained link throughput port-to-port latency these approaches emphasize metric optimization. in general, host-centric applications, with transactions traveling between a wide upstream port and narrow downstream ports, are more latency- oriented. in comparison, peer-to- peer applications, where trans actions are evenly distributed among all ports in a switch, are more throughput -oriented. however, achieving best performance is strongly application-dependent and the above principles are not necessarily always correct. for example , if the pex 8524 is linked with a graphics board in a host-centr ic application, graphics port throughput becomes the most important performance consideration, not latency . conversely, if the traffic pattern in a peer-to-peer appl ication is lightly loaded and bursty, latency can overweigh throughput , to become the highest performance concern. therefore, when tuning performance, it is important to understand the interaction and dynamics among performance metrics. for example , some tunings, in which the sending of traffic from multiple ingress ports to a narrow egress port is avoided, improve s overall throughput and latency by reducing hot-spot queuing within the system. other tunings, such as aggregating traffic from multiple ports into a wider data path and processing them in a time-multiplexed manner, can optimize throughput at the cost of slightly longer port-to-port latency. once the system dynamics are unde rstood, it is easier to exchange performance metrics against one another.
performance metrics plx technology, inc. 134 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8.2 non-blocking switch in switch literature, non-blocking is used to indicate that a packet can be routed from an ingress port to an egress port, provided that not mo re than one packet is received by the same ingress port and not more than one packet is destined to the same egress port. a non-blocking switch is expected to fully route all packets for independent ingress traffic streams, with the destination uniformly distributed. the pex 8524 is a non-blocking switch. 8.2.1 queuing topology three major queuing topologies ar e used in switch architecture: output queuing (oq) ? when a packet arrives at an ingres s port, it is immediately placed into a buffer that resides in the corresponding eg ress port. if, in the worst case, there are n ingress ports simultaneously attempting to transmit packets to the same egress port, the output buffer is required to enqueue traffic n times faster than the egress port?s dequeuing rate. input queuing (iq) ? in this architecture, ingres s port packets have a set of virtual output queues (voq). one of the packets, among all head packets in different voqs to the same egress port, is allowed to be scheduled out of that ingr ess port during a given time slot. the key factor in achieving high performance using voq is the global scheduling algorithm, which is responsible for the selection of packets to tr ansmit from the ingress ports to the egress ports in each time unit. the complexity of such scheduling algorithm is o(n 2 ) . combined input-output queuing (cioq) ? this approach adopts a queuing structure that is a combination of input and output queuing. it provides voq buffers at the ingress side, and also provides o(1) bandwidth buffers at the egress side. the design goal is to achieve the same level of throughput and non-blocking nature as an oq switch, but without requiring o(n) times bandwidth to buffers as an oq switch and without building a centralized scheduler whose complexity is proportional to o(n 2 ) as an iq switch. to achieve this goal, moderate internal fabric speedup is required in the cioq approach, to compensate for transient conflict. the pex 8524 uses cioq as its internal switching to pology to process traffic arriving from different stations. packets from one or more ports are aggr egated first into a station, whose data path is sufficiently wide to accommodate traffic from all ports within it at any time. the pex 8524 implementation includes two stations. in the future, this architectur e will be directly scaled up, to deal with more than two stations. for independent ingress traffic, it is possible for the cioq approach to achieve complete egress throughput with internal fabric to issue a speedup of only 2 ? 1/n. that is , for the two-station pex 8524 implementation, the intern al speedup factor of 1 (no speed up), is sufficient to achieve non- blocking status. after extensive simulation to consider standard switching performance factors including input traffic distribution, packet size distribution, output throughput, port-to-port latency, latency jitter, egress-to- ingress backpressure, as well as pci express-specific pe rformance factors such as physical layer, data link layer overhead, and packet-to-packet dependency caused by pci ordering, plx determined that using an internal speed-up factor of 1.25 allows the pex 8524 to be non-blocking.
february, 2007 port-to-station aggregation expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 135 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8.2.2 port-to-station aggregation as previously stated, a single pex 8524 pci express station is aggregated from multiple ports, provided that the combined port width is less than or equal to 8 lanes for station 0, and 16 lanes for station 1. figure 8-1 redraws the pex 8524 transaction layer architecture, by explicitly dividing a pci express station into individual ingress and egress parts. in a pci express source station, the write port to the ingress packet ram is shared by up to four ingress ports in a time domain multiplex (tdm) manner. the wider the port, the more tdm slots are assigned to that port. within voqs of a single source station, if multiple packets from different ingress ports are available to be dispatched to the same destination, a round-robin arbiter controls which ingress port to select next. moving to the internal fabric, the read ports to ingress packet ram and write ports to egress packet ram are controlled by the plx im plementation of the cioq scheduling algorithm, where a unit in scheduling is a station, rather than a port. in a pci express destination station, the read port to the egress packet ram is shared by up to four egress ports in a tdm manner as well. furthermore, there are four independent egress schedulers. egress schedulers follow virtual channel arbitration, as required by the pci express base r1.0a . figure 8-1. pex 8524 queuing data structures 1,376 x 20b = 27,520b ingress packet ram 32- entry p0 voq ctl 32-entry p1 voq ctl voq scheduler p0 ingress p1 ingress source station 0 2,048 x 20b = 40,960b egress packet ram p0 vc link list p1 vc link list tdm-controlled station-to-port de-aggregation destination station 0 1,376 x 20b = 27,520b ingress packet ram 32-entry p8 voq ctl 32-entry p9 voq ctl 32-entry p10 voq ctl 32-entry p11 voq ctl voq scheduler source station 1 internal fabric egress scheduler egress scheduler 2,048 x 20b = 40,960b egress packet ram p8 vc link list p9 vc link list p10 vc link list p11 vc link list tdm-controlled station-to,port de-aggregation destination station 1 egress scheduler egress scheduler egress scheduler egress scheduler station 0 station 1 p0 egress p1 egress tdm-controlled port-to- station aggregation tdm-controlled port-to-station aggregation p8 ingress p9 ingress p10 ingress p11 ingress p8 egress p9 egress p10 egress p11 egress
performance metrics plx technology, inc. 136 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8.2.3 ram and queue size table 8-1 defines the ram and queue size built into th e pex 8524. the smallest unit of ingress and egress packet ram is defined as a beat , which can store 20 bytes of data. in the pex 8524, the smallest packet (12b header) takes 1 beat to store in a packet ram, and the largest packet (16b header + 256b payload + 4b digest = 276b) takes 14 beats to store in packet ram. in table 8-1 , the number 32 under the cell ingress voq entries , per port indicates the maximum number of voq entries allocated to each ingress port. each voq en try holds one transaction layer packet. for ingress ports, the incomin g packet can travel to two destin ation stations, with each station containing up to four egress ports . also, for egress ports, up to tw o vcs are supported, with each vc potentially having three different packet types ? posted, non-posted, and completion (p, np, and cpl, respectively). each port on the egress side can contain up to six queues, to hold packets from two supported vcs and three supported packet types. a queue that stores packets of a unique vc and a unique type is referred to as a vc&t queue . again, some queues can be completely empty and some queues can contain more than one packet. the maximum number of packets held by a single egre ss port is limited by the number of egress packet ram beats allocated to that port. it can be calculated from table 8-1 that the total packet ram size for the pex 8524 is 136,960 bytes. assume the maximum transaction layer packet ( tlp) size is 276b with a maximum payload size (mps) of 256b. theoretically, the pex 8524 can store up to 496 mps packets. table 8-1. pex 8524 data structure size data structure name per port per station overall ingress packet name programmable 1,376 beats or 27,520 bytes 55,040 bytes ingress voq entries 32 128 256 egress packet ram 1,024 beats or 20,480 bytes for 1 to 2 ports; 512 beats or 10,240 bytes for 3 to 4 ports 2,048 beats or 40,960 bytes 81,920 bytes egress vc&t queues 6 24 48
february, 2007 quality of service (qos) support expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 137 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8.3 quality of service (qos) support quality of service (qos) is a pe rformance differentiation feature offered by pci express to manage multiple traffic classes of differen t characteristics. an application a ssigns a traffic class (tc) value to individual transaction layer packets, according to the qos requested by the class to which the transaction belongs. the static tc value tagged to each packet is dynamically mapped to a vc as it passes through a system pci express-capable device. the tc value ultimately determines the relative priority of a single packet as it traverses the pci express fabric, as well as the accumulated bandwidth allocated to the packets that belong to the same class. 8.3.1 virtual channel (vc) support the pex 8524 supports up to two virtual channels (vcs), vc0 and vc1. each vc has its own buffer resource allocation and data path. for a single port, vc configuration and pr operty are determined by the virtual channel extended capability register map (offset 148h to 1c4h). registers described in the virtual channel extended capability register map apply to the switch egress and ingress ports. registers related to packet arbitr ation are egress-specific, whereas registers defining tc/vc mapping and low-priority vc count are applicable to both egress and ingress ports. [refer to table 11-10, ?pex 8524 virtual channel extended capability register map (all ports),? for further virtual channel mapping information.] virtual channel and traffic labeling allow independent physical resources to handle differentiated traffic. the vc0 resource control and vc1 resource control registers (offsets 15ch and 168h , respectively) contain bits that control tc/vc mapping. across various ports, the pex 8524 supports both symmetric and asymmetric tc/vc mapping. in the latter approach, the tc/vc mapping is port-independen t and configured with di fferent values per port. the pex 8524 default configuration sets al l tc[7:0] to vc0, as provided in the tc/vc0 map bits. for applications requiring two vcs, tc[7:1] can be mapped to vc1 by removing them from the tc/ vc0 map bits and adding them to the tc/vc1 map bits.
performance metrics plx technology, inc. 138 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8.3.2 packet arbitration because of cioq switch architect ure and multiple vc support, the pex 8524 functions with several arbitration/scheduling points distributed in the data path from an ingress port to an egress port. this section discusses the arbitration/scheduling/b ackpressure algorithm used in the source scheduler, internal fabric, and egress scheduler. 8.3.2.1 source scheduler source scheduler is essentially the voq scheduler depicted in figure 8-1 . the source scheduler functions as follows: from all 32 voq entries (each entry represents a si ngle packet) belonging to a single ingress port, identifies one packet to be disp atched to the appropriate destination station, when egress ram space is available arbitrates among multiple-ready packets from different ingress ports with a round-robin mechanism breaks deadlock potential by following pci ordering rules note: packets to different egress ports are selected with oldest first criteria on a per-queue basis. this policy offers optimum fairness and performance properties at low complexity. packets to different vcs are se lected by allowing vc1 higher priority, if configured as such. pci ordering rules are enforced. the source scheduler is capable of handling variable -length packets. it can schedule one packet out of a source station every clock cycl e, regardless of packet size. there are two programmable fiel ds in the source scheduler: high-priority virtual channel plx-specific relaxed ordering 8.3.2.2 high-priori ty virtual channel when two vcs are enabled, packets from vc1 are scheduled with high priority by clearing the port vc capability 1 register (offset 14ch ) low-priority extended vc count bit. default setup can be changed by serial eeprom initialization.
february, 2007 packet arbitration expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 139 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8.3.2.3 plx-specific relaxed ordering plx relaxed ordering capability is supported to enhance the performance of ?push-only? traffic (posted packets, such as memory writes and messages) in the pex 8524. plx-specific relaxed ordering mode is enabled when any bit within the plx-specific relaxed ordering mode (ingress) register enable plx relaxed ordering field is set to 1: port 0 or 8 ? offset bfch [7:0] port 1 or 9 ? offset bfch [15:8] port 10 ? offset bfch [23:16] port 11 ? offset bfch [31:24] according to pci ordering rules, posted packets ar e not allowed to bypass previously posted packets of the same vc&t, regardless of whether they are targeting different egress ports. in applications such as storage area networks or ip networks, where po sted pci express packets are used to transmit encapsulated data traffic through switches, unnece ssary serial dependency might be created in the source scheduler for those posted packets coming fr om the same ingress ports, but going to different egress ports, if strict pci ordering rules were followe d. this can result in dram atically degraded overall switch throughput. the plx-specific relaxed ordering mode (ingress) register can be used to enable the plx-specific relaxed ordering capability. there is an enable bit fo r tcs in each ingress port. all packets are allowed to bypass older packets from the same ingress port and tc. packets targeting different egress ports are free to proceed without waiting for ordering dependency to be cleared. meanwhile, packets targeting the same egress port are processed ?in order, ? because there is no performance gain. because the enable bit is tc-based, taking advant age of plx-specific relaxe d ordering mode requires the pex 8524 to be programmed with symmetric tc/vc mapping first. posted traffic benefits most from this mode. to take advantage of plx-specific relaxed ordering mode, without violating other ordering rules defined by the pci r2.3 , it is suggested to restrict outstanding traffic flow to be ?posted only? and shut down all non-posted packets. there are two usage models: restrict all posted traffic requiring high-throughput in vc1 and program all tcs belonging to vc1 to enable relaxed ordering. software disables plx-specific relaxed ordering mode in all tcs beforehand, performing all setups that involve non-posted packet s, and then setting any bit within a plx-specific relaxed ordering mode register enable plx relaxed ordering field (offset bfch [31:0]) to 1 when the system enters pure data transfer mode. when the data transfer completes, disable plx-specific relaxed ordering mode. note: silicon revisions bb/bc only ? a variation of this feature, relaxed completion ordering, allows only completions to bypass posted packets, while preserving the remainder of pci ordering. refer to section 4.3.2.2, ?pex 8524 relaxed completion ordering ? silicon revisions bb/bc only,? for details.
performance metrics plx technology, inc. 140 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8.3.2.4 internal fabric backpressure internal fabric provides egress packet ram space available status from destination stations to source stations. the source scheduler never trans mits a packet to overflow egress packet ram. moreover, to prevent packets in a particular vc&t from occupying the majo rity of egress packet ram, and to speed up backpressure from egress queu es to ingress queues and ultimately to external devices in the case of congestion avoidance, vc&t-based (vc and type ? p, np, cpl) packet cutoff information is passed from egress ports to each source station. egress queue congestion occurs when the packet arrival rate overcomes the packet dispatching rate. there are two causes of congestion: insufficient credit to transmit the packets insufficient bandwidth to transmit the packets as quickly as they arrive in either case, if the cause co ntinues, eventually the egress qu eues of the congested port fill. the pex 8524 utilizes a watermark mechanism to cut off additional p ackets from the ingress side when the egress queues back up. with some egress ports cu t off, ingress queues that contain packets targeting those egress ports could then fill. a filled ingress queue prevents additional credit to its link partner, which causes that external device to stop transmitting packets in that vc&t. the itch vc&t threshold registers are per-vc&t-based in an egress port. all ports in a station share the same programmed value. each vc&t has its own upper and lower limit. if more data than the programmed upper limit is queued, no more packets of that vc&t can be scheduled across the internal fabric, thereby cutting off that vc&t flow. after cu tting off the vc&t flow, an egress queue eventually drops below its lower limit, as packets are schedule d out of the egress port. this event turns on the internal fabric vc&t-enabling flags, which allow that vc&t to resume flow. [refer to the itch vc&t threshold_1 through itch vc&t threshold_3 registers (offset c00h through c08h , respectively) for further details.] there are two rules used for programming the itch vc&t threshold registers: the unit value for the upper and lower limits is equivalent to 8 beats. the maximum value programmable in the upper limit is a f unction of the port width, defined in table 8-2 . a x8 egress port can handle no more than 1,024 beats, a meaningful value for the upper and lower limits is bounded by 1,024/8 = 128 (or 80h). in the device, the default value used by the upper and lower limits (ffh) is larger than its maximum legal value (80h). therefore, by default, the backpressure mechanism is not triggered. the upper and lower limits must be different, with the upper number being larger than the lower number by at least two units. table 8-2. vc&t threshold limits port width maximum upper limit in beats x1 128 x2 256 x4 512 x8 1,024 x16 (station 1 only) 2,048
february, 2007 packet arbitration expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 141 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 for example , programming upper = 14 and lower = 7 for vc 0 posted allows each po rt in the station to accumulate 1 4x8beats = 112 beats = 112 x 20 bytes = 2,240b vc0 posted bytes before any one port cuts off vc0 posted internal traffic. if there are four ports in the sta tion, then 8,960 bytes can be stored in the ram without the upper limit being crossed. af ter a port receives more than 112 beats of vc0 posted, no further vc0 posted is forwarded from the in gress port. the egress port must drain 7 x 8 beats before resuming vc0 posted forwarding. the main objective is to avoid clogging the egress ram with excessive packets of the same type that might prevent packets of other types from making fast forward progress inside the switch. if necessary, program the upper and lower limits. 8.3.2.5 egress scheduler in each egress port, the pex 8524 strictly follows vc and port arbitration mechanisms, as defined by the pci express base r1.0a . virtual channel arbitration in the context of scheduling traffic in vc0 and vc1, the main goal of the egress scheduler?s vc arbitration is to provide differentiated services be tween data flows within th e fabric. there are three vc arbitration choices: strict priority ? vc1 always prevails over vc0 round-robin, or ?hardware-fixed arbitration? in the pci express base r1.0a ? alternate between vc0 and vc1 weighted round-robin (wrr) with 32 phases ? select vc0 or vc1, based on 32 values programmed with the vc&t arbitration table (refer to table 8-3 ) the strict priority selection is made by clearing the port vc capability 1 register low-priority extended vc count bit to 0. the default value is strict priority, and can only be changed by serial eeprom initialization. if the low-priority extended vc count bit is set to 1 (by way of serial eeprom), then vc0 and vc1 share the low-priority pool. within the low-prio rity pool, round-robin or weighted round-robin arbitration can be selected. the port vc capability 2 register vc arbitration capability bits (offset 150h [1:0]) describe the two types of vc arbitration for mechanisms supported by the pex 8524. the port vc control register vc arbitration select bit (offset 154h [1]) defines programming. when using weighted round-robin, the 32-phase vc arbitration table must be programmed before loading the table. table entries represent one phase that is loaded by software with a low-priority vc id value. the vc arbiter repeatedly sequentially scans all table entries, and transmits transactions from the vc buffer specified in the table entries. after a transaction is dispatched, the arbiter moves to the next phase. (refer to table 8-3 and the vc arbitration table phase n register.) table 8-3. virtual channel arbitration table register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 phase 7phase 6phase 5phase 4pha se 3 phase 2 phase 1 phase 0 1b8h phase 15 phase 14 phase 13 phase 12 phase 11 phase 10 phase 9 phase 8 1bch phase 23 phase 22 phase 21 phase 20 phase 19 phase 18 phase 17 phase 16 1c0h phase 31 phase 30 phase 29 phase 28 phase 27 phase 26 phase 25 phase 24 1c4h
performance metrics plx technology, inc. 142 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 egress port arbitration regarding egress ports, the pex 8524 supports only one port arbitration mechanism ? non-configurable hardware arbitration scheme. in particular, the oldest ready packet from all ingress ports arriving at the current egress port are selected first. ready packet is defined as a packet with available egress credit and no ordering violations. 8.4 throughput 8.4.1 theoretical upper limit pci express allows for bi-directional traffic capability and scalable widths, allowing it to closely match the necessary bandwidth. as discussed in this s ection, compared to the 2.5-gbps raw bandwidth provided by each serdes lane, the achievable data payload efficiency, assume the maximum payload size (mps) of 256b is approximately 70%. 8.4.1.1 physical layer overhead the 2.5-gbps serial data on a serdes is encoded with additional information for clock recovery and error detection through 8b/10b encoding. when the additional information is removed, a 2.0-gbps data rate remains, which is 80% of the starting bandwidth. the phy layer also adds a 1-byte start symbol (stp ) and a 1-byte end symbol (end or edb) to the packet size, thereby introducing 2 bytes of overhead per tlp. also in the phy layer, skip ordered-sets are used to compensate for differences in frequency between bit rates at opposite ends of a link. the pci express base r1.0a specifies a clock frequency tolerance of 600 parts per million (ppm), which in turn requires a skip ordered-sets to transmit within the range of 1,180 to 1,530 symbol times. this causes the achievable efficiency to drop another 4/1,180 = 0.34%. 8.4.1.2 data link layer overhead to ensure data integrity passing over the wire, the pci express base r1.0a states that the dll (data link layer) adds a sequence number at the start of the packet and an lcrc inte grity check at the end of the packet. the sequence number is 2 bytes, and the lcrc is 4 bytes, thereby introducing 6 bytes of overhead per tlp. in addition to the overhead inherent in tlp payload transmission, the pci express base r1.0a uses the same wire to transmit dllps (data link layer packets). ack (acknowledge) and updatefc are the two most frequently used types of dllps during standard run time, where throughput matters. ack is used to acknowledge tlp receipt. updatefc is used to provide additional credits, which enables additional tlp transactions. dllps are structured so that a single ack can re present receiving multiple tlps, reducing the total number of acks required. similarly, a single update fc is structured so that credit for more than one packet can be extended at a time, reducing the number of required updatefcs per tlp. the size of a single dllp is 8 bytes. in the worst case, two outgoing dllps are formed for each incoming tlp, which equals 16b in per tlp overhead. in the best case, there is zero dllp overhead for incoming tlps. dllps flow in the opposite direction of tlp s, as they are feedback mechanisms. for one-way tlp traffic, the dllp overhead does not impact overall link utilization.
february, 2007 theoretical upper limit expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 143 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8.4.1.3 transaction layer overhead all pci express payloads are encapsulated in a tlp. a tlp contains a header portion that provides the pex 8524 with routing information for the packet. the header can be 12 or 16 bytes. according to the pci express base r1.0a , maximum payload size (mps) can range from 128 to 4,096 bytes. the pex 8524 supports mps of up to 256 bytes. the device control register maximum payload size field (offset 70h [ 7:5 ]) default mps is 128 bytes. software can change the default value; however, the entire syst em must have a consistent mps. in general, longer payloads are mo re efficient, but require more on- chip resources to buffer, and can cause much worse hot spot congestion in bursty traffic flows. a tlp can also incur additional overhead when end-to-end data integrity is essential. in such cases, a 4-byte ecrc is added as another type of overhead to the end of the packet. note: refer to the device control register maximum payload size field (offset 70h[7:5]) for mps limitations. 8.4.1.4 pci express effici ency upper bound summary table 8-4 summarizes pci express inherent efficiency for 0b, 4b, 8b, 40b, 128b, 256b, and 4,096b payload sizes on various negotiated link widths. the 4,096b table row is provided for reference only, as the pex 8524 supports mps of up to 256 bytes. the table columns provide th ree types of variations: comparing to raw serdes bandwidth of 2.5 gb ps versus 2.0 gbps after 8b/10b decoding. 0% additional dllp generation versus 100% dllp generation, assuming traffic is equal in both directions. 0% dllp assumes that dllp traf fic is not injected into the tlp stream, such as a uni-directional traffic stream. 100 % dllp assumes that for every tlp transmitted, an additional ack dllp and updatefc dllp are generated in the reverse direction fo r a bi-directional fully loaded traffic stream. non-payload tlp overhead of 12b versus 20b (16b header + ecrc). in summary, the larger the payload, the more effi cient the pci express communication. for 256-byte maximum payload size supported by the pex 8524, the limit efficiency compared to the raw 2.5-gbps bandwidth is between 68 to 73.92%. note: not all factors are reflected in this table. skip ordered-set drops another 0.3%. any credit shortage or transient congestion can significantly drop. table 8-4. throughput theoretical upper limit bytes of payload 2.5 gbps raw bandwidth 2.0 gbps raw bandwidth after 8b/10b decoding 0% dllp 100% dllp 0% dllp 100% dllp 12b 20b+ 12b 20b+ 12b 20b+ 12b 20b+ ecrc 0 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 4 13.28% 10.00% 8.00% 6.64% 16.60% 12.50% 10.00% 8.30% 8 22.80% 17.68% 14.48% 12.24% 28.50% 22.10% 18.10% 15.30% 40 53.12% 46.88% 42.00% 38.00% 66.40% 58.60% 52.50% 47.50% 128 68.96% 65.44% 62.24% 59.36% 86.20% 81.80% 77.80% 74.20% 256 73.92% 71.84% 69.92% 68.00% 92.40% 89.80% 87.40% 85.00% 4,096 79.36% 79.20% 79.04% 78.88% 99.20% 99.00% 98.80% 98.60%
performance metrics plx technology, inc. 144 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8.4.2 single-stream throughput when data flows in a single-packet stream from a fixed-ingress to fixed-egress port, its throughput can be optimized on both the ingress and egress sides. the method for optimizing throughput on both sides is discussed in the following sections. 8.4.2.1 ingress side accept more than one packet in same symbol time the pex 8524 ingress port is design ed to accept incoming traffic at the fastest rate possible. for x8 ports, the pex 8524 allows the ending part of a tlp and beginning part of the next tlp to arrive in the same symbol time. it also allows a partial tlp and a partial or full dllp to simultaneously arrive. optimize ingress credit allocation a tlp cannot be transmitted to the switch without the switch providing sufficient ingress credits beforehand. when a credit is advertised, it indi cates a guaranteed storag e available in the credit transmitter at that time. if there is insufficient or untimely ingress credits advertised from the pex 8524 to its link partner, the incoming tlp stream does not sustain at the highest possible rate. amount of ingress credit required calculation the pex 8524 supports up to six vc &ts per port. the amount of in gress credits advertised in each vc&t is expected to be sufficient to cover the round-trip delay from the time the external device schedules a tlp for transmission in its transactio n layer to the time the external device receives the replenishing credit from the pex 8524 in the same vc&t. to enable a burst of tlps of the same vc&t to enter the pex 8524 without interruption, use the following empirical equation: ingress_credit_advertised = (round_trip_time_in_symbol times x link_width) / packet_size_in_bytes round-trip latency, which can range from 160 to 400 ns (40 to 100 symbol times), is determined by both the pex 8524 and external device and consists of the following: latency for incoming tlp to travel the entire pex 8524 ingress data path delay from writing the first byte of the packet into ingress packet ram until writing the last byte of the packet into ingress packet ram latency for source scheduler to transmit the pack et to egress packet ram and free up the ingress buffers for this tlp packet latency for the pex 8524?s ingress credit scheduler to generate an updatefc packet latency for this updatefc dllp to travel the pex 8524 egress data path to serdes delay in serdes latency for this updatefc dllp to travel the ingress data path of the external device latency for external device to process the updatefc dllp and update its credit limit counter latency for external device to schedule the next tlp in the same vc&t out latency for the external device to move the new tlp across its egress data path to the serdes final delay in serdes for example , suppose a link with a 400 ns round-trip time contains eight lanes and a stream of posted transactions is broken into p ackets of 64b payload each. the amoun t of posted type header credit needed to sustain a steady incoming traffic flow is approximately 100 x 8 / (16 + 64) = 10.
february, 2007 single-stream throughput expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 145 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 the smaller the payload size, the higher demand on the ingress header credit to be advertised. using the same example provided above, but changing payload size from 64b to 4b, the number of ingress header credits required is 40. as previously stated, the pex 8524 contains a total of 32 voq entries in its ingress ports. although 30 voq entries can be allocated to the posted traffic, there is no way to sustain the incoming traffic without stal ling due to lack of credits. program ingress credit threshold rules the pex 8524 provides the capability to program the ingress credit va lue for each vc&t in the ingress ports. refer to section 11.13.8.1, ?inch threshold port virtual channel registers,? to view the registers used to program the in gress credit value. the register s range from offsets a00h to a5ch. in the inch threshold port virtual channel registers, header credit and payload credit thresholds are writable. the following rules are used to program these registers: one unit of header credit threshold represents one packet. a value of 1 allows the pex 8524 to advertise 1 header credit, 2 allows 2 header credits, and so forth. bits [13:9] allow a maximum of 31 header credits to be programmed to vc&t. one unit of payload credit threshold represen ts 16b of data. when the pex 8524 maximum payload size is set as 25 6, a value of at least 16 is required to be pr ogrammed for posted and completion packets. bits [8:0] allow a maximum value of 2 9 payload credit units to be advertised. for posted and completion types, bits [2:0] are reserved , which forces the payload credit threshold to be powers of 8. this effectively makes the granularity for posted and completion credit threshold types increase to 16b x 8 = 128b. for non-posted types, similar restrictions do not apply, because the payload size is never more than 4b. for all ingress vc&ts, the total header credit cannot exceed 32 in a port. for all vc&ts in all potential ports in a source station, the total payload credit cannot exceed 1,376. the default ingress header credit threshold for vc0 posted, non-posted, and completion types are as follows: silicon revision aa ? 5, 9, and 5, respectively silicon revisions bb, bc ? 12, 7, and 10 respectively the default ingress data payload credit threshold for vc0 posted, non-posted, and completion types are as follows: silicon revision aa ? 88, 9, and 88, respectively silicon revisions bb, bc ? 144, 7, and 128 respectively it is strongly recommended that to achieve better ingress throughput for a particular type, fine-tuning ingress credit thresholds is an indispensable step. for example , when the pex 8524 is ?talking? to a x8 graphics board, almost 28.5% throughput boost is observed by modifying the ingress header credit for vc0 posted, non-posted, and completion types to be 15, 4, 13, and ingress payload credit to be 40, 4, and 40, respectively.
performance metrics plx technology, inc. 146 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 ingress credit threshold programming there are methods for changing the ingress credit threshold ? by way of a serial eeprom or direct csr programming. the first approach is straightforward ? program the required values and the link produces the programmed values. however, the latter approach requires further explanation. in the direct csr programming method, if a credit threshold requires an increase, perform a csr write. this immediately results in a new updatefc to be transmitted, carrying the ne wly increased credits. in contrast, if a credit thres hold requires a decrease, the pci express base r1.0a does not provide a pre-defined method for reclaiming unused credit prev iously advertised to the external device. the danger of programming a smaller credit threshold than the initial value is that ingress packet storage can overflow if the external device is not aware of th e credit threshold, and continues sending packets according to the initial credit thre shold. use the following approach to avoid packet ram overflow: upstream port ? use csr access to program the vc&ts whose credit requires a decrease. ? transmit ?side-impact free? traffi c from host to those vc&ts, to deplete all credits to be reclaimed. before the surplus credits are co mpletely reclaimed, the pex 8524 transmits updatefc for that vc&t. after the amount of incoming traffic attains the difference between the old and new credit thresholds, the pex 8524 starts transmitting fresh updatefc dllps for incoming tlps. downstream ports ? program all ingress credit threshold csrs in all vc&ts to the required values. ? execute a secondary bus reset in the bridge control register (offset 3ch [ 22 ]=1) ? release the reset. the newly programmed values take effect afterward. ingress credit threshold registers are not sticky after a primary rese t; therefore, this sequence requires repeating after any primary reset. tip: if a serial eeprom is available and you want to experiment with credit values, initially program all thresholds to 1. there is no impact in increasing the credit (up to the maximum of pex 8524 resources). this allows for the most flexibility in your experiments. 8.4.2.2 egress side provide sufficient egress credit the simplest way to improve an egress port?s throughput is to provide the pex 8524 with sufficient egress credit. in general, the number of egress credit required by the pex 8524 follows the same equation as the ingr ess credit calculation: egress_credit_required = (round_trip_time_in_clocks x link_width) / packet_size_in_bytes for the pex 8524 to achieve pipelined performance, the external device is suggested to advertise at least two mps worth of payload credits. for 128b mps, th e payload credit is greater than or equal to 16 (16 credits = 296b = 2 mps). for 256b mps, the payl oad credit must be greater than or equal to 32 (2 mps). although a packet?s payload is smaller than mps, without a 2 mps credit, the pex 8524 schedules one packet out, waits for the updatefc to return, then schedules the next packet out.
february, 2007 multiple stream throughput expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 147 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 egress schedulers select frequency to simplify the egress scheduler design, one limitation incurred is that one packet can be scheduled out every other clock cycle. for port widths narrower than x16, this restriction does not cause a performance degradation. for station 1 x16 port widths, the throughput of header-only packets (16b or less) is not sustained. x8 and x16 port pad slots when a pex 8524 port is configured as x8 or x16 (station 1 only), only bytes belonging to one tlp are transmitted in single-symbol time. the residue lanes are filled with pad. also, for x8 or x16 ports, the pex 8524 does not attempt to optimize throughput by placing a partial tlp and dllp in single-symbol time. 8.4.3 multiple stream throughput 8.4.3.1 enable plx-speci fic relaxed ordering the pex 8524 does not support optional relaxed ordering bits in tlp, as specified in the pci express base r1.0a , table 2-23. by default, all packets en tering from a specific port are dispatched to their respective destinatio ns, based on strict ordering. however, as described in section 8.3.2.1, ?source scheduler,? the pex 8524 provides its own relaxed ordering to overcome the packet-to-p acket dependency in a burst of posted traffic from the same ingress port, but to different egress ports. 8.4.3.2 avoid hot spots a hot spot forms when multiple ingress ports attempt to transmit packets to the same egress port, and the overall influx bandwidth outweighs the efflux bandwidt h. if the hot spot is not transient, the hot spot port throughput can appear high. however, eventually the egress queues fill, backpressuring the ingress queues. when the ingress queues f ill, ingress traffic is backpressured, potentially impacting traffic flow not targeting the congested egress port. as a result, the switch overall average throughput is dramatically reduced. pci express do es not provide a mechanism to rec ognize and avoid hot spots. it is therefore left to the system designers to understand and avoid this pitfall. 8.4.4 throughput and packet size relationship in general, sustained throughput increases as payl oad size increases due to the increased pci express protocol efficiency. however, the following secondary effects can also affect throughput: in peer-to-peer applications, long er packets can result in less interleaved or randomized egress port distribution compared to shorter packets. th is increases the chance of building up transient congestion in egress ports, and can negatively impact overall throughput. longer packets require fewer header credits per uni t time, and are therefore less likely to idle the link while waiting for ad ditional header credit. longer packets burn up payload credits faster a nd can stall dllps behind the long tlp longer, potentially causing credit starvati on. if there is insufficient link cr edit (3 tlps worth or more), shorter packets may provide better throughput. posted packets block younger packets of other types (non-posted and completions). in a system with minimal credits, posted packets shou ld receive the strongest consideration when allocating credits. it is recommended to carefully compare the benefits and draw backs of using longer packets.
performance metrics plx technology, inc. 148 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8.4.5 data link layer considerations 8.4.5.1 arbitration between dllp and tlp to reduce dllp overhead on the wire, the pex 8524 uses the following fixed-priority scheme to determine what transmits next: 1. completion of a tlp or dllp currently in transmission. 2. initialization flow control (fc-init) dllps. 3. nak dllp. 4. ack dllp, due to receipt of a duplicate tlp or ack latency timer expiration. * 5. update fc dllp, due to the fc update pending timer expiration. * 6. retry buffer tlp, due to received nak or retry timeout. 7. new tlps. * 8. update fc dllp, due to cha nge in available credits. * 9. power management dllp. 10. ack dllp for the last received tlp. * among these ten categories, the five most frequently seen new packets are noted with an asterisk ( *) . updated-fc, initfc, and ack dllps appear twice ? once as higher priority than tlps, and once as lower priority than tlps. a regular dllp turns into a higher priority dllp based on a programmable timer. the basic idea is to reduce the number of dllps, the timers provide the opportunity to collapse multiple dllps into 1. the timer s are discussed in sections 8.4.5.2 and 8.4.5.3 . 8.4.5.2 dllp ack frequency control the ack transmission latency limit register (offset 1f8h ) indicates a minimum amount of time (in 4 ns clocks) that the switch waits before prioritizing an ack. by setting this register to the minimum value of 2 (refer to note below), acks are typically always transmitted with high priority, allowing the most dllp traffic and the smallest possible re try buffer in the other device on the link. note: 2 is the minimum value that has an effect; 0 or 1 wait for 255 clocks. the larger the number written into this csr, th e larger the chance of ack collapse, and the more efficient the outgoing tlp throughput can be. however, by setting the ack transmission latency limit to the maximum (255), 255 symbol times (4 ns each) to occur before prioritizing an ack. if the retry buffer in the external device is not sufficiently deep, it can slow the incoming tlp rate. on a x4 link, 1,020b can be transmitted in 255 symbol times, which is 51 20b packets. the extern al device would need to have a retry buffer that could store more than 51 tlps, so as not to im pact the back-to-back burst of incoming tlps. because programming a smaller value into this cs r decreases egress tlp throughput but can increase the ingress tlp throughput, a tradeoff must be addressed. if there is no tlp traffic, an ack can be transmit ted earlier than the timer in dicates as a low-priority dllp. the initial value depends on the programmed link width. however, the value can be overwritten by serial eeprom or a regular csr write.
february, 2007 data link layer considerations expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 149 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8.4.5.3 dllp updatefc frequency control the inch fc update pending timer register (offset 9f4h ) controls the amount of time a port can wait before prioritizing an updatefc dllp. before the timer expires, tlps have priority over updatefc dllps. after the timer expires, updatefc dllps move to higher priority. the value programmed into this csr is a counter expiration value. all six vc&ts in an ingress port share the same counter upper li mit; however, each has its own se t of counters, for counting up. the smaller the value written into these register s, the sooner an update fc dllp becomes higher priority; therefore, the sooner the updatefc dllp is tran smitted. the sooner an updatefc is transmitted, the less likely the chance to collapse tw o vc&t updatefcs. however, even for small timer values, only one updatefc is typically sent per each incoming tlp. the updatefc is broken into multiple dllps for each incoming tlp only if ther e are insufficient resources to replace the credit. note: each vc and type has its own updatefc. only updatefcs for the same vc&t can be collapsed. the pci express base r1.0a guidelines for the fc update pending timer are provided in table 8-5 . for implementation, a value of 01h or 00h into the csr results in waiting 255 symbol times. the smallest value is 10h. the initial value of 00h is effectively 255 symbol times. table 8-5. fc update pending timer guidelines maximum packet size link width recommended timer count 128 bytes x1 76h x2 40h x4 24h x8 21h x16 (station 1 only) 18h 256 bytes x1 d0h x2 6ch x4 3bh x8 36h x16 (station 1 only) 24h
performance metrics plx technology, inc. 150 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8.5 latency 8.5.1 queuing effect in switches with large internal buffers, the late ncy increases once internal queuing is developed. the packet at the end of an egress vc&t queue does not transmit until all packets in front of it are transmitted. assume the egress ram of a x4 port is packed with packets of the same vc&t, draining the entire egress ram takes 2,560 clocks (512 b eats x 20b per beat / 4b/clock). worst-case packet latency can be as long as 10 s. to overcome the queuing effect, attempt the following: avoid creating hot spots. in particular, ensure that the upstream port width in a host-centric application matches the sum width of all active do wnstream ports. otherw ise, the upstream port can easily become a hot spot when all downstream ports are attempting to transmit packets to it. program a small egress queue packet upper and lower limit, to av oid packet accumulation in an egress port. section 8.3.2.4 describes how to program these thresholds. lower latency is achieved at the cost of reducing the pex 8524?s cap ability to buffer transient congestion. reduce traffic load. lighter traffic is less likely to experience congestion and can drain relatively faster, as the egress links can drain at the full link rate. 8.5.2 time division multiplex effect as previously illustrated, the pex 8524 source stat ion employs port-to-station aggregation, and the destination station employs station-to-port de-aggregation. time division multiplex (tdm) controls aggregation and de-aggregation. usually, waiting for a proper tdm slot to process packet coming from or going to a particular port increases the latency. the wider the port, the more tdm slots that port owns; therefore, the less latency contributed by tdm. within a station, only a subset of 8 lanes for station 0 and up to 16 lanes for station 1 are connected to serdes. one approach to reduce latency is to strap the port as a wider port and allow it to negotiate down to the expected link width. for example, if there is only a x2 port ow ned by a station, the port can be strapped as x8 (station 0) or x16 (station 1), and allowed to become x2 later through the normal link training process. as a result, all tdm slots in this station are acquired by the x2 port. the worst case tdm effect for a x1 or x2 port is 14 symbol times = 57 ns.
february, 2007 high-priority packets expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 151 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8.5.3 high-priority packets the previous sections discussed methods for opti mizing latency in a single vc system. however, a better solution for some traffic scenarios that require consistently low latency is to use a different vc. the pex 8524 does not support isochronous traffic that requires high-priority packets by way of a switch with a time limit. however, it does provide a high-priority packet path throughout the entire switch if there are two vcs and vc1 is configured with higher priority compared to vc0 in both the ingress and egress ports. vc1 includes independent credit, storage, and schedu ling with respect to vc0. however, it shares the wires in and out of the switch. at any point where there can be congestion between the two vcs, vc1 is treated separately and preferentially to vc0. this occurs at the ingress queu es, internal fabric, and egress queues. for contention, vc1 packets are given priority over vc0 packets. in this case, vc0 is earmarked for slower, bulk da ta transfer, and vc1 processes packets with a much shorter latency if there is no over-subscription. two conditions are required to make the high-priority path meaningful: tc/vc mapping is symmetric across all ports all ports configure the low-priority ex tended vc count as 0, in the egress port vc capability 1 register (offset 14ch ; default) to give vc1 the higher priority certain tcs map to vc1 [ vc0 resource control or vc1 resource control registers (offsets 15ch and 168h , respectively)] and the high-priorit y tlps use the tcs that map to vc1 vc1 is enabled on ingress and egress ports 8.5.4 smaller size packets the pex 8524 uses a store-and-forwar d architecture. without cut throu gh, a packet must be completely written into the pex 8524?s internal packet ram before the first byte of the packet can be transmitted out of the egress port. fall-through latency is a function of the packet size; therefore, the smaller the packet size, the shorter the fall-thro ugh latency. the bulk of the latency is dictated by the amount of time it takes for the packet to arrive. narrower ingress ports contain correspondingly higher latency than wider egress ports. 8.5.5 power management saving power and optimizing latency are typically tw o conflicting tasks. after a chip enters power saving mode, the wakeup time when new burst packets arrive always contributes to latency. for latency-sensitive applications, it is recommended to use software to turn off the aspm l0s entrance/ exit, as well as the l1 entrance/exit.
performance metrics plx technology, inc. 152 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 this page intentionally left blank.
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 153 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 9 hot plug support 9.1 hot plug purpose and capability note: the pex 8524?s hot plug controllers are compliant with the pci hot plug r1.1 and pci standard hot plug controller and subsystem r1.0. hot plug capability allows board insertion and extraction from a running system, without adversely affecting the system. boards are typical ly inserted or extracted to repair faulty boards or re-configure the system without system down time. hot plug capability allows systems to isolate faulty boards in the event of a failure. the pex 8524 includes one hot plug controller per downstream port. 9.1.1 hot plug controller capabilities insertion and removal of pci express boards, without removing system power board-present and mrl (manually operated re tention latch) sensor signals supported power indicator and attention indicator output signals controlled attention button monitored power fault detection and faulty board isolation power switch for controlling downstream device power generates pme (power management event) for hot plug events in sleeping systems (d3hot) presence detect is accomplished through an in-band serdes receiver detect mechanism or by using the hp_prsnt x # signal hot plug interrupts can be sent in-band using int x or msi messages
hot plug support plx technology, inc. 154 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 9.1.2 hot plug port external signals the pex 8524?s hot plug controllers include ni ne hot plug signals for each pci express port (6 ports x 9 signals/port = 54 total signals), defined in table 9-1 . (refer to table 3-5, ?pex 8524vaa/ bb/bc hot plug signals, 680-ball pbga ? 54 balls,? or table 3-12, ?pex 8524bb/bc hot plug signals, 644-ball pbga ? 54 balls,? for signal-to-ball mapping.) table 9-1. hot plug signals signal name type description hp_atnled x #o hot plug attention led output per port active-low slot control logic output used to drive the attention indicator. output is set low to turn on the led. enabled when the slot capabilities register attention indicator present bit is set (offset 7ch [3]=1) and controlled by the slot control register attention indicator control field (offset 80h [7:6]). when software writes any value other than 00b ( reserved ) to the attention indicator control field and an attention_indi cator message is sent to the downstream device, a command completed interrupt can be generate d to notify the host that the command has been executed. when the following conditions exist: slot capabilities register attention indicator present bit is set (offset 7ch[3]=1), and slot control register command completed interrupt enable bit is not masked (offset 80h[4]=1), and slot control register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated to the host. an external current-limitin g resistor is required. hp_button x # i pu hot plug attention button input per port active-low slot control logic input , directly connected to the attention button, with input assertion status latched in the slot status register attention button pressed field (offset 80h[16]). enabled when the slot capabilities register attention button present bit is set (offset 7ch[0]=1). when the following conditions exist: hp_button x # is not masked ( slot control register attention button pressed enable bit (offset 80h [0]=1), and slot capabilities register hot plug capable bit is set (offset 7ch[6]=1), and slot control register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) ca n be generated, to notify the host of intended board insertion or removal. note: hp_buttonx# is internally de-bounced, bu t must remain stable for at least 10 ms. hp_clken x #o reference clock enable output per port active-low output that, when enabled, allows external refclk to be provided to the slot. enabled when the slot capabilities register power controller present bit is set (offset 7ch [1]=1), and controlled by the slot control register power controller control bit (offset 80h [10]). the time delay from hp_pwren x # output assertion to hp_clken x # output assertion is programmable (through serial eeprom load) from 16 ms (default) to 128 ms, in the hpc tpepv delay field (offset 1e0h [4:3]).
february, 2007 hot plug port external signals expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 155 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 hp_mrl x # i pu hot plug manually operated retention latch sensor input per port active-low input that tr iggers slot control logic. directly connected to an optional mrl sensor that is logic high when the latch is not closed. hp_mrl x # input assertion enables hot plug output sequencing to turn on the slot?s power (hp_pwren x # and hp_pwrled x #) and clock (hp_clken x #), and de-assert reset (hp_perst x #) after reset or under software control. a change in the hp_mrl x # input signal state is latched in the slot status register mrl sensor changed bit (offset 80h[18]), and the st ate change can assert an inte rrupt to notify the host of a change in the mrl sensor state. when the following conditions exist: hp_mrl x # is not masked ( slot control register mrl sensor changed enable bit, offset 80h[2]=1), and slot control register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually excl usive) can be generated. if the associated hot plug-capable downstream port connects to a pci expre ss board slot that does not implement an mrl sensor, hp_mrl x # is normally connected to hp_prsnt x # and a pull-up resistor, with the common node connected to the prsnt2# signal(s) at the slot. if the associated hot plug-capable downstream port instead connects directly to a device (in which case hot plug is not used), pull hp_mrl x # low. note: hp_mrlx# is internally de-bounced, bu t must remain stable for at least 10 ms. hp_mrlx#, if enabled, is not de-bounced when sampled immediately after reset. hp_perst x #o reset output per port active-low hot plug output used to reset the slot. controlled by the slot control register power controller control bit (offset 80h[10]). hp_prsnt x # i pu combination of hot plug prsnt1# and prsnt2# input per port active-low input connected to th e slot?s prsnt2# signal, which on the add-in board connects to the slot?s prsnt1# signal, which is normally grounded on the prsnt2# signal at the motherboard slot. a change in the hp_prsnt x # input signal state is latched in the slot status register presence detect changed bit (offset 80h [19]), and the state change can assert an interrupt to notify the host of board presence or absence. when the following conditions exist: hp_prsnt x # is not masked ( slot control register presence detect changed enable bit (offset 80h[3]=1), and slot control register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually excl usive) can be generated. note: hp_prsntx# is internally de-bounced, bu t must remain stable for at least 10 ms. table 9-1. hot plug signals (cont.) signal name type description
hot plug support plx technology, inc. 156 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: if hot plug outputs (including hp_perstx#) are used a nd hp_mrlx# input is not used, pull hp_mrlx# low so that hot plug outputs (including hp_perstx#) will properly sequence if the serial eeprom is blank or missing. default register values enable hp_mrlx# , which must then be asserted to cause hot plug outputs to toggle (for example, to de-assert hp_perstx# and assert hp_pwrledx#). hp_pwren x #o active-low hot plug power enable output per port active-low slot control logic out put that controls the slot powe r state. when this signal is low, power is enabled to the slot. enabled when the slot capabilities register power controller present bit is set (offset 7ch [1]=1). when software turns the slot?s power controller on or off ( slot control register power controller control bit, offset 80h [10]), a command completed interrupt ca n be generated to notify the host that the command has been executed. when the following conditions exist: slot control register command completed interrupt enable bit is not masked (offset 80h[4]=1), and slot control register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated to the host. when hp_mrl x # is enabled [ slot capabilities register mrl sensor present bit is set (offset 7ch[2]=1)], hp_mrl x # input assertion enables hot plug output sequencing to turn on the slot?s power, by asserting hp_pwren x # after reset or unde r software control. hp_pwrflt x # i pu hot plug power fault input per port active-low input that indicates th e slot?s external power controlle r detected a power fault on one or more supply rails. enabled when the slot capabilities register power controller present bit is set (offset 7ch [1]=1), and input assertion stat us is latched in the slot status register power fault detected (offset 80h [17]). when the following conditions exist: hp_pwrflt x # is not masked ( slot control register power fault detector enable bit (offset 80h[1]=1), and slot control register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated, to notify the host of a power fault. note: if hp_pwrenx# and hp_clkenx# are not used, hp_pwrfltx# can be used as a general-purpose input with status reflected in the slot status register power fault detected (offset 80h[17]), provided the slot capabilities register power controll er present bit is set (offset 7ch[1]=1). hp_pwrled x #o hot plug power led output per port active-low slot control logic output used to driv e the power indicator. this output is set low to turn on the led. enabled when the slot capabilities register power indicator present bit is set (offset 7ch[4]=1), and controlled by the slot status register power indicator control field (offset 80h[9:8]). when software writes any value other than 00b ( reserved ) to the power indicator control field and a power_indicator message is sent to the downstream devi ce, a command completed interrupt can be generated to notify the ho st that the command has been executed. when the following conditions exist: slot capabilities register power indicator present bit is set (offset 7ch[4]=1), and slot control register command completed interrupt enable bit is not masked (offset 80h[4]=1), and slot control register hot plug interrupt enable bit is set (offset 80h[5]=1), an interrupt (msi, or int x message, both mutually exclusive) can be generated to the host. an external current-limi ting resistor is required. table 9-1. hot plug signals (cont.) signal name type description
february, 2007 hot plug output signal states for disabled hot plug slots expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 157 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 9.1.3 hot plug output signal states for disabled hot plug slots when a hot plug slot is disabled, the hot plug output balls for that port are in the logic states defined in table 9-2 . 9.2 pci express capability registers for hot plug the hot plug configuration, capability, command, status, and events are described in section 11.9, ?pci express capability registers.? the applicable registers are as follows: slot capabilities (offset 7ch ) slot status and control (offset 80h ) note: hot plug slot status and other hot plug control-related registers are ?don?t care? for the nt port virtual interface, and should not be modified by the user. table 9-2. hot plug outputs for disabled hot plug slot output signal logic comments hp_atnled x # high attention led is turned off hp_clken x # high reference clock is not driven to the slot hp_perst x # low slot remains in reset hp_pwren x # high power controller is turned off hp_pwrled x # high power led is turned off
hot plug support plx technology, inc. 158 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 9.3 hot plug interrupts each hot plug controller supports hot plug interrupt generation on the following events: attention button pressed power fault detected mrl sensor changed presence detect changed command completed hot plug interrupts can be signaled by in-band int x or msi messages. only one interrupt mechanism can be selected, and all hot plug ports must use the same mechanism. int x interrupts are enabled if: inta messages are enabled ( command register interrupt disable bit, offset 04h [10]=0) and, msi is disabled ( message control register msi enable bit, offset 48h [16]=0) msi interrupts are enabled if: inta messages are disabled ( command register interrupt disable bit, offset 04h[10]=1) and, msi is enabled ( message control register msi enable bit, offset 48h[16]=1) depending on the downstream port power state, a ho t plug event can generate a system interrupt or pme. when a pex 8524 downstream port is in the d0 power state, hot plug events generate a system interrupt; when not in the d0 state, a pme interrupt message is generated by hot plug events. the slot status register command completed bit (offset 80h [20]) does not generate a pme interrupt message. when the system is in sleep mode, hot plug operation uses pme logic to wake up the system. 9.4 hot plug controller power-up/down sequence if a transparent downstream port is enabled, the port?s hot plug controller can power-up or power-down the slot. this section describes how this process occurs. 9.4.1 slot power-up sequence if a downstream port is connected to a slot, that port?s hot plug controller can power up the slot, with or without an external serial eeprom. hot plug contro ller sequencing is determined by the states of the following bits: slot capabilities register power controller present bit (offset 7ch [1]) slot capabilities register mrl sensor present bit (offset 7ch[2]) (mrl is manually operated retention latch) slot control register power controller control bit (offset 80h [10]) and the hp_mrl x # input state, if the mrl sensor present bit is set to 1. hot plug-configurable features are programmable only by the serial eeprom.
february, 2007 slot power-up sequence expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 159 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 9.4.1.1 configuring hot pl ug controller slot power- up sequence features with serial eeprom an external serial eeprom can be used to configure the hot plug controller and hot plug outputs. features can be changed by using the registers defined in table 9-3 . the hot plug controller outputs remain in the default state described in table 9-2 , before the serial eeprom image is loaded into the device. after the serial eeprom image is loaded, the hot plug controller starts a power-up sequence on each slot that has the slot capabilities register power controller present bit set (offset 7ch [1]=1) and the slot control register power controller control bit cleared (offset 80h [10]=0). table 9-3. configuring power-up se quence features with serial eeprom register bit hot plug controller and hot plug output signal configurable features power controller present ( slot capabilities register, offset 7ch [1]) the power controller present bit enables or disables the hot plug controller on the pex 8524 downstream ports. if the power controller present bit is cleared to 0, the hot plug controller is disabled for that slot and a power-up sequence is not execut ed. the slot remains in the disabled state, as defined in table 9-2 . if the power controller present bit is enabled (set to 1), the hot plug controller powers up the slot when the mrl is closed and the slot control register power controller control bit is cleared (offset 80h[10]= 0). otherwise, if the mrl sensor present bit is disabled (cleared to 0), the mrl?s position has no effect on powering up the slot. mrl sensor present ( slot capabilities register, offset 7ch [2]) when enabled (set to 1), the pex 8524 senses wh ether the mrl is open or closed for a slot. if this bit is set to 1, the mrl shou ld be low for power-on for that slot. if this bit is cleared to 0, the mrl pos ition is ?don?t care? for that slot. hpc tpepv delay ( power management hot plug user configuration register, offset 1e0h [4:3]) this field controls the delay from when hp_pwren x # is asserted low, to when power is valid at a slot. (refer to section 9.4.1.2 .) this register is read -only and can be set by serial eeprom. values for this field are as follows: bits [4:3] delay value 00b 16 ms (default) 01b 32 ms 10b 64 ms 11b 128 ms hpc tpvperl delay ( power management hot plug user configuration register, offset 1e0h [6]) this bit controls the delay from when powe r is valid at the slot to when hp_perst x # is de-asserted high. (refer to section 9.4.1.2 .) two settings can be specified through the serial eeprom: bit 6 delay value 0 20 ms 1 100 ms (default) attention indicator present ( slot capabilities register, offset 7ch [3]) when set to 1, this bit controls whether the hp_atnled x # output for the slot drives out active-low. otherwise, this output is not functional on the slot. power indicator present ( slot capabilities register, offset 7ch [4]) when set to 1, this bit controls whether the hp_pwrled x # output for the slot drives out active-low. otherwise, this output is not functional on the slot.
hot plug support plx technology, inc. 160 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 9.4.1.2 slot power-up sequencing when power controller present bit is set by default, the power controller present , mrl sensor present , and power controller control (when the mrl is open) bits are set to 1. when the se rial eeprom is not presen t, present but blank, or programmed with default register values, the hot plug controller is initially powered up, and the pex 8524 is in the following state: 1. hot plug controller is enabled for all slots. 2. all slots are enabled to be powered up. 3. attention led (hp_atnled x #) and power led (hp_pwrled x #) are high on the slot chassis. immediately after the pex 8524 exits reset ( pex_perst# input goes high), if a downstream port?s mrl sensor present bit is set to 1 (default), the hp_mrl x # input for that slot is sampled. if the hp_mrl x # input is enabled and asserted (v alue of 0), the pex 8524 clears the power controller control bit to 0, to enable slot power-up. if the power controller control bit is not cleared, either by initially enabling it (default) and asserting hp_mrl x #, or by programming both the mrl sensor present and power controller control bit values to 0 in the serial eeprom, the downstream slot is not powered up and remains in the disabled state, as defined in table 9-2 and illustrated in figure 9-3 . if a slot?s power controller present bit is set to 1, and the power controller control bit is cleared to 0 (either by initially enabling and asserting hp_mrl x # or by programming the mrl sensor present and power controller control bit values to 0 in the serial eeprom ), the slot starts power-up sequencing with hp_pwren x # and hp_pwrled x # assertion, following pex_ perst# input de-assertion: if the serial eeprom is not present, hp_pwren x # and hp_pwrled x # are asserted approximately 6.1 ms after pex_ perst# input is de-asserted if the serial eeprom is present, hp_pwren x # and hp_pwrled x # are asserted approximately 18.7 ms after pex_ perst# input is de-asserted
february, 2007 slot power-up sequence expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 161 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 the power-up sequence is as follows: 1. the hot plug controller drives hp_pwrled x # low, to turn on the power indicator, and drives hp_pwren x # low to turn on the external power controller. 2. after the programmable t pepv time delay following hp_pwren x # assertion, power to the slot is valid and the hot plug controller drives hp_clken x # low to turn on the reference clock (pex_refclkn/p) to the slot. the t pepv time delay is specified by setting the power management hot plug user configuration register hpc tpepv delay field (offset 1e0h [4:3]) to a non-zero value. by default, this field is cleared to 00b, indicating a 16-ms time delay from the time hp_pwren x # goes low to power beco ming valid at the slot. 3. after the programmable t pvperl time delay following hp_clken x # assertion, the hot plug controller de-asserts hp_perst x # to release slot reset. the t pvperl time delay is specified in the power management hot plug user configuration register hpc tpvperl delay bit (offset 1e0h [6]). by default, this bit is set to 1, indicating a 100-ms delay. with this default delay, if the serial eeprom is not present, hp_perst x # output is de-asserted approximately 122 ms after pex_ perst# input is de-asserted. ho wever, if the serial eeprom is present, hp_perst x # output is de-asserted approximate ly 135 ms after pex_perst# input is de-asserted. because the pci express base r1.0a allows the host to start conf iguration accesses 100 ms after the root complex de-asserts its perst# output, it is recommended that a programmed serial eeprom be used to clear the hpc tpvperl delay bit to 0, to reduce the t pvperl time delay to 20 ms, so that hp_perst x # is de-asserted approximately 55 ms after pex_perst# input is de-asserted.
hot plug support plx technology, inc. 162 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 figure 9-1 illustrates the timing sequence with the power controller present bit (offset 7ch [1]) set to 1. this timing sequence occurs at system power-up, or when a slot is being powered up by the user. if hp_mrl x # is enabled but not asserted to power-up the slot immediately after reset, hp_mrl x # can be asserted at runtime to start the slot power-up sequence, provided the power controller present and mrl sensor present bits are set (offset 7ch[2:1]=11b, either by default values when the serial eeprom is not present or blank, or by programmi ng the serial eeprom to set these bits), and the power controller control bit is cleared (offset 80h [10]=0, either by the programmed serial eeprom or by software). power-up sequencing at runt ime is controlled by software clearing the power controller control bit after hp_mrl x # assertion causes an in terrupt, if enabled [the slot control register hot plug interrupt enable and mrl sensor changed enable bits must be set (offset 80h [5, 2]=11b)]. hp_mrl x # assertion and de-assertion at runtime is not latched until the 10-ms de-bounce ensures that the state change is stable. slots with the mrl sensor not present can use the attention button pressed interrupt to generate an event and start the slot power-up sequence at runtime. (refer to figure 9-1 .) figure 9-1. slot power-up timing when power controller present bit is set note: hp_pwrledx# is not asserted if the serial eeprom clears the power indicator present bit (offset 7ch[4]) to 0. t pepv = 16 ms hp_pwrled x # power valid at slot t pvperl = 100 ms hp_pwren x # hp_perst x # hp_clken x #
february, 2007 slot power-up sequence expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 163 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 9.4.1.3 hp_perst x # (reset) and hp_pwrled x # output power-up sequencing when power controller present bit is clear the hp_perst x # and hp_pwrled x # outputs can be used without enabling the hot plug power controller (hp_pwren x # and hp_clken x # outputs and hp_pwrflt x # input). for example , hp_perst x # can be used to reset an on-board downstream device. if the power controller present (offset 7ch [1]) and power controller control (offset 80h [10]) bits are cleared to 0 by the serial eeprom, hp_perst x # is de-asserted (high) and hp_pwrled x # is asserted (low), after the root complex perst# input is de-asserted, as illustrated in figure 9-2 . however, hp_pwrled x # is not asserted if the serial eeprom also cleared the power indicator present bit (offset 7ch[4]) to 0. if the serial eeprom is initially blank, causing register default values to be loaded, hp_perst x # is not de-asserted and hp_pwrled x # is not asserted unless hp_mrl x # is low. therefore, if the hp_perst x # and/or hp_pwrled x # outputs are used [and a manual ly operated retention latch (mrl) is not used], pull hp_mrl x # low, to allow the outputs to toggle, regardless of whether the serial eeprom is blank. hp_perst x # can also be toggled at runtime by toggling the power controller control bit, provided that either the power controller present bit is cleared, or that hp_perst x # is initially de-asserted during slot power-up sequencing, as described in section 9.4.1.2 . a value of 1 asserts hp_perst x # (low). a value of 0 de-asserts hp_perst x # (high). figure 9-2. hot plug outputs when power controller present and power controller control bits are cleared note: hp_pwrledx# is not asserted if the serial ee prom clears the power indicator present bit (offset 7ch[4]) to 0. hp_perst x # after serial eeprom load hp_pwrled x # hp_pwren x # hp_clken x #
hot plug support plx technology, inc. 164 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 9.4.1.4 disabling power-up hot plug output sequencing if the power controller control bit is set to 1, after reset, the hp_pwren x #, hp_pwrled x #, and hp_clken x # outputs remain high, and the hp_perst x # output remains low. the hp_pwren x #, hp_pwrled x #, and hp_clken x # outputs also remain high if hp_mrl x # is not asserted in the default hot plug power-up sequencing described in section 9.4.1.2 . (refer to figure 9-3 .) figure 9-3. hot plug outputs when power controller control bit is set hp_perst x # hp_pwrled x # hp_pwren x # hp_clken x #
february, 2007 slot power-down sequence expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 165 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 9.4.2 slot power-down sequence software can power-down slots by setting the power controller control bit (offset 80h [10]=1). if the mrl sensor present bit is set (offset 7ch [2]=1), the hot plug controller can power down the slot if the mrl is open. figure 9-4 illustrates the following power-down timing sequence for either event: 1. hp_perst x # to the port is asserted. 2. hp_clken x # is de-asserted to the sl ot 100 s after hp_perst x # is asserted. 3. hp_pwren x # is de-asserted to the slot 100 s after hp_clken x # is de-asserted. figure 9-4. hot plug automatic power-down sequence 100 s 100 s hp_perst x # hp_pwren x # hp_clken x #
hot plug support plx technology, inc. 166 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 9.5 hot plug board insertion and removal process table 9-4 defines the board insertion procedure supported by the pex 8524. table 9-5 defines the board removal procedure. table 9-4. hot plug board insertion process operator / action hot plug controller software a. places board in slot. 1. sets presence detect state bit to 1. 2. sets presence detect changed bit to 1. 3. generates interrupt message due to presence detect change, if enabled. clears presence detect changed bit to 0. 4. transmits interrupt de -assertion message, if enabled. b. locks mrl. 5. clears mrl sensor state bit to 0. 6. sets mrl sensor changed bit to 1. 7. generates interrupt messa ge due to mrl sensor state change, if enabled. clears mrl sensor changed bit to 0. 8. transmits interrupt de -assertion message, if enabled. c. presses attention button. 9. sets attention button pressed bit to 1. 10. generates interrupt messa ge due to attention button pressed event, if enabled. clears attention button pressed bit to 0. 11. transmits interrupt de -assertion message, if enabled. writes to the slot control register power indicator control field, to blink the power indicator led, which indicates that the board is being powered up. continued ?
february, 2007 hot plug board insertion and removal process expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 167 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 d. power indicator blinks. 12. sets power indicator control field to 10b. 13. power indicator blink message is transmitted to the downstream device. 14. sets command completed bit to 1. 15. generates interrupt message due to power indicator turn on command completion, if enabled. clears command completed bit to 0. 16. transmits interrupt de -assertion message, if enabled. clears slot control register power controller control bit to 0, to turn on power to the port. 17. slot is powered up. 18. after a t pepv delay, sets command completed bit to 1. 19. generates interrupt message due to power turn on command completion, if enabled. clears command completed bit to 0. 20. transmits interrupt de -assertion message, if enabled. writes to the slot control register power indicator control field, to turn on the power indicator led, which indicates that the slot is fully powered on. 21. sets power indicator control field to 01b. 22. transmits interrupt assertion message due to power indicator turn on command completion, if enabled. clears command completed bit to 0. e. power indicator on. 23. transmits interrupt de -assertion message, if enabled. table 9-4. hot plug board insertion process (cont.) operator / action hot plug controller software
hot plug support plx technology, inc. 168 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 table 9-5. hot plug board removal process operator / action hot plug controller software a. presses attention button. 1. sets attention button pressed bit to 1. 2. generates interrupt messa ge due to attention button pressed, if enabled. clears attention button pressed bit to 0. 3. transmits interrupt de -assertion message, if enabled. writes to the slot control register power indicator control field, to blink the power indicator led, which indicates that the board is being powered down. b. power indicator blinks. 4. sets power indicator control field to 10b. 5. power indicator blink message is transmitted to the downstream device. 6. sets command completed bit to 1. 7. generates interrupt message due to power indicator command completion, if enabled. clears command completed bit to 0. 8. transmits interrupt de -assertion message, if enabled. sets slot control register power controller control bit to 1, to turn off power to the port. c. power indicator off. 9. slot is powered off. 10. after a t pepv delay, sets the command completed bit to 1. 11. generates interrupt message due to power turn off command completion, if enabled. clears command completed bit to 0. clears power indicator control field to 00b, to turn off the power indicator led, which indicates that the slot is fully powered off and the board can be removed. d. power indicator off, board ready to be removed. 12. clears power indicator control field to 00b. 13. sets command completed bit to 1, due to power indicator off command completion. clears command completed bit to 0. 14. transmits interrupt de -assertion message, if enabled. e. unlocks mrl. 15. sets mrl sensor state bit to 1. 16. sets mrl sensor changed bit to 1. 17. generates interrupt messa ge due to mrl sensor state change, if enabled. clears mrl sensor changed bit to 0. 18. transmits interrupt de -assertion message, if enabled. f. removes board from slot. 19. clears presence detect state bit to 0. 20. sets presence detect changed bit to 1. 21. generates interrupt message due to presence detect change, if enabled. clears presence detect changed bit to 0. 22. transmits interrupt de -assertion message, if enabled.
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 169 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 10 power management 10.1 power management capability the pex 8524 power management (pm) module inte rfaces with chip sections to reduce power consumption. the pex 8524 supports: link power management states (l-states) ? pci bus power management ? l0, l1, l2/l3 ready, and l3 (auxiliary power is not supported ) ? active state power management ? l0s and l1 device power management state (d-states) ? d0 (d0_uninitialized and d0_active) and d3 (d3hot and d3cold) support power management event (pme) support from d3hot power management event due to hot plug events downstream ports generate and forward pme_turn_off broadcast messages implements pci power mgmt. r1.1 note: because the pex 8524 does not support aux-power, pme generation from d3cold is not supported . the pm module interfaces with the physical layer el ectrical sub-block to tran sition the link state into low-power states when the module receives a power state change request from an upstream component, or an internal event forces the link state entry into low-power states in hardware-autonomous pm (active link state pm) mode. pci express link states are not directly visible to conventional pci bus driver software; instead, they are derived from the power management state of the components residing on those links. a functional block diagram of the pex 8524?s power management controller is illustrated in figure 10-1 .
power management plx technology, inc. 170 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 figure 10-1. power management controller functional block diagram note: the hot plug controller is available only on downstream ports. hot plug controller physical layer interface data link layer interface pme handler link state management power management csr device states message control port arbiter pm event device state link state control dllp receive dllp transmit suspend timers tlp egress tlp availability/credits power management controller pm_message_req arb_message_ack csr, interrupt, and message control csr write path csr read path message write message response
february, 2007 device power states expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 171 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 10.1.1 device power states the pex 8524 supports the pci express pci-pm d0, d3hot, and d3cold (no vaux) device power management states. the d1 and d2 states, which are optional in the pci express base r1.0a , are not supported by the pex 8524. the d3hot state can be entere d from the d0 stat e, when system software programs the power management status and control register power state field (offset 44h [1:0]=11b) for the appropriate port. the d0_uninitialized state ca n be entered from the d3hot stat e when the upstream and downstream links are in the l0s state an d system software clears the power management status and control register power state field (offset 44h[1:0]=00b). 10.1.1.1 d0 state d0 is divided into two distinct substates ? uninitialized and active . when power is initially applied to a pci express component, it defaults to the d0_uni nitialized state. the co mponent remains in the d0_uninitialized state until th e serial eeprom load completes. a device enters the d0_active state when: any single memory access enable occurs system software sets any combination of the command register bus master enable , memory access enable , and/or i/o access enable bits (offset 04h [2, 1, and/or 0], respectively) 10.1.1.2 d3hot state a device in the d3hot state must be able to res pond to configuration accesse s, allowing transition by software to the d0_uninitialized state. once in the d3hot state, the device can later be transitioned into the d3cold state by removing power from the device. in the d3hot state, hot plug operations cause a pme in the pex 8524. 10.1.1.3 d3cold state the pex 8524 transitions to the d3 cold state when power is removed. re-applying power causes the pex 8524 to transition from the d3cold state into the d0_uninitialized state, followed by a configuration and link training sequence. the d3cold state assumes that all previous context is lost; therefore, software must save the required cont ext while the pex 8524 remains in the d3hot state. the pex 8524 does not support aux-power; therefore, pme generation from d3cold is not supported .
power management plx technology, inc. 172 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 10.1.2 link power management state the power management state of a link is determin ed by the d-state of its downstream link. the pex 8524 holds its upstream and downstream links in the l0 state when it is in standard operating mode (pci pm state in d0_active). active-state link power management defines a protocol for components in the d0 state, to reduce link po wer by placing their links into a low-power state and instructs the opposite end of the link to do likewise. this capability allows hardware-autonomous, dynamic-link power reduction beyond what is achievable by software-only power management. table 10-1 defines the relationship between a pex 8524 power state and its downstream link. table 10-1. power states of connected link components downstream component d state pex 8524 dstate permissible interconnect state power saving actions d0 d0 l0 full power. l0s, l1 (optional) phy transmit lanes in high-impedance state. d1 d0 l1 phy transmit lanes in high-impedance state. d2 d0 l1 d3hot d0 or d3hot a a. the pex 8524 initiates a link-state transition of its upstream port to l1 when the port is programmed to d3hot. l1, l2/l3 ready phy transmit lanes in high-impedance state. fc and dll ack/nak timers suspended. pll can be disabled. d3cold (no aux power) d0, d3hot, or d3cold l3 link-off state. no power to component.
february, 2007 pex 8524 pci express power management support expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 173 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 10.1.3 pex 8524 pci express power management support the pex 8524 supports pci express features that are required or important for pci express switch power management. table 10-2 lists supported and non-supported feat ures and the register bits/fields used for configuration or activation. table 10-2. supported pci express power management capabilities register description supported offset bit(s) yes no 40h power management capability 7:0 capability id set to 01h, indicating that the data structure currently being pointed to is the pci power management data structure. ? 15:8 next capability pointer default 48h points to the message signaled interrupt capability register. ? 18:16 ver s i o n default 010b indicates compliance with the pci power mgmt. r1.1. ? 19 pme clock cleared to 0, as required by the pci express base r1.0a . ? 21 device-specific initialization default 0 indicates that devi ce-specific initialization is not required. ? 24:22 aux current default 000b indicates that the pex 8524 does not support auxiliary current requirements. ? 25 d1 support default 0 indicates that the pex 8524 does not support the d1 power state. ? 26 d2 support default 0 indicates that the pex 8524 does not support the d2 power state. ? 31:27 pme support default 11001b indicates that the corresponding pex 8524 port forwards pme messages in the d0, d3hot , and d3cold power states. ?
power management plx technology, inc. 174 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 44h power management status and control 1:0 power state this field is used to determine the current power state of the port, and to set the port into a new power state. 00b = d0 01b = d1 ? not supported 10b = d2 ? not supported 11b = d3hot if software attempts to wr ite an unsupported state to th is field, the write operation completes normally; however, the data is discarded and no state change occurs. ? 8 pme enable 0 = disables pme ge neration by the corresponding pex 8524 port a 1 = enables pme generation by the corresponding pex 8524 port ? 12:9 data select rw by serial eeprom mode only b . bits [12:9] select the data and data scale registers. 0h = d0 power consumed 3h = d3hot power consumed 4h = d0 power dissipated 7h = d3hot power dissipated ? ro for hardware auto-configuration. ? 14:13 data scale rw by serial eeprom mode only b . there are four internal data scale registers per port. bits [12:9], data select , select the data scale register. ? 15 pme status 0 = pme is not generated by the corresponding pex 8524 port a 1 = pme is being generated by the corresponding pex 8524 port ? power management control/status bridge extensions 22 b2/b3 support cleared to 0, as required by the pci power mgmt. r1.1. ? 23 bus power/clock control enable cleared to 0, as required by the pci power mgmt. r1.1 . ? power management data 31:24 data rw by serial eeprom mode only b . there are four internal data registers per port. bits [12:9], data select , select the data register. ? data scale and data registers (for all data selects). table 10-2. supported pci express power management capabilities (cont.) register description supported offset bit(s) yes no
february, 2007 pex 8524 pci express power management support expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 175 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 6ch device capabilities 8:6 endpoint l0s acceptable latency because the pex 8524 is a switch and not an endpoint, it does not support this feature. 000b = disables the capability ? 11:9 endpoint l1 acceptable latency because the pex 8524 is a switch and not an endpoint, it does not support this feature. 000b = disables the capability ? 12 attention button present (upstream port) for the pex 8524 upstream port, value of 1 indicates that an attention button is implemented on that adapter board. the pex 8524 serial eeprom register initiali zation capability is us ed to change this value to 0, indicating that an attention button is not present on an adapter board for which the pex 8524 provides the system interface. do not change for downstream ports. ? 13 attention indicator present (upstream port) for the pex 8524 upstream port, value of 1 indicates that an attention indicator is implemented on the adapter board. the pex 8524 serial eeprom register initiali zation capability is us ed to change this value to 0, indicating that an attention indicator is not present on an adapter board for which the pex 8524 provides the system interface. do not change for downstream ports. ? 14 power indicator present (upstream port) for the pex 8524 upstream port, value of 1 indicates that a power indicator is implemented on the adapter board. the pex 8524 serial eeprom register initiali zation capability is us ed to change this value to 0, indicating that a power indicator is not present on an adapter board for which the pex 8524 provides the system interface. do not change for downstream ports. ? 25:18 captured slot power limit value (upstream port) for the pex 8524 upstream port, the upper l imit on power supplied by the slot is determined by multiplying the value in this field by the value in the captured slot power limit scale field. do not change for downstream ports ? 27:26 captured slot power limit scale (upstream port) for the pex 8524 upstream port, the upper l imit on power supplied by the slot is determined by multiplying the value in this field by the value in the captured slot power limit value field. 00b = 1.0 01b = 0.1 10b = 0.01 11b = 0.001 do not change for downstream ports. ? table 10-2. supported pci express power management capabilities (cont.) register description supported offset bit(s) yes no
power management plx technology, inc. 176 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 70h device status and control 10 auxiliary (aux) power pm enable cleared to 0 for each port. ? 20 auxiliary (aux) power detected cleared to 0 for each port. ? 74h link capabilities 11:10 active state power management (aspm) support indicates the level of aspm supported by the port. 01b = l0s link power state entry is supported 10b = l0s and l1 link power states are supported all other values are reserved . ? 14:12 l0s exit latency 101b = corresponding pex 8524 port l0s ex it latency is between 1 and 2 s ? 17:15 l1 exit latency 101b = corresponding pex 8524 port l1 ex it latency is between 16 and 32 s ? 78h link status and control 1:0 active state power management (aspm) control 00b = disables l0s and l1 entries for the corresponding pex 8524 port c 01b = enables only l0s entry 10b = enables only l1 entry 11b = enables both l0s and l1 entries ? 7ch slot capabilities (for downstream ports) 0 attention button present 0 = attention button is not implemented 1 = attention button is implemented on the slot chassis of the corresponding pex 8524 downstream port do not change for upstream port. ? 1 power controller present 0 = power controller is not implemented 1 = power controller is implemented for the slot of the corresponding pex 8524 downstream port do not change for upstream port. ? 2 mrl sensor present 0 = mrl sensor is not implemented 1 = mrl sensor is implemented on the sl ot chassis of the corresponding pex 8524 downstream port do not change for upstream port. ? 3 attention indicator present 0 = attention indicato r is not implemented 1 = attention indicator is implemented on the slot chassis of the corresponding pex 8524 downstream port do not change for upstream port. ? table 10-2. supported pci express power management capabilities (cont.) register description supported offset bit(s) yes no
february, 2007 pex 8524 pci express power management support expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 177 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 7ch slot capabilities (for downstream ports) (cont.) 4 power indicator present 0 = power indicator is not implemented 1 = power indicator is implemented on the slot chassis of the corresponding pex 8524 downstream port do not change for upstream port. ? 5 hot plug surprise 0 = no device in the corresponding pex 8524 downstream port slot is removed from the system without prior notification 1 = device in the corresponding pex 8524 do wnstream port slot can be removed from the system without prior notification do not change for upstream port. ? 6 hot plug capable 0 = corresponding pex 8524 downstream port slot is not capable of supporting hot plug operations 1 = corresponding pex 8524 downstream por t slot is capable of supporting hot plug operations do not change for upstream port. ? 14:7 slot power limit value the maximum power available from th e corresponding pex 8524 downstream port is determined by multiplying the value in this field (expressed in decimal; 25d = 19h) by the value specified by the slot power limit scale field. do not change for upstream port. ? 16:15 slot power limit scale the maximum power available from th e corresponding pex 8524 downstream port is determined by multiplying the value in this field by the slot power limit value field. 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x do not change for upstream port. ? table 10-2. supported pci express power management capabilities (cont.) register description supported offset bit(s) yes no
power management plx technology, inc. 178 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 80h slot status and control (for downstream ports) 1 power fault detector enable 0 = function is disabled 1 = enables software notification with a hot plug interrupt if the port is in the d0 power state ( power management status and control register power state field, offset 44h [ 1:0 ]=00b), or with a pme message if the port is in the d3hot state (offset 44h[1:0]=11b), for a power fault event on the corresponding pex 8524 downstream port. do not change for upstream port. ? 9:8 power indicator control controls the power indicator on the co rresponding pex 8524 down stream port slot. 00b = reserved ? writes are ignored 01b = turns on indicator to constant on state 10b = causes indicator to blink 11b = turns off indicator software must use a byte or word write (and not a dword write) to control the hp_pwrled x # output signal. reads return the corresponding pex 8524 downstream port power indicator?s current state. do not change for upstream port. ? 10 power controller control controls the power controller on the corresponding pex 8524 downstream port slot. 0 = turns on power controller; re quires some delay to be effective 1 = turns off power controller software must use a byte or word write (and not a dword write) to control the power controller output signals. note: value of 0 requires some delay to be effective. ? 17 power fault detected set to 1 when the power controller of the corresponding pex 8524 downstream port slot detects a power fault at the slot. do not change for upstream port. ? 138h power budgeting extended capability 15:0 extended capability id set to 0004h, as required by the pci express base r1.0a . ? 19:16 capability version set to 1h, as required by the pci express base r1.0a . ? 31:20 next capability offset set to 148h , which addresses the pex 8524 virtual channel extended capability registers. ? 13ch data select 7:0 data select indexes the power budgeting data reported by way of eight power budgeting data registers per port and selects the dword of power budgeting data that appears in each power budgeting data register. index values start at 0, to select the first dword of power budgeting data; subseque nt dwords of power budg eting data ar e selected by increasing index values 1 to 7. ? table 10-2. supported pci express power management capabilities (cont.) register description supported offset bit(s) yes no
february, 2007 pex 8524 pci express power management support expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 179 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 140h power budgeting data 7:0 base power eight registers/port. specifies (in watts) the base power value in the operating condition. this value must be multiplied by the data scale to produce the actual power consumption value. ? 9:8 data scale specifies the scale to apply to the base po wer value. the device power consumption of the device is determined by multiplying the base power field contents with the value corresponding to the encoding returned by this field. 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x ? 12:10 pm sub-state 000b = corresponding pex 8524 port is in th e default power mana gement sub-state ? 14:13 pm state current power state. 00b = d0 state 01b = not used ? d1 state not supported 10b = not used ? d2 state not supported 11b = d3 state ? 17:15 type type of operating condition. 000b = pme auxiliary 001b = auxiliary 010b = idle 011b = sustained 111b = maximum all other values are reserved . ? 20:18 power rail power rail of operating condition. 000b = power is 12v 001b = power is 3.3v 010b = power is 1.8v 111b = thermal all other values are reserved . ? there are eight registers per port that can be programmed, through the serial eeprom. each non-zero register value describes the power usage for a different operating c ondition. each configuration is selected by writing to the data select register data select field (offset 13ch [ 7:0 ]). table 10-2. supported pci express power management capabilities (cont.) register description supported offset bit(s) yes no
power management plx technology, inc. 180 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 144h power budget capability 0 system allocated 1 = power budget for the device is in cluded within the sy stem power budget ? 1e0h power management hot plug user configuration 0 l0s entry idle count time to meet to enter l0s. 0 = idle condition lasts for 1 s 1 = idle condition lasts for 4 s ? 1 l1 upstream port receiver idle count for active l1 entry. 0 = upstream port receiver idle for 2 s 1 = upstream port receiver idle for 3 s ? 2 hpc pme turn-off enable 1 = pme turn-off message is transmitted before the port is turned off on a downstream port ? 4:3 hpc t pepv delay slot power-applied to power-valid delay time. 00b = 16 ms 01b = 32 ms 10b = 64 ms 11b = 128 ms ? 5 hpc inband presence-detect enable 0 = hp_prsnt[1:0]# or hp_prsnt[11:8]# input balls are used to detect a board present in the slot 1 = serdes receiver detect mechanism is used to detect a board present in the slot ? 6 hpc t pvperl delay downstream port power-valid to reset signal release time. 0 = 20 ms 1 = 100 ms (default) ? table 10-2. supported pci express power management capabilities (cont.) register description supported offset bit(s) yes no
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 181 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 11 pex 8524 transparent mode port registers 11.1 introduction this chapter defines the pex 8524 transparent mode port registers. the pex 8524 ports have their own configuration, capability, control, and status register space. the re gister mapping is the same for each port. (refer to table 11-1 .) this chapter also presents the pex 8524 programmable registers and the order in which they appear in the register map. re gister descriptions, when applicable, include details regarding their use and meaning in the upst ream and downstream ports. (refer to figure 11-1 .) nt port registers are defined in chapter 15, ?nt port virtual interface registers,? and chapter 16, ?nt port link interface registers.? for further details regarding register names and descriptions, refer to the following specifications: pci r2.3 pci power mgmt. r1.1 pci-to-pci bridge r1.1 pci express base r1.0a note: for the pex 8524 to properly route memory and i/o requests and completions, each station contains content addressable memory (cam) registers that hold mirror copies of certain registers in each port. refer to the pex 85xx eeprom ? pex 8532/8524/8516 design note , section 6.12, ?shadowed registers.? if the registers that are shadowed are programmed by the serial eeprom to non-default values, the corresponding cam registers must be programmed by serial eeprom to contain the same values as the shadowed registers.
pex 8524 transparent mode port registers plx technology, inc. 182 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.2 type 1 pex 8524 port register map table 11-1. type 1 pex 8524 port register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00h ? configuration header regi sters capability pointer ( 40h ) 34h ? 3ch next capability pointer ( 48h ) capability id ( 01h ) 40h power management capability registers 44h next capability pointer ( 68h ) capability id ( 05h ) 48h message signaled interr upt capabilit y registers ? 64h next capability pointer ( 00h ) capability id ( 10h ) 68h pci express capability registers ? 80h reserved 84h ? fch next capability offset ( fb4h ) 1h extended capability id ( 0003h ) 100h device serial number exte nded capability registers 104h 108h reserved 10ch ? 134h next capability offset ( 148h ) 1h extended capability id ( 0004h ) 138h power budgeting extended capability registers ? 144h next capability offset ( 000h ) 1h extended capability id ( 0002h ) 148h virtual channel extende d capability registers ? 1c4h plx-specific registers 1c8h ? c08h reserved c3ch ? fb0h next capability offset ( 138h ) 1h pci express extended capability id ( 0001h )fb4h advanced error reporti ng capability registers ? ffch
february, 2007 pex 8524 port register configuration and map expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 183 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.3 pex 8524 port register configuration and map the pex 8524 port registers are configured similarly ? not all the same. port 0 of station 0 and port 8 of station 1 include more device-specific registers than the other station po rts. the registers for these ports contain setup and control information specific to the station. also, port 0 of station 0 contains registers used to set up and control the switch, and serial eeprom interf ace logic and control. the port register map is defined in table 11-2 . (refer to appendix a, ?serial eeprom memory map,? for a detailed description of this register map.) table 11-2. pex 8524 port register configuration and map register types station 0, port 0 station 1, port 8 station 0, port 1 station 1, ports 9, 10, 11 configuration header registers 00h - 3ch 00h - 3ch 00h - 3ch power management capability registers 40h - 44h 40h - 44h 40h - 44h message signaled interrupt capability registers 48h - 64h 48h - 64h 48h - 64h pci express capability registers 68h - 8ch 68h - 8ch 68h - 8ch device serial number ex tended capabilit y registers 100h - 108h 100h - 108h 100h - 108h power budgeting extended capability registers 138h - 144h 138h - 144h 138h - 144h virtual channel extended capability registers 148h - 1c4h 148h - 1c4h 148h - 1c4h ecc check disable 1c8h 1c8h device-specific error 1cch - 1d0h 1cch - 1d0h debug 1d4h - 1dch 1d4h - 1d8h power management, hot plug, and miscellaneous control 1e0h - 1fch 1e0h - 1ech, 1f8h - 1fch 1e0h - 1ech, 1f8h - 1fch physical layer (all exce pt for serial eeprom-related) 200h - 25ch 200h - 25ch serial eeprom 260h - 264h bus number cam station 0, st ation 1 2c8h - 2f4h 2c8h - 2f4h i/o cam station 0, station 1 308h - 31ch 308h - 31ch amcam memory base a nd limit 348h - 404h 348h - 404h ingress control registers 660h - 73ch 660h - 73ch i/o cam upper station 0, station 1 680h - 6ach 680h - 6ach station 0 bar, st ation 1 bar 6c0h - 71ch 6c0h - 71ch virtual channel station 0, station 1 740h - 79ch 840h - 9ech 740h - 79ch 840h - 9ech 740h ingress credit handler (inch) registers 9f0h - b7ch 9f4h- b7ch a00h - b7ch ingress one-bit ecc error count register be8h be8h relaxed completion orderi ng (ingress) register ? silicon revisions bb/bc only bech bech relaxed ordering mode (ingress) register bf0h - bfch bf0h - bfch internal credit handler (itch ) vc&t threshold registers c00h - c08h c00h - c08h advanced error reporting capability registers fb4h - ffch fb4h - ffch fb4h - ffch
pex 8524 transparent mode port registers plx technology, inc. 184 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.4 register access each pex 8524 port implements a 4-kb configuration space. the lower 256 bytes (offsets 00h through ffh) is the pci-compatible configuration space, and the upper 960 dwords (offsets 100h through fffh) is the pci express extended configuration sp ace. the pex 8524 supports three mechanisms for accessing registers: pci r2.3-compatible configuration mechanism pci express enhanced configuration mechanism plx-specific memory-mapped configuration mechanism 11.4.1 pci r2.3 -compatible configuration mechanism the pci r2.3 -compatible configuration m echanism provides standard access to the pex 8524 ports? first 256 bytes (the bytes at offsets 00h through ffh) of the pci express configuration space. this mechanism is used to access the pex 8524 port type 1 (pci-to-pci bridge) registers: configuration header registers power management capability registers message signaled interrupt capability registers pci express capability registers the pci r2.3 -compatible configuration mechanism uses pci type 0 and type 1 configuration transactions to access the pex 85 24 configuration registers. the pex 8524 upstream port captures the bus and device numbers assigned by the upstream device on the pci express link attached to the pex 8524 upstream port, as required by the pci express base r1.0a . the pex 8524 decodes all type 1 configuration accesse s received on its upstream port, when any of the following conditions exist: if the bus number specified in the configuration access is the nu mber of the pex 8524 internal virtual pci bus, the pex 8524 au tomatically converts the type 1 configuration access into the appropriate type 0 configuratio n access for the specified device. ? if the specified device corresponds to the pc i-to-pci bridge in one of the pex 8524 downstream ports, the pex 8524 processes the read or write request to the specified downstream port register specified in the original type 1 configuration access. ? if the specified device number does not correspond to any of the pex 8524 downstream port device numbers, the pex 8524 responds with an unsupported request (ur). if the specified bus number in the type 1 configurat ion access is not the number of the pex 8524 internal virtual pci bus, but is the number of one of the pex 8524 downstream port secondary/subordinate buse s, the pex 8524 passes the configuration access onto the pci express link attached to that pex 8524 downstream port. if the specified bus number is the downstream port s econdary bus number, and the specified device number is 0, the pex 852 4 converts the type 1 configuration access to a type 0 configuration access before passing it on. if the specified device number is not 0, the downstream port drops the tlp and generates a ur. if the specified bus number is not the downstream port secondary bus number, the pex 8524 passes along the type 1 configuration access, without change.
february, 2007 pci express enhanced configuration mechanism expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 185 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 because the pci r2.3 -compatible configuration mechanism is limited to the first 256 bytes of the pci express configuration space of the pex 8524 ports, the pci e xpress enhanced configuration mechanism (described in section 11.4.2 ) or plx-specific memory-map ped configuration mechanism (described in section 11.4.3 ) must be used to access beyond byte ffh. the pci express enhanced configuration mechanism can access the registers in the pci-compatible region, as well as those in the pci express extended conf iguration space that are defined by pci express specifications; however, it generally cannot access the pex 8524 device-specifi c registers above 100h. the plx-specific memory-mapped configuration mechan ism can access all pex 8524 registers. 11.4.2 pci express enhanced configuration mechanism the pci express enhanced configuration mechanis m is implemented on all pci express pcs and on systems that do not implement a processor-specifi c firmware interface to the configuration space, providing a memory-mapped address space in the root complex through wh ich the root complex translates a memory access into one or more conf iguration requests. device drivers normally use an application programming interface (a pi) provided by the operating system, to use the pci express enhanced configuration mechanism. the pci express enhanced configuration mechanis m is used to access the pex 8524 port type 1 (pci-to-pci bridge) registers that are defined by pci express specifications: configuration header registers power management capability registers message signaled interrupt capability registers pci express capability registers device serial number extended capability registers power budgeting extended capability registers virtual channel extended capability registers advanced error reporting capability registers the pex 8524 device-specific registers that exist in the pci express extended configuration space (above 100h) generally cannot be accessed by th e pci express enhanced configuration mechanism. the plx-specific memory-mapped config uration mechanism (described in section 11.4.3 ) can access all pex 8524 registers.
pex 8524 transparent mode port registers plx technology, inc. 186 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.4.3 plx-specific memory-m apped configuration mechanism the plx-specific memory-mapped configura tion mechanism provides a method to access the configuration registers of each port in a single memory map, as illustrated in figure 11-1 . the registers of all ports are contained within a 4-kb range. the pex 8524 supports up to six simultaneously active ports. the pex 8524 requires a single contiguous memory space of 128 kb to contain all the pex 8524 configuration registers and sufficient memory sp ace to support software compatibility for future device expansion. to use the plx-specific memory-mapped configur ation mechanism, program the upstream port?s type 1 configuration space base address 0 and base address 1 registers ( bar0 and bar1 , offsets 10h and 14h , respectively) registers. after the pex 8524 upstream port memory-mapped register base address registers are configured, po rt 0 registers can be accessed with memory reads from and writes to the fi rst 4 kb (0h to fffh), po rt 1 registers can be accessed with memory reads from and writes to the second 4 kb (1000h to 1fffh), port 8 regi sters can be accessed with memory reads from and writes to the ni nth 4 kb (8000h to 8fffh), and so forth. within each of these 4-kb windows, individual registers are located at the dword offsets indicated in table 11-1 . the upstream port bar0 and bar1 registers are typically enumerat ed at boot time, by bios or the operating system (os) software. when the regi sters are written (by serial eeprom or software), the pex 8524 automatically copies the values into the bar0 and bar1 shadow registers that exist in ports 0 and 8, located at offsets 6c0h through 71ch . the particular registers used within this block depend upon which port is the upstream port. if the upstream port bar0 and bar1 registers are enumerated by serial eeprom, rather than by bios/os, the serial eeprom must be programmed to also load the same valu es to the corresponding bar0 and bar1 shadow registers in each station. note: the shadow registers provide for another option. after bar0 and bar1 are programmed, it is possible to overwrite the ?shadow ed? location (using the serial eeprom or software) to set up non-tree hierarchies, in which each station can have different memory windows. if doing this, it is recommended to match the upstream station shadow register with the bars.
february, 2007 plx-specific memory-mapped configuration mechanism expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 187 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 figure 11-1. pex 8524 register offset from upstream port bar0/1 base address (transparent mode) port 0 port 1 reserved port 8 port 9 port 10 port 11 reserved pex 8524 0 kb 4 kb 8 kb 32 kb 36 kb 40 kb 44 kb 48 kb 128 kb
pex 8524 transparent mode port registers plx technology, inc. 188 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.5 register descriptions the remainder of this chapter details the pex 8524 registers, including: bit/field names description of register functions for the pex 8524 upstream port and downstream ports type ( such as rw or hwinit; refer to table 11-3 for type descriptions) whether the power-on/reset value can be modified by way of the pex 8524 serial eeprom initialization feature default power-on/reset value table 11-3. register types, grouped by user accessibility type description hwinit hardware initialized refers to the pex 8524 hardware initialization me chanism or pex 8524 serial eeprom register initialization feature. read-only after initia lization and can only be reset with a fundamental reset. rw read-write read/write and is set or cleared to the needed state by software. rw1c read-only status, write 1 to clear write 1 to clear status register or bit. indicates st atus when read. a status bit set by the system to 1 (to indicate status ) is cleared by writing 1 to th at bit. writing 0 has no effect. rw1cs read-only status, write 1 to clear, sticky same as rw1c, except that bits are not modified by a hot reset. rw1s read-write, write 1 to set, sticky non-transparent ports contain these types of device-specific control registers. software writes 1 to the register to enable control and 1 to a register with rw1c privilege to clear the c ontrol. writing 0 has no effect. rws read-write, sticky same as rw, except that bits are not modified by a hot reset. ro read-only read-only and cannot be altered by software . initialized by th e pex 8524 hardware initialization mechanism or pex 8524 serial eeprom register initialization feature. ros read-only, sticky same as ro, except that bits are not initialized nor modified by a hot reset.
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 189 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.6 configuration header registers table 11-4. configuration header register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 device id vendor id 00h status command 04h class code revision id 08h bist (not supported) header type and multi-function primary latency timer cache line size 0ch base address 0 10h base address 1 14h secondary latency timer subordinate bus numb er secondary bus number primary bus number 18h secondary status i/ o limit i/o base 1ch memory limit address memory base address 20h prefetchable memory limit address prefetchable memory base address 24h prefetchable memory up per base address[63:32] 28h prefetchable memory u pper limit address[63:32] 2ch i/o limit upper 16 bits i/o base upper 16 bits 30h reserved capability pointer ( 40h ) 34h expansion rom base address (not supported) 38h bridge control interrupt pin interrupt line 3ch register 11-1. 00h product identification (all ports) bit(s) description type serial eeprom default 15:0 ven do r i d unless overwritten by the seri al eeprom, returns the plx pci-sig-assigned vendor id. th e pex 8524 serial eeprom register initialization capability is used to replace the plx vendor id with another vendor id. hwinit yes 10b5h 31:16 device id unless overwritten by the serial eeprom, 8532h is returned by the pex 8524v and 8524h is returned by the pex 8524, the plx-assigned device id. th e serial eeprom register initialization capability is used to replace the plx-assigned device id with another device id. hwinit yes 8532h (pex 8524v) 8524h (pex 8524)
pex 8524 transparent mode port registers plx technology, inc. 190 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-2. 04h command/status (all ports) bit(s) description type serial eeprom default command 0 i/o access enable 0 = pex 8524 ignores i/o accesses on the corresponding port?s primary interface 1 = pex 8524 responds to i/o accesses on the corresponding port?s primary interface rw yes 0 1 memory access enable 0 = pex 8524 ignores memory accesses on the corresponding port?s primary interface 1 = pex 8524 responds to memory accesses on the corresponding port?s primary interface rw yes 0 2 bus master enable controls the pex 8524 memory and i/o request forwarding in the upstream direction. neither affect message forwarding nor completions in the upstream or downstream direction. 0 = pex 8524 handles memory and i/o re quests received on the corresponding port downstream/secondary interfac e as unsupported requests (ur); for non-posted requests, the pex 8524 returns a completion with ur completion status 1 = pex 8524 forwards memory and i/o requests in the upstream direction rw yes 0 3 special cycle enable cleared to 0, as required by the pci express base r1.0a. ro no 0 4 memory write and invalidate cleared to 0, as required by the pci express base r1.0a. ro no 0 5 vga palette snoop cleared to 0, as required by the pci express base r1.0a. ro no 0 6 parity error response enable controls the master data parity error bit. rw yes 0 7 idsel stepping/wait cycle control cleared to 0, as required by the pci express base r1.0a. ro no 0 8 serr# enable controls the signaled system error bit. when = 1, enable s reporting of fatal and non-fatal errors detected by th e device to the root complex. rw yes 0 9 fast back-to-back transactions enabled cleared to 0, as required by the pci express base r1.0a. ro no 0 10 interrupt disable 0 = corresponding pex 8524 port is enabled to generate int x interrupt messages 1 = corresponding pex 8524 port is prevented from generating int x interrupt messages rw yes 0 15:11 reserved 00h
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 191 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 status 18:16 reserved 000b 19 interrupt status 0 = no int x interrupt message is pending 1 = int x interrupt message is pending in ternally to the corresponding pex 8524 port ro yes 0 20 capabilities list required by the pci express base r1.0a to be 1 at all times. ro yes 1 21 66 mhz capable cleared to 0, as required by the pci express base r1.0a. ro no 0 22 reserved 0 23 fast back-to-back transactions capable cleared to 0, as required by the pci express base r1.0a. ro no 0 24 master data parity error if the parity error response enable bit is set to 1, the corresponding pex 8524 port sets this bit to 1 when the port: forwards the poisoned tlp write re quest from the secondary to the primary interface, or receives a completion marked as poisoned on the primary interface if the parity error response enable bit is cleared to 0, the pex 8524 never sets this bit. this error is natively reported by the uncorrectable error status register poisoned tlp status bit (offset fb8h [12]), which is mapped to this bit for conventional pci backward compatibility. rw1c yes 0 26:25 devsel timing cleared to 00b, as required by the pci express base r1.0a. ro no 00b 27 signaled target abort when a memory-mapped access payload length is greater than one dword, the pex 8524 upstream port sets this bit to 1. this error is natively reported by the uncorrectable error status register completer abort status bit (offset fb8h[15]), which is mapped to this bit for conventional pci ba ckward compatibility. rw1c yes 0 register 11-2. 04h command/status (all ports) (cont.) bit(s) description type serial eeprom default
pex 8524 transparent mode port registers plx technology, inc. 192 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 28 received target abort cleared to 0. it is never set to 1. ro no 0 29 received master abort cleared to 0. it is never set to 1. ro no 0 30 signaled system error when the serr# enable bit is set to 1, the corresponding pex 8524 port sets this bit to 1 when it transmits an err_fatal or err_nonfatal message to its upstream device. this error is natively reported by the device status register fatal error detected and non-fatal error detected bits (offset 70h [18:17], respectively), which are mapped to this bit for conventional pci backward compatibility. rw1c yes 0 31 detected parity error set to 1 when the corresponding port re ceives a poisoned tlp on its primary side, regardless of the parity error response enable bit state. this error is natively reported by the upstream port?s uncorrectable error status register poisoned tlp status bit (offset fb8h [12]), which is mapped to this bit for conventional pci backward compatibility. rw1c yes 0 register 11-3. 08h class code and revision id (all ports) bit(s) description type serial eeprom default 7:0 revision id unless overwritten by the serial eepro m, returns the sili con revision (aah, bbh, or bch for pex 8524v; bbh or bch for pex 8524), the plx-assigned revision id for this version of th e pex 8524. the pex 8524 serial eeprom register initialization capability is used to replace the pl x revision id with another revision id. note: silicon revision bb only ? bit 0 is hardwired to 1 and is not programmable by serial eeprom. silicon revi sion bc only ? bits [2:0] are hardwired to 100b and are not programmable by serial eeprom. ro ye s (refer to note) aah, bbh, or bch (pex 8524v) or bbh or bch (pex 8524) class code 060400h 15:8 programming interface pex 8524 ports support the pci-to-pci bridge r1.1 requirements, but not subtractive decoding, on its upstream interface. ro yes 00h 23:16 sub-class code pci-to-pci bridge. ro yes 04h 31:24 base class code bridge device. ro yes 06h register 11-2. 04h command/status (all ports) (cont.) bit(s) description type serial eeprom default
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 193 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-4. 0ch miscellaneous control (all ports) bit(s) description type serial eeprom default 7:0 cache line size implemented as a read-write field for conventional pci-compatibility purposes and does not imp act pex 8524 functionality. rw yes 00h 15:8 primary latency timer cleared to 00h, as required by the pci express base r1.0a. ro no 00h 22:16 header type corresponding pex 8524 port configuration space header adheres to the type 1 pci-to-pci bridge conf iguration space layout defined by the pci-to-pci bridge r1.1 . ro yes 01h 23 multi-function always 0, because the pex 8524 is a single-function device. ro yes 0 31:24 bist not supported ro no 00h
pex 8524 transparent mode port registers plx technology, inc. 194 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-5. 10h base address 0 (upstream port only; reserved for downstream ports) bit(s) description ports type serial eeprom default 0 memory space indicator when enabled, the base address register maps the corresponding pex 8524 port configuration registers into memory space. note: hardwired to 0. upstream ro no 0 reserved for downstream ports. downstream 0 2:1 memory map type 00b = corresponding pex 8524 port configuration registers can be mapped anywhere in 32-bit memory address space 10b = corresponding pex 8524 port configuration registers can be mapped anywhere in 64-bit memory address space 01b, 11b = reserved upstream ro yes 00b reserved for downstream ports. downstream 00b 3 prefetchable the base address register maps the corresponding pex 8524 port configuration registers into non-prefetchable memory space by default. note: hardwired to 0. upstream ro no 0 reserved for downstream ports. downstream 0 16:4 reserved no 0-0h 31:17 base address base address for plx-sp ecific memory-mapped configuration mechanism. upstream rw yes 0000h reserved for downstream ports. downstream 0000h register 11-6. 14h base address 1 (upstream port only; reserved for downstream ports) bit(s) description ports type serial eeprom default 31:0 base address 1 for 64-bit addressing ( base address 0 register memory map type field is set to 10b), base address 1 extends base address 0 to provide the upper 32 address bits. upstream rw yes 0000_0000h read-only when the base address 0 register memory map type field indicates 32-bit memory addressing (offset 10h [2:1]=00b). ro no reserved for downstream ports. downstream 0000_0000h
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 195 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-7. 18h bus number (all ports) bit(s) description type serial eeprom default 7:0 primary bus number records the bus number of the pci bus segment to which the primary interface of this port is connected . set by configuration software. rw yes 00h 15:8 secondary bus number records the bus number of the pci bus segment that is the secondary interface of this port. set by configuration software. rw yes 00h 23:16 subordinate bus number records the bus number of the highest numbered pci bus segment that is subordinate to this port. se t by configuration software. rw yes 00h 31:24 secondary latency timer cleared to 00h, as required by the pci express base r1.0a. ro no 00h
pex 8524 transparent mode port registers plx technology, inc. 196 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-8. 1ch secondary status, i/o limit, and i/o base (all ports) bit(s) description type serial eeprom default i/o base 3:0 i/o base addressing capability 1h = 32-bit address decoding is supported other values are not allowed. ro yes 1h 7:4 i/o base address[15:12] the pex 8524 ports use their i/o base and i/o limit registers to determine the address range of i/o transactions to forward from the primary interface to the secondary interf ace or vice versa. i/o base address[15:12] bits specif y the corresponding pex 8524 port i/o base address[15:12]. the pex 8524 assume s i/o base address[11:0] = 000h. for 16-bit i/o addressing, the pex 8 524 assumes address[31:16] = 0000h. for 32-bit addressing, the pex 8524 decodes address[31:0], and uses the i/o base upper 16 bits and i/o limit upper 16 bits . rw yes fh i/o limit 11:8 i/o limit addressing capability 1h = 32-bit address decoding is supported other values are not allowed. ro yes 1h 15:12 i/o limit address[15:12] the pex 8524 ports use their i/o base and i/o limit registers to determine the address range of i/o transactions to forward from the primary interface to the secondary interface or vice versa. i/o limit address[15:12] specify the corresponding pex 8524 port i/o limit address[15:12]. the pex 8524 assumes addr ess bits [11:0] of the i/o limit address are fffh. for 16-bit i/o addressing, the pex 8 524 decodes address bits [31:16] and assumes address bits [31:16] of the i/o limit address are 0000h. for 32-bit addressing, the pex 8524 decodes address bits [31:0], and uses the i/o base upper 16 bits and i/o limit upper 16 bits . if the i/o limit address is less than the i/o base address, the pex 8524 does not forward i/o transactions from th e corresponding port primary/upstream bus to its secondary/downstream bus. ho wever, the pex 8524 forwards all i/o transactions from the secondary bus of the corresponding port to its primary bus. rw yes 0h
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 197 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 secondary status 20:16 reserved 0-0h 21 66 mhz capable not supported 0 = not enabled, as pci express does not support 66 mhz ro no 0 22 reserved 0 23 fast back-to-back transactions capable not supported 0 = not enabled, as pci express does not support this function ro no 0 24 master data parity error if the parity error response enable bit value is 1, the corresponding pex 8524 port sets this bit to 1 when it transmits or receives a tlp on its downstream side, and when either of the fo llowing two conditions occur: port receives comple tion marked poisoned port forwards poiso ned tlp write request if the parity error response enable bit = 0, the pex 8524 never sets this bit. rw1c yes 0 26:25 devsel timing cleared to 00b, as required by the pci express base r1.0a. ro no 00b 29:27 reserved 000b 30 received system error set to 1 when a port receives an err_fatal or err_nonfatal message on its secondary interface. rw1c yes 0 31 detected parity error set to 1 by the secondary side of a type 1 configuration space header device when the device receives a poi soned tlp, regardless of the parity error response enable bit state. rw1c yes 0 register 11-8. 1ch secondary status, i/o limit, and i/o base (all ports) (cont.) bit(s) description type serial eeprom default
pex 8524 transparent mode port registers plx technology, inc. 198 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: the pex 8524 port forwards memory transactions from its primary interface to its secondary interface (downstream) if a memory address is within the range defined by the memory base address and memory limit address registers (when the base is less than or equal to the limit). conversely, the pex 8524 port forwards memory transac tions from its secondary interface to its primary interface (upstream) if a memory address is outside this address range [provided the address is not within the range defined by the prefetchable memory base (offsets 28h + 24h [15:0]) and prefetchable memory limit (offsets 2ch + 24h [31:16])] registers. register 11-9. 20h memory base and limit address (all ports) bit(s) description type serial eeprom default memory base address 3:0 reserved 0h 15:4 memory base address[31:20] specifies the corresponding pex 8524 port memory base address[31:20]. the pex 8524 assumes memory base address[19:0]=00000h. rw yes fffh memory limit address 19:16 reserved 0h 31:20 memory limit address[31:20] specifies the corresponding pex 8524 por t non-prefetchable memory limit address[31:20]. the pex 8524 assumes memory limit address[19:0]=fffffh. rw yes 000h
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 199 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: the pex 8524 port forwards memory transactions from its primary interface to its secondary interface (downstream) if a memory address is within the range defined by the prefetchable memory base (offsets 28h + 24h[15:0]) and prefetchable memory limit (offsets 2ch + 24h[31:16]) registers (when the base is less than or equal to the limit). conversely, the pex 8524 port forwards memory transac tions from its secondary interface to its primary interface (upstream) if a memory address is outside this address range [provided the address is not within the range defined by the memory base address and memory limit address registers (offset 20h ). register 11-10. 24h prefetchable memory base and limit address (all ports) bit(s) description type serial eeprom default prefetchable memory base address 3:0 prefetchable memory base capability 1h = corresponding pex 8524 port defaults to 64-bit prefetchable memory addressing support note: if the application needs 32-bit only prefetchable space, the serial eeprom must not equal the va lue of this field and bits [19:16] ( prefetchable memory limit address register prefetchable memory limit capability field). ro yes 1h 15:4 prefetchable memory base address[31:20] specifies the corresponding pex 8524 port prefetchable memory base address[31:20]. the pex 8524 assumes prefetchable memory base address[19:0]=00000h. rw yes fffh prefetchable memory limit address 19:16 prefetchable memory limit capability 1h = corresponding pex 8524 port defaults to 64-bit prefetchable memory addressing support ro yes 1h 31:20 prefetchable memory limit address[31:20] specifies the corresponding pex 8524 port prefetchable memory base address[31:20]. the pex 8524 assumes prefetchable me mory base addr ess[19:0]=fffffh. rw yes 000h
pex 8524 transparent mode port registers plx technology, inc. 200 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-11. 28h prefetchable memory upper base address[63:32] (all ports) bit(s) description type serial eeprom default 31:0 prefetchable memory base address[63:32] silicon revision aa the pex 8524 uses this register for prefetchable memory upper base address[63:32]. rw yes ffff_ffffh silicon revisions bb/bc the pex 8524 uses this register for prefetchable memory upper base address[63:32]. rw yes 0000_0000h register 11-12. 2ch prefetchable memory upper limit address[63:32] (all ports) bit(s) description type serial eeprom default 31:0 prefetchable memory limit address[63:32] the pex 8524 uses this register fo r prefetchable memory upper limit address[63:32]. rw yes 0000_0000h register 11-13. 30h i/o base address[31:16] and i/o limit address[31:16] (all ports) bit(s) description type serial eeprom default 15:0 i/o base upper 16 bits the pex 8524 uses this register for i/o base address[31:16]. rw yes ffffh 31:16 i/o limit upper 16 bits the pex 8524 uses this register for i/o limit address[31:16]. rw yes 0000h register 11-14. 34h capabilities pointer (all ports) bit(s) description type serial eeprom default 7:0 capability pointer default 40h points to the power management capability register. ro yes 40h 31:8 reserved 0000_00h register 11-15. 38h expansion rom base address (all ports) bit(s) description type serial eeprom default 31:0 expansion rom base address not supported cleared to 0000_0000h. ro no 0000_0000h
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 201 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-16. 3ch bridge control and interrupt signal (all ports) bit(s) description type serial eeprom default 7:0 interrupt line the pex 8524 does not use this register, but provides it for operating system and device driver use. rw yes 00h 15:8 interrupt pin identifies the conventional pci interrupt message(s) that the device (or device function) uses. when values = 01h, 02h, 03h, a nd 04h, maps to conventional pci interrupt messages for inta#, intb#, intc#, and intd#, respectively. when 00h, indicates that the de vice does not use conventional pci interrupt message(s). only values 00h or 01h are allowed in the pex 8524. ro yes 01h
pex 8524 transparent mode port registers plx technology, inc. 202 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 bridge control 16 parity error response enable controls the response to poisoned tlps. 1 = enables the secondary master data parity error bit rw yes 0 17 serr# enable controls forwarding of err_cor, err_fatal, and err_nonfatal from the secondary interface to the primary interface. when set to 1, and the command register serr# enable bit value is 1, enables the signaled system error bit. rw yes 0 18 isa enable silicon revision aa not supported cleared to 0. no 0 silicon revisions bb/bc modifies the pex 8524?s response to isa i/o addresses enabled by the i/o base and i/o limit registers and located in the first 64 kb of the pci i/o address space. 1 = pex 8524 blocks forwarding from the primary to secondary interface, of i/o transactions addressing the last 768 bytes in each 1-kb block. in the opposite direction (secondary to primar y), i/o transactions are forwarded when they address the last 768 bytes in each 1-kb block. rw yes 0 19 vga enable silicon revision aa not supported cleared to 0. no 0 silicon revisions bb/bc modifies the pex 8524?s response to vga- compatible addres ses. when set, the bridge on the switch?s appropriate port positively decodes and forwards the following accesses on the prima ry to secondary interface (and, conversely, blocks the forwarding of these addresses from the secondary to primary interface): memory accesses in the range 000a_0000h to 000b_ffffh i/o address in the first 64 kb of the i/o address space [address[31:16] for pci express are zero (0000h)] and where address[9:0] is within the range of 3b0h to 3bbh or 3c0h to 3dfh (inclusive of isa address aliases ? address[15:10] can be any value and is not used in decoding) when the vga enable bit is set, vga address fo rwarding is independent of the isa enable bit value, and the i/o addres s range and memory address ranges defined by the i/o base and i/o limit , memory base address and memory limit address , and prefetchable memory base address and prefetchable memory limit address registers. vga address forwarding is qualified by the command register i/o access enable and memory access enable bits. 0 = does not forward vga-compatib le memory and i/o addresses from the primary to secondary interface (a ddresses defined above), unless they are enabled for forwarding by the de fined i/o and memory address ranges 1 = forwards vga-compatible memo ry and i/o addresses (addresses defined above) from the primary to secondary interface (when the i/o access enable and memory access enable bits are set), independent of the i/o and memory address ranges and isa enable bit rw yes 0 register 11-16. 3ch bridge control and interrupt signal (all ports) (cont.) bit(s) description type serial eeprom default
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 203 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 20 vga 16-bit decode silicon revision aa not supported cleared to 0. rw no 0 silicon revisions bb/bc enables the pex 8524 to provide 16-bit decoding of the vga i/o address, precluding the decoding of alias addresses every 1 kb. useful only when bit 19 ( vga enable ) of this register is also set to 1, enabling vga i/o decoding and bridge forwarding. enables system configurat ion software to select between 10- and 16-bit i/o address decoding for all vga i/o register accesses that are forwarded from the primary to se condary interface, when the vga enable bit is set to 1. 0 = execute 10-bit address decodes on vga i/o accesses 1 = execute 16-bit address decodes on vga i/o accesses rw yes 0 21 master abort mode cleared to 0, as required by the pci express base r1.0a. ro no 0 22 secondary bus reset 1 = causes a hot reset on the corresponding pex 8524 port secondary/ downstream pci bus rw yes 0 23 fast back-to-back transactions enable cleared to 0, as required by the pci express base r1.0a . ro no 0 24 primary discard timer cleared to 0, as required by the pci express base r1.0a . ro no 0 25 secondary discard timer cleared to 0, as required by the pci express base r1.0a . ro no 0 26 discard timer status cleared to 0, as required by the pci express base r1.0a . ro no 0 27 discard timer serr# enable cleared to 0, as required by the pci express base r1.0a . ro no 0 31:28 reserved 0h register 11-16. 3ch bridge control and interrupt signal (all ports) (cont.) bit(s) description type serial eeprom default
pex 8524 transparent mode port registers plx technology, inc. 204 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.7 power management capability registers this section details the pex 8524 power management capability registers. the register map is defined in table 11-5 . table 11-5. power management capability register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 power management capabili ty next capability pointer ( 48h ) capability id ( 01h ) 40h data power management control/ status bridge extensions power management status and control 44h register 11-17. 40h power management capability (all ports) bit(s) description type serial eeprom default 7:0 capability id set to 01h, indicating that the data stru cture currently being pointed to is the pci power management data structure. ro yes 01h 15:8 next capability pointer default 48h points to the message signaled interrupt capability register. ro yes 48h 18:16 ve rs i o n default 010b indicates compliance with the pci power mgmt. r1.1. ro yes 010b 19 pme clock cleared to 0, as required by the pci express base r1.0a. ro no 0 20 reserved 0 21 device-specific initialization default 0 indicates that device-specific initialization is not required. ro yes 0 24:22 aux current not supported default 000b indicates that the pex 8524 does not support auxiliary current requirements. ro yes 000b 25 d1 support not supported default 0 indicates that the pex 8524 does not support the d1 power state. ro no 0 26 d2 support not supported default 0 indicates that the pex 8524 does not support the d2 power state. ro no 0 31:27 pme support default 11001b indicates that the corresponding pex 8524 port forwards pme messages in the d0, d3hot, and d3cold power states. ro yes 11001b
february, 2007 power manage ment capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 205 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-18. 44h power management status and control (all ports) bit(s) description type serial eeprom default power management status and control 1:0 power state this field is used to determine the current power state of the port, and to set the port into a new power state. 00b = d0 01b = d1 ? not supported 10b = d2 ? not supported 11b = d3hot if software attempts to write an unsupported state to this field, the write operation completes normally; however, the data is discarded and no state change occurs. rw yes 00b 7:2 reserved ro no 0h 8 pme enable 0 = disables pme generation by the corresponding pex 8524 port a 1 = enables pme generation by the corresponding pex 8524 port rws no 0 12:9 data select rw by serial eeprom mode only b . bits [12:9] select the data and data scale registers. 0h = d0 power consumed 3h = d3hot power consumed 4h = d0 power dissipated 7h = d3hot power dissipated ro yes 0h ro for hardware auto-configuration. not supported ro no 0h 14:13 data scale rw by serial eeprom mode only b . there are four internal data scale registers per port. bits [12:9], data select , select the data scale register. ro yes 00b 15 pme status 0 = pme is not generated by the corresponding pex 8524 port a 1 = pme is being generated by the corresponding pex 8524 port rw1c no 0
pex 8524 transparent mode port registers plx technology, inc. 206 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 power management control/status bridge extensions 21:16 reserved 0-0h 22 b2/b3 support cleared to 0, as required by the pci power mgmt. r1.1 . ro no 0 23 bus power/clock control enable cleared to 0, as required by the pci power mgmt. r1.1 . ro no 0 power management data 31:24 data rw by serial eeprom mode only b . there are four internal data registers per port. bits [12:9], data select , select the data register. ro yes 00h a. because the pex 8524 does not support auxiliary power, this bit is not s ticky, and is always cleared to 0 at power-on reset. b. with no serial eeprom, reads return 00h for the data scale and data registers (for al l data selects). register 11-18. 44h power management status and control (all ports) (cont.) bit(s) description type serial eeprom default
february, 2007 message signaled interrupt capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 207 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.8 message signaled interrupt capability registers this section details the pex 8524 message signaled interrupt (msi) capability registers. the register map is defined in table 11-6 . table 11-6. message signaled interrupt capability register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved message control next capability pointer ( 68h ) capability id ( 05h ) 48h message address[31:0] 4ch message upper address[63:32] 50h reserved message data 54h reserved 58h ? 64h register 11-19. 48h message signaled interrupt capability (all ports) bit(s) description type serial eeprom default msi capability header 7:0 capability id set to 05h, as required by the pci r2.3. ro yes 05h 15:8 next capability pointer set to 68h to point to the pex 8524 pci express capability registers. ro yes 68h message control 16 msi enable 0 = message signaled interrupts fo r the corresponding port are disabled 1 = message signaled interrupts for the corresponding port are enabled rw yes 0 19:17 multiple message capable 000b = pex 8524 port is requesting one message ? the only value supported ro yes 000b 22:20 multiple message enable 000b = pex 8524 port contains only one allocated message ? the only value supported rw yes 000b 23 msi 64-bit address capable 1 = pex 8524 is capable of generati ng 64-bit message signaled interrupt addresses ro yes 1 31:24 reserved 00h
pex 8524 transparent mode port registers plx technology, inc. 208 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-20. 4ch message address[31:0] (all ports) bit(s) description type serial eeprom default 1:0 reserved 00b 31:2 message address[31:2] msi write transaction lower address[31:2]. note: refer to register offset 50h for message upper address[63:32]. rw yes 0000_0000h register 11-21. 50h message upper address[63:32] (all ports) bit(s) description type serial eeprom default 31:0 message address[63:32] msi write transaction upper address[63:32]. note: refer to register offset 4ch for message address[31:0]. rw yes 0000_0000h register 11-22. 54h message data (all ports) bit(s) description type serial eeprom default 15:0 message data msi write transact ion tlp payload. rw yes 0000h 31:16 reserved 0000h
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 209 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.9 pci express capability registers this section details the pex 8524 pci express capability registers. hot plug capability, command, status, and events are includ ed in these registers. the register map is defined in table 11-7 . table 11-7. pci express capability register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 pci express capabilities next capability pointer ( 00h ) capability id ( 10h ) 68h device capabilities 6ch device status device control 70h link capabilities 74h link status link control 78h slot capabilities 7ch slot status slot control 80h reserved 84h ? 8ch
pex 8524 transparent mode port registers plx technology, inc. 210 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-23. 68h pci express capability list and capabilities (all ports) bit(s) description ports type serial eeprom default pci express capability list 7:0 capability id set to 10h, as required by the pci express base r1.0a. ro yes 10h 15:8 next capability pointer 00h = pci express capability is the last capability in the pex 8524 port capabilities list the pex 8524 port extended capabi lities list starts at 100h . ro yes 00h pci express capabilities 19:16 capability version the pex 8524 ports sets this field to 1h, as required by the pci express base r1.0a. ro yes 1h 23:20 device/port type set at reset, as required by the pci express base r1.0a. upstream ro yes 5h downstream ro yes 6h 24 slot implemented 0 = disables or connects to an upstream port upstream ro no 0 0 = disables or connects to an integrated component a 1 = indicates that the downstre am port connects to a slot, as opposed to being connected to an integrated component or being disabled a. the pex 8524 serial eeprom register initialization capability is used to change this value to 0h, indicating that the corresponding pex 8524 downstream port connects to an integrated component or is disabled. downstream ro yes 1 29:25 interrupt me ssage number the serial eeprom writes 0000_0b, because the base message and msi messages are the same. ro yes 0000_0b 31:30 reserved 00b
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 211 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-24. 6ch device capabilities (all ports) bit(s) description ports type serial eeprom default 2:0 maximum payload size supported 000b = pex 8524 ports support 128-byte maximum payload 001b = pex 8524 ports support 256-byte maximum payload no other values are supported. note: serial eeprom must not load greater than 256 bytes maximum payload size. ro yes 001b 4:3 phantom functions supported not supported cleared to 00b. ro yes 00b 5 extended tag field supported 0 = maximum tag field is 5 bits 1 = maximum tag field is 8 bits ro yes 0 8:6 endpoint l0s acceptable latency not supported because the pex 8524 is a switch and not an endpoint, it does not support this feature. 000b = disables the capability ro yes 000b 11:9 endpoint l1 acceptable latency not supported because the pex 8524 is a switch and not an endpoint, it does not support this feature. 000b = disables the capability ro yes 000b
pex 8524 transparent mode port registers plx technology, inc. 212 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12 attention button present for the pex 8524 upstream port, value of 1 indicates that an attention button is implem ented on that adapter board. the pex 8524 serial eeprom register initialization capability is used to change this value to 0, indicating that an attention button is not present on an adapter board for which the pex 8524 provides the system interface. upstream hwinit yes 1 not valid for downstream ports. downstream ro no 0 13 attention indicator present for the pex 8524 upstream port, va lue of 1 indicates that an attention indicator is implemented on the adapter board. the pex 8524 serial eeprom register initialization capability is used to change this value to 0, indicating that an attention indicator is not present on an adapter board for which the pex 8524 provides the system interface. upstream hwinit yes 1 not valid for downstream ports. downstream ro no 0 14 power indicator present for the pex 8524 upstream port, value of 1 indicates that a power indicator is implemented on the adapter board. the pex 8524 serial eeprom register initialization capability is used to change th is value to 0, indicating that a power indicator is not present on an adapter board for which the pex 8524 provides the system interface. upstream hwinit yes 1 not valid for downstream ports. downstream ro no 0 17:15 reserved 000b 25:18 captured slot power limit value for the pex 8524 upstream port, the upper limit on power supplied by the slot is determined by multiplying the value in this field by the value in the captured slot power limit scale field. upstream ro yes 00h not valid for downstream ports. downstream ro no 0 27:26 captured slot power limit scale for the pex 8524 upstream port, the upper limit on power supplied by the slot is determined by multiplying the value in this field by the value in the captured slot power limit value field. 00b = 1.0 01b = 0.1 10b = 0.01 11b = 0.001 upstream ro yes 00b not valid for downstream ports. downstream ro no 0 31:28 reserved 0h register 11-24. 6ch device capabilities (all ports) (cont.) bit(s) description ports type serial eeprom default
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 213 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-25. 70h device status and control (all ports) bit(s) description type serial eeprom default device control 0 correctable error reporting enable 0 = disables 1 = enables corresponding pex 8524 por t to report correctable errors rw yes 0 1 non-fatal error enable 0 = disables 1 = enables corresponding pex 8524 port to report non-fatal errors rw yes 0 2 fatal error reporting enable 0 = disables 1 = enables corresponding pex 8524 port to report fatal errors rw yes 0 3 unsupported request reporting enable 0 = disables 1 = enables corresponding pex 8524 port to report unsupported request errors rw yes 0 4 pci express relaxed ordering enable not supported cleared to 0. ro no 0 7:5 maximum payload size software can change this field to c onfigure the pex 8524 ports to support other payload sizes; however, software cannot ch ange this field to a value larger than that indicated by the device capabilities register maximum payload size supported field (offset 6ch [2:0]). 000b = indicates that initia lly the pex 8524 port is configured to support a maximum payload size of 128 bytes 001b = indicates that initia lly the pex 8524 port is configured to support a maximum payload size of 256 bytes no other values are supported. rw yes 000b 8 extended tag field enable not supported cleared to 0. ro no 0 9 phantom functions enable not supported cleared to 0. ro no 0 10 auxiliary (aux) power pm enable not supported cleared to 0. ro no 0 11 no snoop enable not supported cleared to 0. ro no 0 14:12 maximum read request size not supported cleared to 000b. ro no 000b 15 reserved 0
pex 8524 transparent mode port registers plx technology, inc. 214 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 device status 16 correctable error detected 1 = corresponding pex 8524 port detected a correctable error set when the corresponding port detects a correctable error, regardless of the bit 0 ( correctable error reporting enable bit) state. rw1c yes 0 17 non-fatal error detected 1 = corresponding pex 8524 port detected a non-fatal error set when the corresponding port detect s a non-fatal error, regardless of the bit 1 ( non-fatal error enable bit) state. rw1c yes 0 18 fatal error detected 1 = corresponding pex 8524 port detected a fatal error set when the corresponding port dete cts a fatal error, regardless of the bit 2 ( fatal error reporting enable bit) state. rw1c yes 0 19 unsupported request detected 1 = corresponding pex 8524 port detected an unsupported request set when the corresponding port detects an unsupported request, regardless of the bit 3 ( unsupported request reporting enable bit) state. rw1c yes 0 20 auxiliary (aux) power detected not supported cleared to 0. ro no 0 21 transactions pending not supported cleared to 0. ro no 0 31:22 reserved 000h register 11-25. 70h device status and control (all ports) (cont.) bit(s) description type serial eeprom default
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 215 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-26. 74h link capabilities (all ports) bit(s) description type serial eeprom default 3:0 maximum link speed set to 0001b, as required by the pci express base r1.0a. ro yes 0001b 9:4 maximum link width actual link width is set by signal ba ll strapping options. the pex 8524 maximum link width is x8 = 00_1000b (station 0), or x16 = 01_0000b (station 1). ro no strap levels 11:10 active state power management (aspm) support indicates the level of aspm supported by the port. 01b = l0s link power state entry is supported 10b = l0s and l1 link power states are supported all other values are reserved . ro yes 11b 14:12 l0s exit latency 101b = corresponding pex 8524 port l0s ex it latency is between 1 and 2 s ro no 101b 17:15 l1 exit latency 101b = corresponding pex 8524 port l1 exit latency is between 16 and 32 s ro yes 101b 23:18 reserved 0-0h 31:24 port number the port number is set by signal ball strapping options: strap_stn0_portcfg[4:0] ? ports 0, 1 strap_stn1_portcfg[3:0] ? ports 8, 9, 10, 11 hwinit no set by strap levels
pex 8524 transparent mode port registers plx technology, inc. 216 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-27. 78h link status and control (all ports) bit(s) description ports type serial eeprom default link control 1:0 active state power management (aspm) control 00b = disables l0s and l1 entries for the corresponding pex 8524 port a 01b = enables only l0s entry 10b = enables only l1 entry 11b = enables both l0s and l1 entries rw yes 00b 2 reserved 0 3 read completion boundary (rcb) cleared to 0, as required by the pci express base r1.0a. ro yes 0 4 link disable not valid for the upstream port. upstream ro no 0 setting to 1 places the li nk on the corresponding pex 8524 downstream port to the di sabled link training state. downstream rw yes 0 5 retrain link not valid for the upstream port. upstream ro no 0 for pex 8524 ports, when read, always returns 0. writing 1 to this bit caus es the corresponding pex 8524 downstream port to initiate retr aining of its pci express link. downstream rw yes 0 6 common clock configuration 0 = corresponding pex 8524 port and th e device at the other end of the corresponding port?s pci express link are operating with an asynchronous reference clock 1 = corresponding pex 8524 port and th e device at the other end of the corresponding port?s pci expres s link are operating with a distributed common reference clock rw yes 0 7 extended sync set to 1 causes the corresponding pex 8524 port to transmit: 4,096 fts ordered-sets in the l0s state, followed by a single skip ordered-set prior to entering the l0 state, finally, transmission of 1,024 ts1 or dered-sets in the recovery state. rw yes 0 15:8 reserved 00h
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 217 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 link status 19:16 link speed set to 1h, as required by the pci express base r1.0a for a 2.5 gbps pci express link. ro yes 1h 25:20 negotiated link width link width is determined by negotia ted value with attached port/lane: 00_0001b = x1 00_0010b = x2 00_0100b = x4 00_1000b = x8 01_0000b = x16 (station 1 only) all other values are not supported . the value in this field is undefined when the link is not up. ro yes 00_0001b 26 training error not valid for the upstream port. upstream ro no 0 when set to 1, indicates that the corresponding pex 8524 port detected a link training error. downstream ro yes 0 27 link training not valid for the upstream port. upstream ro no 0 when set to 1, indicates that the corresponding pex 8524 downstream port requested link training and either the link training is in process or about to start. downstream ro no 0 28 slot clock configuration 0 = indicates pex 8524 uses an independent clock 1 = indicates pex 8524 uses the same physic al reference clock that the platform provides on the connector hwinit yes 0 31:29 reserved 000b a. the port receiver must be capable of entering l0s state, regardless of whether the state is disabled. register 11-27. 78h link status and control (all ports) (cont.) bit(s) description ports type serial eeprom default
pex 8524 transparent mode port registers plx technology, inc. 218 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: register offset 7ch is used only for downstream ports. register 11-28. 7ch slot capabilities (all ports) bit(s) description ports type serial eeprom default 0 attention button present not valid for the upstream port. upstream 0 0 = attention button is not implemented 1 = attention button is implemen ted on the slot chassis of the corresponding pex 8524 downstream port downstream hwinit yes 1 1 power controller present not valid for the upstream port. upstream 0 0 = power controller is not implemented 1 = power controller is implemented for the slot of the corresponding pex 8524 downstream port downstream hwinit yes 1 2 mrl sensor present not valid for the upstream port. upstream 0 0 = mrl sensor is not implemented 1 = mrl sensor is implemented on the slot chassis of the corresponding pex 8524 downstream port downstream hwinit yes 1 3 attention indicator present not valid for the upstream port. upstream 0 0 = attention indicato r is not implemented 1 = attention indicator is impl emented on the slot chassis of the corresponding pex 8524 downstream port downstream hwinit yes 1
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 219 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4 power indicator present not valid for the upstream port. upstream 0 0 = power indicator is not implemented 1 = power indicator is implemente d on the slot chassis of the corresponding pex 8524 downstream port downstream hwinit yes 1 5 hot plug surprise not valid for the upstream port. upstream 0 0 = no device in the corresponding pex 8524 downstream port slot is removed from the system without prior notification 1 = device in the correspondi ng pex 8524 downstream port slot can be removed from the sy stem without prior notification downstream hwinit yes 0 6 hot plug capable not valid for the upstream port. upstream 0 0 = corresponding pex 8524 downstream port slot is not capable of supporting hot plug operations 1 = corresponding pex 8524 downstream port slot is capable of supporting hot plug operations downstream hwinit yes 1 14:7 slot power limit value do not change for upstream port. upstream 00h the maximum power available from the corresponding pex 8524 downstream port is dete rmined by multiplying the value in this field (expressed in decimal; 25d = 19h) by the value specified by the slot power limit scale field. downstream hwinit yes 19h 16:15 slot power limit scale not valid for the upstream port. upstream 00b the maximum power available from the corresponding pex 8524 downstream port is dete rmined by multiplying the value in this field by the slot power limit value field . 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x downstream hwinit yes 00b 18:17 reserved 00b 31:19 physical slot number not valid for the upstream port. upstream 0-0h specifies a non-zero identification number for the corresponding pex 8524 downstream port slot. downstream hwinit yes 0-0h register 11-28. 7ch slot capabilities (all ports) (cont.) bit(s) description ports type serial eeprom default
pex 8524 transparent mode port registers plx technology, inc. 220 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 notes: register offset 80h is used only for downstream ports. if the power indicator present and/or attention indicator present bits (offset 7ch [4:3]) are set, writes to the slot control register (offset 80h[15:0]) cause the downstrea m port to send the appropriate power_indicator_* and attention_indicator_* messages (on/blink/off) to the downstream device, unless the power indicator control and attention indicator control field (offset 80h[9:8 and 7:6], respectively) values that are written are the reserved value 00b. writing 00b to each of these fields is ignored (the stored value is not changed and the hot plug message is not sent). therefore, when writing to this register, the value written to both fields should be 00b unless the purpose of the write command is to change the state of the port?s hp_atnledx# or hp_pwrledx# output signals, in which case byte writes can be used to target only one of the two control fields. register 11-29. 80h slot status and control (all ports) bit(s) description ports type serial eeprom default slot control 0 attention button pressed enable not valid for the upstream port. upstream ro no 0 0 = function is disabled 1 = enables software notification with a hot plug interrupt if the port is in the d0 power state ( power management status and control register power state field, offset 44h [ 1:0 ]=00b), or with a pme message if the port is in the d3hot state (offset 44h[1:0]=11b), for an attention button pressed event on the corresponding pex 8524 downstream port. downstream rw yes 0 1 power fault detector enable not valid for the upstream port. upstream ro no 0 0 = function is disabled 1 = enables software notification with a hot plug interrupt if the port is in the d0 power state ( power management status and control register power state field, offset 44h[1:0]=00b), or with a pme message if the port is in the d3hot state (offset 44h[1:0]=11b), for a power fault event on the corresponding pex 8524 downstream port. downstream rw yes 0
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 221 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 2 mrl sensor changed enable not valid for the upstream port. upstream ro no 0 0 = function is disabled 1 = enables software notification with a hot plug interrupt if the port is in the d0 power state ( power management status and control register power state field, offset 44h[1:0]=00b), or with a pme message if the port is in the d3hot state (offset 44h[1:0]=11b), for an mrl sensor changed event on the corresponding pex 8524 downstream port. downstream rw yes 0 3 presence detect changed enable not valid for the upstream port. upstream ro no 0 0 = function is disabled 1 = enables software notification with a hot plug interrupt if the port is in the d0 power state ( power management status and control register power state field, offset 44h[1:0]=00b), or with a pme message if the port is in the d3hot state (offset 44h[1:0]=11b), for a presence detect changed event on the corresponding pex 8524 downstream port. a presence detect changed event is triggered from one of two sources, dependi ng on the state of the hpc inband presence detect enable bit ( 1e0h [ 5 ]): if the hpc inband presence detect enable bit is cleared (offset 1e0h[5] =0, default), presence detect is input from the hp_prsnt x # signal on the corresponding pex 8524 downstream port if the hpc inband presence detect enable bit is set (offset 1e0h[5]=1), presence detect is input from the serdes receiver detect on the corresponding pex 8524 downstream port downstream rw yes 0 register 11-29. 80h slot status and control (all ports) (cont.) bit(s) description ports type serial eeprom default
pex 8524 transparent mode port registers plx technology, inc. 222 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 4 command completed interrupt enable not valid for the upstream port. upstream ro no 0 0 = function is disabled 1 = enables software notification with a hot plug interrupt when a command is completed by the hot plug controller on the corresponding pex 8524 downstream port downstream rw yes 0 5 hot plug interrupt enable not valid for the upstream port. upstream ro no 0 0 = function is disabled 1 = enables a hot plug interrupt on enabled hot plug events for the corresponding pex 8524 downstream port downstream rw yes 0 7:6 attention indicator control do not change for upstream port. upstream ro no 00b control the attention indicator on the corresponding pex 8524 downstream port slot. 00b = reserved ? writes are ignored 01b = turns on indicator to constant on state 10b = causes indicator to blink 11b = turns off indicator software must use a byte or word write (and not a dword write) to control the hp_atnled x # output signal. reads return the corresponding pex 8524 downstream port attention indicator?s current state. downstream rw yes 11b register 11-29. 80h slot status and control (all ports) (cont.) bit(s) description ports type serial eeprom default
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 223 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 9:8 power indicator control do not change for upstream port. upstream ro no 00b controls the power indicator on the corresponding pex 8524 downstream port slot. 00b = reserved ? writes are ignored 01b = turns on indicator to constant on state 10b = causes indicator to blink 11b = turns off indicator software must use a byte or word write (and not a dword write) to control the hp_pwrled x # output signal. reads return the corresponding pex 8524 downstream port power indicator?s current state. downstream rw yes 11b (mrl open) 01b (mrl closed) 10 power controller control not valid for the upstream port. upstream ro no 0 controls the power controller on the corresponding pex 8524 downstream port slot. 0 = turns on power contro ller; requires some delay to be effective 1 = turns off power controller software must use a byte or word write (and not a dword write) to control the power controller output signals. note: value of 0 requires some delay to be effective. downstream rw yes 1 (mrl open) 0 (mrl closed) 15:11 reserved 0-0h register 11-29. 80h slot status and control (all ports) (cont.) bit(s) description ports type serial eeprom default
pex 8524 transparent mode port registers plx technology, inc. 224 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 slot status 16 attention button pressed not valid for the upstream port. upstream ro no 0 set to 1 when the attention button of the corresponding pex 8524 downstream port slot is pressed. downstream rw1c yes 0 17 power fault detected not valid for the upstream port. upstream ro no 0 set to 1 when the power controller of the corresponding pex 8524 downstream port slot detects a power fault at the slot. downstream rw1c yes 0 18 mrl sensor changed not valid for the upstream port. upstream ro no 0 set to 1 when an mrl state change is detected on the corresponding pex 8524 downstream port slot. downstream rw1c yes 0 19 presence detect changed not valid for the upstream port. upstream ro no 0 set to 1 when a presence detect change is detected on the corresponding pex 8524 downstream port slot. a presence detect changed event is triggered from one of two sources, dependi ng on the state of the hpc inband presence detect enable bit ( 1e0h [ 5 ]): if the hpc inband presence detect enable bit is cleared (offset 1e0h[5] =0, default), presence detect is input from the hp_prsnt x # signal on the corresponding pex 8524 downstream port if the hpc inband presence detect enable bit is set (offset 1e0h[5]=1), presence detect is input from the serdes receiver detect on the corresponding pex 8524 downstream port downstream rw1c yes 0 register 11-29. 80h slot status and control (all ports) (cont.) bit(s) description ports type serial eeprom default
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 225 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 20 command completed do not change for upstream port. upstream ro no 0 set to 1 when the hot plug controller on the corresponding pex 8524 downstream port slot completes an issued command. downstream rw1c yes 0 21 mrl sensor state do not change for upstream port. upstream ro no 0 reveals the corresponding pex 8524 downstream port mrl sensor?s current state. 0 = mrl sensor closed 1 = mrl sensor open downstream ro yes 0 22 presence detect state do not use for upstream port. upstream ro no 0 reveals the corresponding pex 8524 downstream port?s current presence state. presence is determined from one of two sources, depending on the state of the hpc inband presence detect enable bit ( 1e0h [ 5 ]): if the hpc inband presence detect enable bit is cleared (offset 1e0h[5] =0, default), presence detect is input from the hp_prsnt x # signal on the corresponding pex 8524 downstream port if the hpc inband presence detect enable bit is set (offset 1e0h[5]=1), presence detect is input from the serdes receiver detect on the corresponding pex 8524 downstream port 0 = slot is empty, or device is not present 1 = slot is occupied, or device is present downstream ro yes 0 31:23 reserved 0-0h register 11-29. 80h slot status and control (all ports) (cont.) bit(s) description ports type serial eeprom default
pex 8524 transparent mode port registers plx technology, inc. 226 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.10 device serial number extended capability registers this section details the pex 8524 device serial number extended capability registers. the register map is defined in table 11-8 . table 11-8. pex 8524 device serial number extended capability register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next capability offset ( fb4h ) capability ve r s i o n ( 1h ) extended capability id ( 0003h ) 100h serial number (lower dw) 104h serial number (higher dw) 108h register 11-30. 100h device serial number extended capability bit(s) description type serial eeprom default 15:0 extended capability id set to 0003h, as required by the pci express base r1.0a. ro yes 0003h 19:16 capability version set to 1h, as required by the pci express base r1.0a. ro yes 1h 31:20 next capability offset set to fb4h, which is the pci express enhanced capability header registers. ro yes fb4h register 11-31. 104h serial number (lower dw) (all ports) bit(s) description type serial eeprom default 31:0 serial number[31:0] lower half of a 64-bit register. value set by serial eeprom register initialization. ro yes 0000_0edfh register 11-32. 108h serial number (higher dw) (all ports) bit(s) description type serial eeprom default 31:0 serial number[63:32] upper half of a 64-bit register. value set by serial eeprom register initialization. ro yes 0000_0001h
february, 2007 power budgeting extended capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 227 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.11 power budgeting extended capability registers this section details the pex 8524 power budgeting ex tended capability registers. the register map is defined in table 11-9 . table 11-9. pex 8524 power budgeting extended capability register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next capability offset ( 148h ) capability ve r s i o n ( 1h ) extended capability id ( 0004h ) 138h reserved data select 13ch power budgeting data 140h reserved power budget capability 144h register 11-33. 138h power budgeting extended capability (all ports) bit(s) description type serial eeprom default 15:0 extended capability id set to 0004h, as required by the pci express base r1.0a. ro yes 0004h 19:16 capability version set to 1h, as required by the pci express base r1.0a. ro yes 1h 31:20 next capability offset set to 148h , which addresses the pex 8524 virtual channel extended capability registers. ro yes 148h register 11-34. 13ch data select (all ports) bit(s) description type serial eeprom default 7:0 data select indexes the power budgeting data reported by way of eight power budgeting data registers per port and selects the dword of power budgeting data that appears in each power budgeting data register. index values start at 0, to select the first dword of power budgeting data; subseque nt dwords of power budgeting data are selected by increasing index values 1 to 7. rw yes 00h 31:8 reserved 0-0h
pex 8524 transparent mode port registers plx technology, inc. 228 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: there are eight registers per port that can be programmed, through the serial eeprom. each non-zero register value describes the power usage for a different operating condition. each configuration is selected by writing to the data select register data select field (offset 13ch [ 7:0 ]). register 11-35. 140h power budgeting data (all ports) bit(s) description type serial eeprom default 7:0 base power eight registers/port. specifies (in watts) the base power value in the operating condition. this value must be multiplied by the data scale to produce the actual power consumption value. ro yes 00h 9:8 data scale specifies the scale to apply to the base power value. the power consumption of the device is determined by multiplying the base power field contents with the value corresponding to the encoding returned by this field. 00b = 1.0x 01b = 0.1x 10b = 0.01x 11b = 0.001x ro yes 00b 12:10 pm sub-state 000b = corresponding pex 8524 port is in th e default power mana gement sub-state ro yes 000b 14:13 pm state current power state. 00b = d0 state 01b = not used ? d1 state not supported 10b = not used ? d2 state not supported 11b = d3 state ro yes 00b 17:15 type type of operating condition. 000b = pme auxiliary 001b = auxiliary 010b = idle 011b = sustained 111b = maximum all other values are reserved . ro yes 000b 20:18 power rail power rail of operating condition. 000b = power 12v 001b = power 3.3v 010b = power 1.8v 111b = thermal all other values are reserved . ro yes 000b 31:21 reserved 0-0h register 11-36. 144h power budget capability (all ports) bit(s) description type serial eeprom default 0 system allocated 1 = power budget for the device is in cluded within the system power budget hwinit yes 1 31:1 reserved 0-0h
february, 2007 virtual channel extended capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 229 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.12 virtual channel extended capability registers this section details the pex 8524 virtual channel ex tended capability registers. these registers are duplicated for each port. the register map for one port is defined in table 11-10 . table 11-10. pex 8524 virtual channel extended capability register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next capability offset ( 000h ) capability ve r s i o n ( 1h ) extended capability id ( 0002h ) 148h port vc capability 1 14ch port vc capability 2 150h port vc status port vc control 154h vc0 resource capability 158h vc0 resource control 15ch vc0 resource status reserved 160h vc1 resource capability 164h vc1 resource control 168h vc1 resource status reserved 16ch reserved 170h ? 1b4h virtual channel ar bitration table 1b8h ? 1c4h register 11-37. 148h virtual channel extended capability (all ports) bit(s) description type serial eeprom default 15:0 extended capability id set to 0002h, as required by the pci express base r1.0a . ro yes 0002h 19:16 capability version set to 1h, as required by the pci express base r1.0a . ro yes 1h 31:20 next capability offset set to 000h, indicating that the virtual ch annel extended capabi lity is the last extended capability in the port extended capability list. ro yes 000h
pex 8524 transparent mode port registers plx technology, inc. 230 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-38. 14ch port vc capability 1 (all ports) bit(s) description type serial eeprom default 0 extended vc count 0 = pex 8524 supports only the default virtual channel (vc0) 1 = pex 8524 ports support one extended virtual channel (vc1) ro yes 1 3:1 reserved 000b 4 low-priority extended vc count for strict priority arbitration, this bi t indicates the number of extended virtual channels (those in a ddition to the default virtual channel 0) that belong to the low-priority virtual channel group for this pex 8524 port. pex 8524 serial eeprom register initiali zation capability is used to change this field to 1 to also set vc1 to the low-priority virtual channel group. 0 = for this pex 8524 port, only the default virtual channel 0 belongs to the low-priority virtual channel group 1 = for this pex 8524 port, vc0 and vc1 belong to the low-priority virtual channel group ro yes 0 7:5 reserved 000b 9:8 reference clock not supported cleared to 00b. ro no 00b 11:10 port arbitration table entry size not supported cleared to 00b. ro no 00b 31:12 reserved 0-0h register 11-39. 150h port vc capability 2 (all ports) bit(s) description type serial eeprom default 1:0 vc arbitration capability bit 0 value of 1 indicates round-robin (hardware-fixed) arbitration scheme is supported. bit 1 value of 1 indicates weighted round-robin arbitration with 32 phases is supported. ro yes 11b 23:2 reserved 0-0h 31:24 vc arbitration table offset virtual channel arbitration table zero-bas ed offset in quad dwords (16 bytes) from the base address of pex 8524 port vi rtual channel capa bility structure. ro yes 07h
february, 2007 virtual channel extended capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 231 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-40. 154h port vc status and control (all ports) bit(s) description type serial eeprom default port vc control 0 load vc arbitration table writing 1 updates the vc arbitration table for the corresponding pex 8524 port. reading this bit always returns 0. rw yes 0 1 vc arbitration select selects the vc arbitration type for the corresponding pex 8524 port. indicates the bit number in the port vc capability 2 register vc arbitration capability field that corresponds to the arbitration type: 0 = bit 0; round-robin (hardwar e-fixed) arbitration scheme 1 = bit 1; weighted round-robin with 32 phases select only an arbitration type, th at corresponds to a bit set in the vc arbitration capability field. cannot be modified wh en more than one lpvc group vc is enabled. rw yes 0 15:2 reserved 0-0h port vc status 16 vc arbitration table status set to 1 when there is a write to the vc arbitration table. cleared by the corresponding pex 8524 port when the port completes loading the values stored in its vc arbitrat ion table after software sets the load vc arbitration table bit. ro yes 0 31:17 reserved 0-0h register 11-41. 158h vc0 resource capability (all ports) bit(s) description type serial eeprom default 0 port arbitration capability 1 = non-configurable hardware-fixed port arbitration the only configuration supported by the pex 8524. ro yes 1 13:1 reserved 0-0h 14 advanced packet switching not supported cleared to 0. ro no 0 15 reject snoop transactions not a pci express switch feature; therefore, this bit is cleared to 0. ro no 0 22:16 maximum time slots not supported cleared to 000_0000b. ro no 000_0000b 23 reserved 0-0h 31:24 port arbitration table offset not supported cleared to 00h. ro no 00h
pex 8524 transparent mode port registers plx technology, inc. 232 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-42. 15ch vc0 resource control (all ports) bit(s) description type serial eeprom default 0 tc/vc0 map defines traffic classes [7:0], respectively, and indicates which tcs are mapped into virtual channel 0. traffic class 0 (tc0) must be mapped to virtual channel 0. by default, traffic classe s [7:1] are mapped to vc0. ro yes ffh 7:1 rw yes 15:8 reserved 00h 16 load port arbitration table not supported cleared to 0. ro no 0 19:17 port arbitration select not supported cleared to 000b. ro no 000b 23:20 reserved 0-0h 26:24 vc0 id defines the corresponding pex 8524 por t virtual channel 0 id code. because this is the default vc 0, it is cleared to 000b. ro yes 000b 30:27 reserved 0-0h 31 vc0 enable 0 = not allowed 1 = enables corresponding pex 8524 port default virtual channel 0 ro yes 1 register 11-43. 160h vc0 resource status (all ports) bit(s) description type serial eeprom default 15:0 reserved 0000h 16 port arbitration table status not supported cleared to 0. ro no 0 17 vc0 negotiation pending 0 = vc0 negotiation completed 1 = vc0 initialization is not comple te for the corresponding pex 8524 port ro yes 1 31:18 reserved 0-0h
february, 2007 virtual channel extended capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 233 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-44. 164h vc1 resource capability (all ports) bit(s) description type serial eeprom default 0 port arbitration capability 1 = non-configurable hardwa re-fixed port arbitration the only configuration supported by pex 8524. ro yes 1 13:1 reserved 0-0h 14 advanced packet switching not supported cleared to 0. ro no 0 15 reject snoop transactions not valid for pex 8524. ro no 0 22:16 maximum time slots not supported cleared to 000_0000b. ro no 000_0000b 23 reserved 0 31:24 port arbitration table offset not supported cleared to 00h. ro no 00h register 11-45. 168h vc1 resource control (all ports) bit(s) description type serial eeprom default 0 tc/vc1 map defines traffic classes [7:1], respectively, and indicates which tcs are mapped into virtual channel 1. traffic class 0 must be mapped to virtual channel 0. traffic classes [7:1] can be mapped to vc1. ro no 00h 7:1 rw yes 15:8 reserved 0-0h 16 load port arbitration table not supported cleared to 0. ro no 0 19:17 port arbitration select not supported cleared to 000b. ro no 000b 23:20 reserved 0-0h 26:24 vc1 id defines the id code for the corresp onding pex 8524 port virtual channel 1 (001b is the only supported value). rw yes 001b 30:27 reserved 0000b 31 vc1 enable 0 = disables corresponding pex 8524 port virtual channel 1 1 = enables corresponding pex 8524 port virtual channel 1 rw yes 0
pex 8524 transparent mode port registers plx technology, inc. 234 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.12.1 virtual channel arbitration table this section details the pex 8524 virtual channel arb itration registers. the register map is defined in table 11-11 . register 11-46. 16ch vc1 resource status (all ports) bit(s) description type serial eeprom default 15:0 reserved 0000h 16 port arbitration table status not supported cleared to 0. ro no 0 17 vc1 negotiation pending 0 = vc1 negotiation completed 1 = vc1 initialization or disabling is pending for the corresponding pex 8524 port ro yes 0 31:18 reserved 0-0h table 11-11. virtual channel arbitration table register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 phase 7phase 6phase 5phase 4pha se 3 phase 2 phase 1 phase 0 1b8h phase 15 phase 14 phase 13 phase 12 phase 11 phase 10 phase 9 phase 8 1bch phase 23 phase 22 phase 21 phase 20 phase 19 phase 18 phase 17 phase 16 1c0h phase 31 phase 30 phase 29 phase 28 phase 27 phase 26 phase 25 phase 24 1c4h register 11-47. 1b8h - 1c4h vc arbitration table phase n definition (where n = 0 to 31) bit(s) description type serial eeprom default 0 phase n [0] vc arbitration table phases are used to de termine the weighting of the two virtual channels during ?weighted r ound-robin with 32 phases? virt ual channel arbitration. this table is used only if weighted round-robin with 32 phases virtual channel arbitration is selected by way of the vc arbitration select bit. phases are assigned by setting phase n [0] of that phase: 0 = virtual channel 0 1 = virtual channel 1 rw yes 0 3:1 phase n [3:1] ro no 000b
february, 2007 plx-specific registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 235 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13 plx-specific registers plx-specific registers are unique to the pe x 8524 device and are not referenced in the pci express base r1.0a . table 11-12 defines the register map. note: this register group is accesse d using a memory-mapped cycle. it is recommended that these register values not be changed. table 11-12. plx-specific register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 error checking and debug registers 1c8h ? 1fch physical layer registers 200h ? 2c4h cam routing registers 2c8h ? 344h ingress control registers 660h ? 668h i/o cam base and limit upper 16 bits registers 680h ? 6ach base address registers (bars) 6c0h ? 73ch shadow virtual channel (v c) capability registers 740h ? 9ech ingress credit handler (inch) registers 9f0h ? b7ch reserved b80h ? be4h ingress one-bit ecc error count register be8h relaxed completion ordering (ingress) register ? silicon revisions bb/bc only bech relaxed ordering mode (ingress) register bf0h ? bfch internal credit handler (itch ) vc&t threshold registers c00h ? c08h
pex 8524 transparent mode port registers plx technology, inc. 236 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.1 error checking and debug registers table 11-13. plx-specific error checking and debug register map (ports a ) a. certain registers are port-specifi c, some are station-specific, while others are device-specific. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ecc check disable 1c8h error handler 32-bit error status (factory test only) 1cch error handler 32-bit error mask (factory test only) 1d0h factory test only 1d4h ? 1d8h debug control 1dch power management hot pl ug user configuration 1e0h egress control and status 1e4h reserved bad tlp count 1e8h reserved bad dllp count 1ech plx-specific relaxed ordering enable 1f0h software-controlled lane status 1f4h reserved ack transmission latency limit 1f8h reserved 1fch register 11-48. 1c8h ecc check disable (only ports 0 and 8) bit(s) description type serial eeprom default 0 ecc 1-bit error check disable 0 = ram 1-bit soft error check enabled 1 = disables ram 1-bit soft error check rw yes 0 1 ecc 2-bit error check disable 0 = ram 2-bit soft error check enabled 1 = disables ram 2-bit soft error check rw yes 0 31:2 reserved 0-0h
february, 2007 error checking and debug registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 237 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: all errors in register offset 1cch generate msi/intx interrupts, when enabled. register 11-49. 1cch error handler 32-bit error status ( only port 0, factory test only) bit(s) description bit exists only on port(s) type serial eeprom default 0 completion fifo overflow status 0 = no overflow detected 1 = completion fifo overflow detected when 4-deep completion fifo for ingress, or 2-deep completion fifo for egress, overflows 0, 1, 8, 9, 10, 11 rw1cs yes 0 1 egress pram soft-error overflow egress packet ram 1-bit soft error counter overflow. 0 = no error detected 1 = egress pram 1-bit soft-error (8-bit counter) overflow; when destination pa cket ram 1-bit soft error count is greater than or e qual to 256, generates an msi/ int x interrupt, if enabled 0, 8 rw1cs yes 0 2 egress llist soft-error overflow egress link-list ram 1-bit soft error counter overflow. 0 = no error detected 1 = egress link-list 1-bit soft-error (8-bit counter) overflow; when destination module link lists ram 1-bit soft error count is greater th an or equal to 256, generates an msi/int x interrupt, if enabled 0, 8 rw1cs yes 0 3 egress pram ecc error egress packet ram 2-bit error detection. 0 = no error detected 1 = egress pram 2-bit ecc error detected 0, 8 rw1cs yes 0 4 egress llist ecc error egress link-list ram 2-bit error detection. 0 = no error detected 1 = egress link-list 2-bit ecc error detected 0, 8 rw1cs yes 0 5 ingress ram 1-bit ecc error source packet ram 1-bit soft error detection. 0 = no error detected 1 = ingress ram 1-bit ecc error detected 0, 8 rw1cs yes 0 6 egress memory allocation unit (mau) 1-bit soft error counter overflow egress memory allocation/de-allocation ram 1-bit soft error count is greater than or equal to 8. 0 = no error detected 1 = egress mau 1-bit soft-error overflow 0, 8 rw1cs yes 0 7 egress memory allocation unit (mau) 2-bit soft error egress packet memory al location/de-allocation ram 2-bit error detection. 0 = no 2-bit error detected 1 = egress mau 2-bit soft error detected 0, 8 rw1cs yes 0
pex 8524 transparent mode port registers plx technology, inc. 238 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8 ingress ram uncorrectable ecc error ingress packet ram 2-bit error detection. 0 = no 2-bit error detected 1 = packet ram uncorrectable ecc error detected 0, 8 rw1cs yes 0 9 ingress llist 1-bit ecc error ingress link-list ram 1-bi t soft error detection. 0 = no error detected 1 = 1-bit ecc error detected 0, 8 rw1cs yes 0 10 ingress llist uncorrectable ecc error ingress packet link-list ram 2-bit error detection. 0 = no 2-bit error detected 1 = ingress link-list uncorre ctable ecc error detected 0, 8 rw1cs yes 0 11 credit update timeout status no useful credit update to make forward progress for 512 ms or 1s (disabled by default). 0 = no credit update timeout detected 1 = credit update timeout completed 0, 1, 8, 9, 10, 11 rw1cs yes 0 12 inch underrun error ingress credit underrun. 0 = no error detected 1 = credit underrun error detected 0, 1, 8, 9, 10, 11 rw1cs yes 0 13 ingress memory allocation unit 1-bit soft error counter overflow ingress memory allocation/ de-allocation ram 1-bit soft-error count greater than or equal to 8. 0 = no error detected 1 = 1-bit soft error counter is > 8 0, 8 rw1cs yes 0 14 ingress memory allocation unit 2-bit soft error ingress memory allocation/ de-allocation ram 2-bit error detection for transac tion layer ingress memory allocation/de-allocation unit. 0 = no error detected 1 = 2-bit soft error detected 0, 8 rw1cs yes 0 31:15 reserved 0-0h register 11-49. 1cch error handler 32-bit error status ( only port 0, factory test only) (cont.) bit(s) description bit exists only on port(s) type serial eeprom default
february, 2007 error checking and debug registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 239 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: error logging is enabled in register offset 1d0h, by default. register 11-50. 1d0h error handler 32-bit error mask ( only port 0, factory test only) bit(s) description bit exists only on port(s) type serial eeprom default 0 completion fifo overflow mask 0 = if enabled, error generates msi/int x interrupt 1 = completion fifo overflow status bit is masked/ disabled 0, 8 rws yes 1 1 egress pram soft-error overflow mask 0 = no effect on reporting activity 1 = egress pram soft-error overflow bit is masked/ disabled 0, 1, 8, 9, 10, 11 rws yes 1 2 egress llist soft-error overflow mask 0 = no effect on reporting activity 1 = egress llist soft-error overflow bit is masked/ disabled 0, 8 rws yes 1 3 egress pram ecc error mask 0 = no effect on reporting activity 1 = egress pram ecc error bit is masked/disabled 0, 8 rws yes 1 4 egress llist ecc error mask 0 = no effect on reporting activity 1 = egress llist ecc error bit is masked/disabled 0, 8 rws yes 1 5 ingress ram 1-bit ecc error mask 0 = no effect on reporting activity 1 = ingress ram 1-bit ecc error bit is masked/disabled 0, 8 rws yes 1 6 egress memory allocation unit 1-bit soft-error counter overflow mask 0 = no effect on reporting activity 1 = egress memory allocation unit (mau) 1-bit soft error counter overflow bit is masked/disabled 0, 8 rws yes 1 7 egress memory allocation unit 2-bit soft error mask 0 = no effect on reporting activity 1 = egress memory allocation unit (mau) 2-bit soft error bit is masked/disabled 0, 8 rws yes 1
pex 8524 transparent mode port registers plx technology, inc. 240 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8 ingress ram uncorrectable ecc error mask 0 = no effect on reporting activity 1 = ingress ram uncorrectable ecc error bit is masked/ disabled 0, 8 rws yes 1 9 ingress llist 1-bit ecc error mask 0 = no effect on reporting activity 1 = ingress ram 1-bit ecc error bit is masked/disabled 0, 8 rws yes 1 10 ingress llist uncorrectable ecc error mask 0 = no effect on reporting activity 1 = ingress llist uncorrectable ecc error bit is masked/disabled 0, 8 rws yes 1 11 credit update timeout status mask 0 = no effect on reporting activity 1 = credit update timeout status bit is masked/disabled 0, 1, 8, 9, 10, 11 rws yes 1 12 inch underrun error mask 0 = no effect on reporting activity 1 = inch underrun error bit is masked/disabled 0, 1, 8, 9, 10, 11 rws yes 1 13 ingress memory allocation unit 1-bit soft error counter overflow mask mask for ingress memory allocation unit 1-bit soft error counter overflow bit. 0 = no effect on reporting activity 1 = 1-bit soft error counter overflow is masked/disabled 0, 8 rws yes 1 14 ingress memory allocation unit 2-bit soft error mask mask for ingress memory allocation unit 2-bit soft error bit. 0 = error reporting enab led using interrupts 1 = 2-bit soft error repor ting is masked/disabled 0, 8 rws yes 1 31:15 reserved 0-0h register 11-50. 1d0h error handler 32-bit error mask ( only port 0, factory test only) bit(s) description bit exists only on port(s) type serial eeprom default
february, 2007 error checking and debug registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 241 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: for register offset 1dch, if port 0 is the nt port: this register is loaded from the nt port virtual interface register offset 1dch location in the serial eeprom the serial eeprom must be programmed such that both the port 0 and nt port virtual interface register offset 1dch locations contain the sa me value for this register register 11-51. 1dch debug control (port 0, and also nt port virtual interface if port 0 is the nt port) bit(s) description type serial eeprom default 7:0 factory test only 0-0h 11:8 upstream port number when hardware/software configuration mode control bit = 0, upstream port number ? reads external strap value on the strap_upstrm_portsel[3:0] balls. software is not allowed to change this value. hwinit yes set by strapping ball levels when hardware/software configuration mode control bit = 1, upstream port number is set by software. rw a yes 14:12 reserved 000b 15 hardware/software configuration mode control 0 = upstream and nt port selection by the strap_upstrm_portsel[3:0] and the strap_nt_upstrm_portsel[3:0] balls, which are overridden by the serial eeprom, cannot be ch anged by software at runtime. 1 = upstream and nt port assignment can be changed by software writing new values to the upstream port number [11:8] and nt port number [ 27:24 ] fields, followed by issuance of a ho t reset to the upstream port. the bit 20 ( upstream port hot re set and link down reset propagation disable bit) value must be 0. rw yes 0 0h = port 0 8h = port 8 1h = port 1 9h = port 9 2h to 7h = reserved ah = port 10 bh = port 11 ch to fh = reserved
pex 8524 transparent mode port registers plx technology, inc. 242 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16 upstream hot reset severity control 0 = reset nt port data path when the upstream port receives a hot reset or dl_down condition 1 = do not reset nt port data path wh en the upstream port receives a hot reset or dl_down condition note: in nt mode, a value of 1 is automatically set as default. rw yes 0 17 hot reset serial eeprom load disable serial eeprom load disable only fo r a hot reset or dl_down condition; does not affect fundamental reset. 0 = serial eeprom load enabled upon a hot reset 1 = serial eeprom load disabled upon a hot reset rw yes 0 19:18 mode select mode is selected by strap_mode_sel[1:0] strapping balls, and overridden by the serial eeprom. so ftware is not allowed to change this value. 00b = reserved 01b = nt intelligent adapter mode 10b = nt dual-host mode 11b = transparent mode hwinit yes set by strapping ball levels r/w a yes 20 upstream port hot reset and link down reset propagation disable 0 = internal reset and hot reset propagation are enabled 1 = internal reset and hot reset propagation are disabled set to 1 for nt dual-host mode. rw yes 0 23:21 reserved 000b 27:24 nt port number when bits [19:18] ( mode select field) are set to 01b or 10b and bit 15 ( hardware/software configuration mode control bit) is cleared to 0, the nt port number is set by the strap_nt_upstrm_portsel[3:0] strapping balls. this field is ?don?t care? for t mode . software is not allowed to change this value. hwinit yes set by strapping ball levels when bits [19:18] ( mode select field) are set to 01b or 10b and bit 15 ( hardware/software configuration mode control bit) is set to 1, the nt port number is selected by this field set by software: r/w a yes register 11-51. 1dch debug control (port 0, and also nt port virtual interface ifport0isthentport) (cont.) bit(s) description type serial eeprom default 0h = port 0 8h = port 8 1h = port 1 9h = port 9 2h to 7h = reserved ah = port 10 bh = port 11 ch to fh = reserved
february, 2007 error checking and debug registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 243 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 28 virtual interface access enable used only in nt mode. when the serial eeprom is not pr esent, the default value is 1; otherwise, the default value is 0. 0 = retries type 0 configuration tlp received on nt port virtual interface 1 = accepts type 0 configuration tlp on nt port virtual interface notes: this bit does not affect the pex 8524 in transparent mode. set this bit to enable configuration ac cess to the nt port virtual interface. rw yes 1 29 link interface access enable used only in nt mode. default value is 1 when bits [19:18] ( mode select field) are set to 10b (dual host mode). otherwise, the default value is 0. 0 = retries type 0 configuration tl p received on nt port link interface 1 = accepts type 0 configuratio n tlp on nt port link interface notes: this bit does not affect the pex 8524 in transparent mode. set this bit to enable configuration ac cess to the nt port link interface. rw yes 0 30 on-board serdes lane status control 0 = physical layer lane up status controls on-board pex_lane_good[7:0]# and pex_lane_good[31:16]# outputs 1 = software-driven value to offset 1f4h controls the on-board serdes lane-good output rw yes 0 31 power-up ram bist status reports the power-up ram bist result. 0 = no power-up ram bist error 1 = non-recoverable fatal error detected, must replace pex 8524 device ro no 0 a. although these bits are rw, do not change by software. register 11-51. 1dch debug control (port 0, and also nt port virtual interface if port 0 is the nt port) (cont.) bit(s) description type serial eeprom default
pex 8524 transparent mode port registers plx technology, inc. 244 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-52. 1e0h power management hot plug user configuration (all ports) bit(s) description type serial eeprom default 0 l0s entry idle count time to meet to enter l0s. 0 = idle condition lasts for 1 s 1 = idle condition lasts for 4 s rw yes 0 1 l1 upstream port receiver idle count for active l1 entry. 0 = upstream port receiver idle for 2 s 1 = upstream port receiver idle for 3 s rw yes 0 2 hpc pme turn-off enable 1 = pme turn-off message is transmitted before the port is turned off on a downstream port rw yes 0 4:3 hpc t pepv delay slot power-applied to power-valid delay time. 00b = 16 ms 01b = 32 ms 10b = 64 ms 11b = 128 ms ro yes 00b 5 hpc inband presence detect enable 0 = hp_prsnt[1:0]# or hp_prsnt[11:8]# input balls are used to detect a board present in the slot 1 = serdes receiver detect mechanism is used to detect a board present in the slot ro yes 0 6 hpc t pvperl delay downstream port power-valid to reset signal release time. 0 = 20 ms 1 = 100 ms (default) ro yes 1 12:7 hpc test bits factory test only. testing bits ? must be 000_000b. rw yes 0_0000_0b 31:13 reserved 0-0h
february, 2007 error checking and debug registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 245 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-53. 1e4h egress control and status (all ports) bit(s) description ports type serial eeprom default 0 egress credit u pdate timer enable in this mode, when the port is not receiving credits to make forward progress and the egre ss timeout timer times out, the downstream link is brought down. 0 = egress credit update time r disabled 1 = egress credit update timer enabled 0, 1, 8, 9, 10, 11 rw yes 0 1 egress timeout value 0 = minimum 512 ms (maximum 768 ms) 1 = minimum 1,024 ms (maximum 1,280 ms) 0, 1, 8, 9, 10, 11 rw yes 0 2 dl_down handling 0 = reports unsupported request error for all tlp requests received in dl_down state 1 = reports unsupported request for first posted/ non-posted tlp request in dl_down state ? silently drops subsequent tlp requests 0, 1, 8, 9, 10, 11 rw yes 0 7:3 reserved 0-0h 15:8 link-list ram soft error count link-list ram 8-bit soft e rror counter value. counter shared by: packet link-list ram packet link-list de-allocation ram scheduler data ram counter increments for 1-bit soft errors detected in the ram. 0, 8 ro no 00h 19:16 vc&t encountered timeout 0h = vc0 posted 1h = vc0 non-posted 2h = vc0 completion 3h = vc1 posted 4h = vc1 non-posted 5h = vc1 completion 0, 1, 8, 9, 10, 11 ro yes 0h 23:20 reserved 0h 31:24 packet ram soft error count counter increments for each 1-bit soft error detected in the ram. 0, 8 ro no 00h
pex 8524 transparent mode port registers plx technology, inc. 246 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-54. 1e8h bad tlp count (all ports) bit(s) description type serial eeprom default 7:0 bad tlp count counts the number of tlps with bad lcrc, or number of tlps with a sequence number mi smatch error. the maximum value is ffh. the counter saturates at ffh and does not roll over to 00h. rw yes 00h 31:8 reserved 0000_00h register 11-55. 1ech bad dllp count (all ports) bit(s) description type serial eeprom default 7:0 bad dllp count counts the number of dllps with bad lcrc, or number of dllps with a sequence number mis match error. the maximum value is ffh. the counter saturates at ffh and does not roll over to 00h. rw yes 00h 31:8 reserved 0000_00h register 11-56. 1f0h plx-specific relaxed ordering enable (all ports) bit(s) description type serial eeprom default 19:0 reserved 0h 20 plx-specific relaxed ordering enable silicon revision aa reserved 0 silicon revisions bb/bc enables vc0 completions to pass vc0 posted packets. 0 = vc0 completion tlp blocke d by older vc0 posted tlp 1 = vc0 completion tlp bypasse s the older vc0 posted tlp rw yes 0 31:21 reserved 0h
february, 2007 error checking and debug registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 247 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: for register offset 1f4h, if the following conditions are met: serial eeprom programs port 0 to be the nt port on-board serdes lane status control is set ( 1dch [30]=1) to enable software or serial eeprom control of the pex_lane_good[31:16, 7:0]# outputs the serial eeprom must be programmed such that both port 0 and the nt port virtual interface register offset 1f4h locations contain the same value for this register. register 11-57. 1f4h software-controlled lane status (port 0, and also nt port virtual interface if port 0 is the nt port) bit(s) description type serial eeprom default 7:0 software-controlled lane status echoes the state of the pex_lane_good[7:0]# balls when the debug control register on-board serdes lane status control bit (offset 1dch [30]) is cleared to 0; otherwise, these bits are read-write when the on-board serdes lane status control bit is set to 1. these bits control the se rdes lanes, as follows: bit serdes lane 00 ? 66 77 ro yes 0-0h rw yes 0-0h 15:8 reserved 0-0h 31:16 software-controlled lane status echoes the state of the pex_lane_good[31:16]# balls when the debug control register on-board serdes lane status control bit (offset 1dch[30]) is cleared to 0; otherwise, these bits are read-write when the on-board serdes lane status control bit is set to 1. these bits control the se rdes lanes, as follows: bit serdes lane 16 16 ? 30 30 31 31 ro yes 0-0h rw yes 0-0h
pex 8524 transparent mode port registers plx technology, inc. 248 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-58. 1f8h ack transmission latency limit (all ports) bit(s) description type serial eeprom default 7:0 ack transmission latency limit if the serial eeprom is not present, the va lue of this register changes based upon the negotiated link width after the link is up. this value assumes that maximum payload size is 256 bytes. if the serial eeprom is present, program the serial eeprom to load the value based upon the programmed port width and device control register maximum payload size field value (offset 70h [ 7:5 ]): a. x16 is valid only for station 1. note: the value of this field is valid after link negotiation completes. rw yes ffh 15:8 hpc test bits fac t or y te st on ly. testing bits ? must be 00h. rw yes 00h 31:16 reserved 0000h maximum payload size port width x1 x2 x4 x8 x16 a 128b fah 80h 49h 43h 37h 256b ffh d9h 76h 6bh 64h
february, 2007 physical layer registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 249 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.2 physical layer registers notes: in this section, the term ?serdes quad? or ?quad? re fers to assembling serdes lanes into groups of four contiguous lanes for testing purposes. for port 0, the quads are serdes[0-3] and serdes[4-7]. for port 8, the quads are serdes[16-19], serdes[20- 23], serdes[24-27], and serdes[28-31]. port 0 bits in these registers affect station 0 ports and serdes. port 8 bits in these registers affect station 1 ports and serdes. table 11-14. plx-specific physical layer register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved 200h ? 20ch phy user test pattern 0 210h phy user test pattern 4 214h phy user test pattern 8 218h phy user test pattern 12 21ch physical layer status ph ysical layer command 220h port configuration 224h physical layer test 228h physical layer 22ch physical layer port command 230h skip ordered-set interval 234h quad 0 serdes diagnostic data 238h quad 1 serdes diagnostic data 23ch quad 2 serdes diagnostic data 240h quad 3 serdes diagnostic data 244h serdes nominal drive current select 248h serdes drive current level select 1 24ch serdes drive current level select 2 250h serdes drive equalization level select 1 254h serdes drive equalization level select 2 258h reserved 25ch status data from serial eeprom serial eeprom status serial eeprom control 260h serial eeprom buffer 264h reserved 268h ? 2c4h
pex 8524 transparent mode port registers plx technology, inc. 250 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-59. 210h phy user test pattern 0 (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default 31:0 test pattern 0 test pattern bytes 0-3. used for digital far-end loop-back testing. rw yes 0-0h register 11-60. 214h phy user test pattern 4 (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default 31:0 test pattern 4 test pattern bytes 4-7. used for digital far-end loop-back testing. rw yes 0-0h register 11-61. 218h phy user test pattern 8 (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default 31:0 test pattern 8 test pattern bytes 8-11. used for digital far-end l oop-back testing. rw yes 0-0h register 11-62. 21ch phy user test pattern 12 (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default 31:0 test pattern 12 test pattern bytes 12-15. used for digital far-end loop-back testing. rw yes 0-0h
february, 2007 physical layer registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 251 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-63. 220h physical layer command and status (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default physical layer command 0 port enumerator enable 0 = enumerate not enabled 1 = enumerate enabled hwinit yes 0 1 tdm enable 0 = tdm not enabled 1 = tdm enabled hwinit yes 0 2 reserved 0 3 upstream port as conf iguration master enable 0 = upstream port cross-link not supported 1 = upstream port cross-link supported rw yes 0 4 downstream port as configuration slave enable 0 = downstream port cross-link not supported 1 = downstream port cross-link supported rw yes 0 5 lane reversal disable 0 = lane reversal supported 1 = lane reversal not supported rw yes 0 6 reserved 0 7 fc-init triplet enable silicon revision aa 0 = fc-init1 triplet (p, np, cpl) can be interrupted by idles 1 = fc-init1 triplet (p, np, cpl) must be back-to-back note: logic in silicon revisi ons bb/bc is inverted from silicon revision aa. rw yes 1 fc-init triplet disable silicon revisions bb/bc 0 = fc-init1 triplet (p, np, cpl) must be back-to-back 1 = fc-init1 triplet (p, np, cpl) can be interrupted by idles note: logic in silicon revisi ons bb/bc is inverted from silicon revision aa. rw yes 1 15:8 n_fts value number of fast training sets (n_fts) value to transmit in training sets. rw yes 40h
pex 8524 transparent mode port registers plx technology, inc. 252 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 physical layer status 19:16 reserved 0h 22:20 number of ports enumerated number of ports in current configuration. hwinit yes 000b 23 reserved 0 24 port 0 or 8 deskew buffer error status 1 = deskew buffer overflow or underflow rw1c yes 0 25 port 1 or 9 deskew buffer error status 1 = deskew buffer overflow or underflow rw1c yes 0 26 port 10 deskew buffer error status 1 = deskew buffer overflow or underflow reserved for station 0. rw1c yes 0 27 port 11 deskew buffer error status 1 = deskew buffer overflow or underflow reserved for station 0. rw1c yes 0 31:28 reserved 0h register 11-63. 220h physical layer command and status (only ports 0, 8, and nt port link interface) (cont.) bit(s) description type serial eeprom default
february, 2007 physical layer registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 253 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-64. 224h port configuration (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default 4:0 port configuration the serial eeprom bit values always override the values of the strap_stn0_portcfg[4:0] and strap_stn1_portcfg[3:0] strapping signals (assuming the se rial eeprom values are loaded; refer to table 11-15 ). bits [4:3] must always be programmed to 00b. this register is reset onl y by a fundamental reset ( pex_perst# assertion). the serial eeprom is used to optionall y re-configure the ports from the value set by the strap_stn0_portcfg[4:0] and strap_stn1_portcfg[3:0] inputs, using the values defined in table 11-15 . note: all other configurations default to option 0h. hwinit yes 0_0000b 31:5 reserved 0-0h table 11-15. pex 8524 port configurations configuration value (port 0 or 8, offset 224h[4:0]) lane width per port station 0 station 1 0 1 8 9 10 11 0h x4 x4 x4 x4 x4 x4 1h x16 a a. ports 8 and 9 can be combined to create a 16-lane (x16) port. ??? 2h x8 x8 x8 ? ? 3h x8 x4 x4 ? 4h x8 x4 x2 x2 5h x8 x2 x2 x4 6h x8 x2 x4 x2
pex 8524 transparent mode port registers plx technology, inc. 254 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-65. 228h physical layer test (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default 0 timer test mode enable 0 = normal physical laye r timer parameters used 1 = shortens timer scale fro m milliseconds to microseconds rw yes 0 1 skip-timer test mode enable 0 = disables skip-timer test mode 1 = enables skip-timer test mode rw yes 0 2 port_0_x1 1 = ports 0 and/or 8 are configured as x1 only rw yes 0 3 tcb capture disable 0 = training control bit (t cb) capture is enabled 1 = disables tcb capture rw yes 0 4 analog loop-back enable 0 = pex 8524 enters digital loop-bac k slave mode if an external device sends at least two consecutiv e ts1 ordered-sets that have the loop-back bit exclusively set in the ts1 training control symbol. pex 8524 then loops back data th rough the elastic buffer, 8b/10b decoder, and 8b/10b encoder. 1 = pex 8524 enters analog loop-back slave mode if an external device sends at least two consecutiv e ts1 ordered-sets that have the loop-back bit exclusively set in the ts1 training control symbol. pex 8524 then loops back the symbol stream from the 10-bit receive interface (before the elastic buffer) to the 10-bit transmit interface. rw yes 0 5 port/serdes test pattern enable select 1 = bits [31:28] ( user test pattern enable bits) select ports rather than serdes quads rw yes 0 6 reserved 0 7 serdes bist enable when programmed to 1 by serial eeprom, enables serdes internal loop-back pseudo-random bit se quence (prbs) test for 512 s before starting link initialization. ro yes 0 9:8 prbs diagnostic data select selects the serdes within the quad for prbs generation/checking. port 0 port 8 value station 0 serdes station 1 serdes 00b = [0, 4] [16, 20, 24, 28] 01b = [1, 5] [17, 21, 25, 29] 10b = [2, 6] [18, 22, 26, 30] 11b = [3, 7] [19, 23, 27, 31] rw yes 00b 15:10 reserved 0-0h
february, 2007 physical layer registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 255 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 19:16 prbs enable when set to 1, enables prbs sequence generation/checking on the serdes quads, by station. port 0 port 8 bit station 0 serdes station 1 serdes 16 [0-3] [16-19] 17 [4-7] [20-23] 18 reserved [24-27] 19 reserved [28-31] note: prbs enable and user test pattern enable (bits [ 31:28 ]) are mutually exclusive functions an d must not be enabled together for the same serdes quad. in each station register (ports 0 and 8), the logical result of bits [19:16] anded with bits [31:28] must be 0000b. rw yes 0000b 23:20 prbs external loop-back 0 = serdes quad establishes intern al analog loop-back mode when the corresponding prbs enable bit (bit 19, 18, 17, or 16) is set to 1 1 = serdes quad establishes anal og loop-back master mode when the corresponding prbs enable bit (bit 19, 18, 17, or 16) is set to 1 the following bit commands are valid when the physical layer port command register port x loop-back command bit (port 0 or 8, offset 230h [ 0 , 4 , 8 , and/or 12 ]) is set for the associated port. port 0 port 8 bit station 0 serdes station 1 serdes 20 [0-3] [16-19] 21 [4-7] [20-23] 22 reserved [24-27] 23 reserved [28-31] rw yes 0000b register 11-65. 228h physical layer test (only ports 0, 8, and nt port link interface) (cont.) bit(s) description type serial eeprom default
pex 8524 transparent mode port registers plx technology, inc. 256 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: port 0 parameters apply to serdes[0-3] and serdes[4-7]. port 8 parameters apply to serdes[16-19], serdes[20-23], serdes[24- 27], and serdes[28-31]. 27:24 prbs error count reset when set to 1, resets the prbs error counter ( quad serdes x diagnostic data register prbs error count field). the bits in this field are self-clearing. port 0 port 8 bit station 0 station 1 24 offset 238h [31:24] offset 238h [31:24] 25 offset 23ch [31:24] offset 23ch [31:24] 26 reserved offset 240h [31:24] 27 reserved offset 244h [31:24] ro yes 0000b 31:28 user test pattern enable 0 = disables transmission of the 128-bit test pattern 1 = enables transmission of the 128-bit phy user test pattern [ phy user test pattern x registers (ports 0 and 8, offsets 210h through 21ch )] on the serdes quads in digital far-end loop-back master mode. port 0 port 8 bit station 0 serdes station 1 serdes 28 [0-3] [16-19] 29 [4-7] [20-23] 30 reserved [24-27] 31 reserved [28-31] note: user test pattern enable and prbs enable (bits [ 19:16 ]) are mutually exclusive functions an d must not be enabled together for the same serdes quad. in each station register (ports 0 and 8), the logical result of bits [19:16] anded with bits [31:28] must be 0000b. rw yes 0000b register 11-65. 228h physical layer test (only ports 0, 8, and nt port link interface) (cont.) bit(s) description type serial eeprom default
february, 2007 physical layer registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 257 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-66. 22ch physical layer (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default 5:0 factory test only rw1s yes 00_0000b 7:6 reserved rw1s yes 00b 9:8 serdes quad 0 txtermadjust serdes quad 0 txtermadj[1:0]. control bus to adjust transmit termination values above or below the nominal 50 ohms for physical lanes [0-3]/[16-19]. this allows precise matc hing to compensate for package or board impedanc e mismatch. 00b = sets tx termination to nominal (approximately 50 ohms) 01b = sets tx termination to (nominal -17%) 10b = sets tx termination to (nominal +10%) 11b = sets tx termination to (nominal -15%) rw1s yes 00b 11:10 serdes quad 1 txtermadjust serdes quad 1 txtermadj[1:0]. control bus to adjust transmit termination values above or below the nominal 50 ohms for physical lanes [4-7]/[20-23]. this allows precise matc hing to compensate for package or board impedanc e mismatch. 00b = sets tx termination to nominal (approximately 50 ohms) 01b = sets tx termination to (nominal -17%) 10b = sets tx termination to (nominal +10%) 11b = sets tx termination to (nominal -15%) rw1s yes 00b 13:12 serdes quad 2 txtermadjust serdes quad 2 txtermadj[1:0]. control bus to adjust transmit termination values above or below the nominal 50 ohms for physical lanes [24-27]. this allows prec ise matching to compensate for package or board impedance mismatch. 00b = sets tx termination to nominal (approximately 50 ohms) 01b = sets tx termination to (nominal -17%) 10b = sets tx termination to (nominal +10%) 11b = sets tx termination to (nominal -15%) rw1s yes 00b 15:14 serdes quad 3 txtermadjust serdes quad 3 txtermadj[1:0]. control bus to adjust transmit termination values above or below the nominal 50 ohms for physical lanes [28-31]. this allows prec ise matching to compensate for package or board impedance mismatch. 00b = sets tx termination to nominal (approximately 50 ohms) 01b = sets tx termination to (nominal -17%) 10b = sets tx termination to (nominal +10%) 11b = sets tx termination to (nominal -15%) rw1s yes 00b
pex 8524 transparent mode port registers plx technology, inc. 258 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 17:16 serdes quad 0 rxtermadjust serdes quad 0 rxtermadj[1:0]. control bus to adjust receive termination values above or below the nominal 50 ohms for physical lanes [0-3]/[16-19]. this allows precise matc hing to compensate for package or board impedanc e mismatch. 00b = sets tx termination to nominal (approximately 50 ohms) 01b = sets tx termination to (nominal -17%) 10b = sets tx terminati on to (nominal +10%) 11b = sets tx termination to (nominal -15%) rw1s yes 00b 19:18 serdes quad 1 rxtermadjust serdes quad 1 rxtermadj[1:0]. control bus to adjust receive termination values above or below the nominal 50 ohms for physical lanes [4-7]/[20-23]. this allows precise matc hing to compensate for package or board impedanc e mismatch. 00b = sets tx termination to nominal (approximately 50 ohms) 01b = sets tx termination to (nominal -17%) 10b = sets tx terminati on to (nominal +10%) 11b = sets tx termination to (nominal -15%) rw1s yes 00b 21:20 serdes quad 2 rxtermadjust serdes quad 2 rxtermadj[1:0]. control bus to adjust receive termination values above or below the nominal 50 ohms for physical lanes [24-27]. this allows prec ise matching to compensate for package or board impedance mismatch. 00b = sets tx termination to nominal (approximately 50 ohms) 01b = sets tx termination to (nominal -17%) 10b = sets tx terminati on to (nominal +10%) 11b = sets tx termination to (nominal -15%) rw1s yes 00b 23:22 serdes quad 3 rxtermadjust serdes quad 3 rxtermadj[1:0]. control bus to adjust receive termination values above or below the nominal 50 ohms for physical lanes [28-31]. this allows prec ise matching to compensate for package or board impedance mismatch. 00b = sets tx termination to nominal (approximately 50 ohms) 01b = sets tx termination to (nominal -17%) 10b = sets tx terminati on to (nominal +10%) 11b = sets tx termination to (nominal -15%) rw1s yes 00b register 11-66. 22ch physical layer (only ports 0, 8, and nt port link interface) (cont.) bit(s) description type serial eeprom default
february, 2007 physical layer registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 259 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: port 0 parameters apply to serdes[0-3] and serdes[4-7]. port 8 parameters apply to serdes[16-19], serdes[20-23], serdes[24- 27], and serdes[28-31]. 25:24 serdes quad 0 rxeqctl serdes quad 0 rxeqctl[1:0]. control bus to adjust the receiver equalization, globally for physical lanes [0-3]/[16- 19]. for further details, refer to the expanded description that fo llows this register table. field decode is defined in table 11-16 . rw1s yes 00b 27:26 serdes quad 1 rxeqctl serdes quad 1 rxeqctl[1:0]. control bus to adjust the receiver equalization, globally for physical lanes [4-7]/[20- 23]. for further details, refer to the expanded description that fo llows this register table. field decode is defined in table 11-16 . rw1s yes 00b 29:28 serdes quad 2 rxeqctl serdes quad 2 rxeqctl[1:0].control bus to adjust the receiver equalization, globally fo r physical lanes [24-27] . for further details, refer to the expanded description that fo llows this register table. field decode is defined in table 11-16 . rw1s yes 00b 31:30 serdes quad 3 rxeqctl serdes quad 3 rxeqctl[1:0].control bus to adjust the receiver equalization, globally fo r physical lanes [28-31] . for further details, refer to the expanded description that fo llows this register table. field decode is defined in table 11-16 . rw1s yes 00b register 11-66. 22ch physical layer (only ports 0, 8, and nt port link interface) (cont.) bit(s) description type serial eeprom default
pex 8524 transparent mode port registers plx technology, inc. 260 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 serdes quad x rxeqctl expanded description . at high speeds, the channel between a pci express transmitter and receiver exhibits frequency-dependent losses ( such as due to pcb dielectric and conductor skin-effect). the channel acts as a low-pass filter, attenuat ing the high-frequency components of a signal passing through it. this distortion results in inter symbol interference (isi). isi is a form of deterministic jitter that can easily close the received data ?eye,? re ducing the ability to reliably recover a data stream across the channel. to mitigate the eff ects of isi, the receiver at each lane includes a receive equalizer. the receive equalizer is implemented as a se lectable, high-pass filter at the receiver input pad and is capable of removing as much as 0.4 ui of isi-related jitter. serdes quad x rxeqctl decodes as defined in table 11-16 . the channel length assumes standard fr4 material. the rx equalizer settings should be chosen based on the amount of deterministic jitter induced by the channel. the channel lengths listed in the table above are included as a general guideline, not as an absolute reference. deterministic jitter as a function of channel length can vary with pcb layer stackup, pcb material, and the type of connector(s) used. table 11-16. rxeqctl[1:0] decode for register offset 224h[31:24] rxeqctl[1:0] rx eq setting input jitter channel length 00b maximum rx eq 0.25 ui 50.8 cm (20 inches) and two or more connectors 01b minimum rx eq between 0.1 and 0.25 ui between 20.32 and 50.8 cm (8 and 20 inches) and up to two connectors 10b, 11b rx eq off < 0.1 ui 20.32 cm (8 inches) or less, up to one connector
february, 2007 physical layer registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 261 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-67. 230h physical layer port command (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default 0 port 0 or 8 loop-back command 0 = port 0 or 8 is not enabled to go to loop-back master state 1 = port 0 or 8 is enabled to go to loop-back master state rw yes 0 1 port 0 or 8 scrambler disable if serial eeprom load sets this bit, scrambler is disabled in configuration-complete state. if software sets this bit when the link is in the up state, hardware immediately disabl es its scrambler withou t executing link training protocol. the upstream/downstre am device scra mbler will not be disabled. 0 = port 0 or 8 scrambler is enabled 1 = port 0 or 8 scrambler is disabled rw yes 0 2 port 0 or 8 rx l1 only port 0 or 8 receiver enters to aspm l1. 0 = port 0 or 8 receiver is allowe d to go to aspm l0s or l1 state when it detects electrical idle ordered-set in l0 state 1 = port 0 or 8 receiver is allowed to go to aspm l1 only when it detects electrical idle ordered-set in l0 state rw yes 0 3 port 0 or 8 ready as loop-back master port 0 or 8 ltssm establis hed loop-back as a master. 0 = port 0 or 8 is not in loop-back master mode 1 = port 0 or 8 is in loop-back master mode ro no 0 4 port 1 or 9 loop-back command 0 = port 1 or 9 is not enabled to go to loop-back master state 1 = port 1 or 9 is enabled to go to loop-back master state rw yes 0 5 port 1 or 9 scrambler disable if serial eeprom load sets this bit, scrambler is disabled in configuration-complete state. if software sets this bit when the link is in the up state, hardware immediately disabl es its scrambler withou t executing link training protocol. the upstream/downstream de vice scrambler is not disabled. 0 = port 1 or 9 scrambler is enabled 1 = port 1 or 9 scrambler is disabled rw yes 0 6 port 1 or 9 rx l1 only port 1 or 9 receiver enters to aspm l1. 0 = port 1 or 9 receiver is allowe d to go to aspm l0s or l1 state when it detects electrical idle ordered-set in l0 state 1 = port 1 or 9 receiver is allowed to go to aspm l1 only when it detects electrical idle ordered-set in l0 state rw yes 0 7 port 1 or 9 ready as loop-back master port 1 or 9 ltssm establis hed loop-back as a master. 0 = port 1 or 9 is not in loop-back master mode 1 = port 1 or 9 is in loop-back master mode ro no 0
pex 8524 transparent mode port registers plx technology, inc. 262 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8 port 10 loop-back command 0 = port 10 is not enabled to go to loop-back master state 1 = port 10 is enabled to go to loop-back master state reserved for station 0. rw yes 0 9 port 10 scramble disable if serial eeprom load sets this bit, scrambler is disabled in configuration-complete state. reserved for station 0. if software sets this bit when the link is in the up state, hardware immediately disabl es its scrambler withou t executing link training protocol. the upstream/downstream de vice scrambler is not disabled. 0 = port 10 scrambler is enabled 1 = port 10 scrambler is disabled rw yes 0 10 port 10 rx l1 only port 10 receiver enters to aspm l1. reserved for station 0. 0 = port 10 receiver is allowed to go to aspm l0s or l1 state when it detects electrical idle ordered-set in l0 state 1 = port 10 receiver is allowed to go to aspm l1 only when it detects electrical idle ordered-set in l0 state rw yes 0 11 port 10 ready as loop-back master port 10 ltssm established loop-back as a master. reserved for station 0. 0 = port 10 is not in loop-back master mode 1 = port 10 is in loop-back master mode ro no 0 12 port 11 loop-back command 0 = port 11 is not enabled to go to loop-back master state 1 = port 11 is enabled to go to loop-back master state reserved for station 0. rw yes 0 13 port 11 scramble disable if serial eeprom load sets this bit, scrambler is disabled in configuration-complete state. reserved for station 0. if software sets this bit when the link is in the up state, hardware immediately disabl es its scrambler withou t executing link training protocol. the upstream/downstream de vice scrambler is not disabled. 0 = port 11 scrambler is enabled 1 = port 11 scrambler is disabled rw yes 0 14 port 11 rx l1 only port 11 receiver enters to aspm l1. reserved for station 0. 0 = port 11 receiver is allowed to go to aspm l0s or l1 state when it detects electrical idle ordered-set in l0 state 1 = port 11 receiver is allowed to go to aspm l1 only when it detects electrical idle ordered-set in l0 state rw yes 0 15 port 11 ready as loop-back master port 11 ltssm established loop-back as a master. reserved for station 0. 0 = port 11 is not in loop-back master mode 1 = port 11 is in loop-back master mode ro no 0 31:16 reserved 0-0h register 11-67. 230h physical layer port command (only ports 0, 8, and nt port link interface) (cont.) bit(s) description type serial eeprom default
february, 2007 physical layer registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 263 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: port 0 parameters apply to serdes[0-3]. port 8 parameters apply to serdes[16-19]. note: port 0 parameters apply to serdes[4-7]. port 8 parameters apply to serdes[20-23]. register 11-68. 234h skip ordered-set interval (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default 11:0 skip ordered-set interval skip ordered-set interval, in symbol times. 49ch = minimum interval (1,180 symbol times) 602h = maximum interval (1,538 symbol times) rws yes 49ch 31:12 reserved 0000_0h register 11-69. 238h quad 0 serdes diagnostic data (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default 9:0 expected prbs data expected prbs serdes[0-3 ]/[16-19] diagnostic data. ro yes 00h 19:10 received prbs data received prbs serdes[0-3]/[16-19] diagnostic data. ro yes 00h 23:20 reserved 0h 31:24 prbs error count prbs serdes[0-3]/[16-19] error count (0 to 255). ro yes 00h register 11-70. 23ch quad 1 serdes diagnostic data only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default 9:0 expected prbs data expected prbs serdes[4-7 ]/[20-23] diagnostic data. ro yes 00h 19:10 received prbs data received prbs serdes[4-7 ]/[20-23] diagnostic data. ro yes 00h 23:20 reserved 0h 31:24 prbs error count prbs serdes[4-7]/[20-23] error count (0 to 255). ro yes 00h
pex 8524 transparent mode port registers plx technology, inc. 264 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: this register is reserved for port 0. port 8 parameters apply to serdes[24-27]. note: this register is reserved for port 0. port 8 parameters apply to serdes[28-31]. register 11-71. 240h quad 2 serdes diagnostic data (only port 8 and nt port link interface) bit(s) description type serial eeprom default 9:0 expected prbs data expected prbs serdes[2 4-27] diagnostic data. ro yes 00h 19:10 received prbs data received prbs serdes[24-27] diagnostic data. ro yes 00h 23:20 reserved 0h 31:24 prbs error count prbs serdes[24-27] error count (0-255). ro yes 00h register 11-72. 244h quad 3 serdes diagnostic data (only port 8 and nt port link interface) bit(s) description type serial eeprom default 9:0 expected prbs data expected prbs serdes[ 28-31] diagnostic data. ro yes 00h 19:10 received prbs data received prbs serdes[ 28-31] diagnostic data. ro yes 00h 23:20 reserved 0h 31:24 prbs error count prbs serdes[28-31] error count (0 to 255). ro yes 00h
february, 2007 physical layer registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 265 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: port 0 parameters apply to serdes[0-3] (bits [7:0]) and serdes[4-7] (bits [15:8]); bits [31:16] are reserved . port 8 parameters apply to serdes[16-19], serde s[20-23], serdes[24-27], and serdes[28-31]. note: port 0 parameters apply to serdes[0-7]. port 8 parameters apply to serdes[16-23]. register 11-73. 248h serdes nominal drive current select (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default 1:0 serdes_0/serdes_16 nominal drive current the following values for nominal current apply to each drive: 00b = 20 ma 01b = 10 ma 10b = 28 ma 11b = 20 ma rws yes 00b 3:2 serdes_1/serdes_17 nominal drive current rws yes 00b 5:4 serdes_2/serdes_18 nominal drive current rws yes 00b 7:6 serdes_3/serdes_19 nominal drive current rws yes 00b 9:8 serdes_4/serdes_20 nominal drive current rws yes 00b 11:10 serdes_5/serdes_21 nominal drive current rws yes 00b 13:12 serdes_6/serdes_22 nominal drive current rws yes 00b 15:14 serdes_7/serdes_23 nominal drive current rws yes 00b 17:16 serdes_24 nominal drive current rws yes 00b 19:18 serdes_25 nominal drive current rws yes 00b 21:20 serdes_26 nominal drive current rws yes 00b 23:22 serdes_27 nominal drive current rws yes 00b 25:24 serdes_28 nominal drive current rws yes 00b 27:26 serdes_29 nominal drive current rws yes 00b 29:28 serdes_30 nominal drive current rws yes 00b 31:30 serdes_31 nominal drive current rws yes 00b register 11-74. 24ch serdes drive current level select 1 (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default 3:0 serdes_0/serdes_16 dr ive current level the following values represent the ratio of actual current/ nominal current (selected in the serdes nominal drive current select register) and apply to each drive: rws yes 0h 7:4 serdes_1/serdes_17 dr ive current level rws yes 0h 11:8 serdes_2/serdes_18 dr ive current level rws yes 0h 15:12 serdes_3/serdes_19 dr ive current level rws yes 0h 19:16 serdes_4/serdes_20 dr ive current level rws yes 0h 23:20 serdes_5/serdes_21 dr ive current level rws yes 0h 27:24 serdes_6/serdes_22 dr ive current level rws yes 0h 31:28 serdes_7/serdes_23 dr ive current level rws yes 0h 0h = 1.00 1h = 1.05 2h = 1.10 3h = 1.15 4h = 1.20 5h = 1.25 6h = 1.30 7h = 1.35 8h = 0.60 9h = 0.65 ah = 0.70 bh = 0.75 ch = 0.80 dh = 0.85 eh = 0.90 fh = 0.95
pex 8524 transparent mode port registers plx technology, inc. 266 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: this register is reserved for port 0. port 8 parameters apply to serdes[24-31]. note: port 0 parameters apply to serdes[0-7]. port 8 parameters apply to serdes[16-23]. register 11-75. 250h serdes drive current level select 2 (only port 8 and nt port link interface) bit(s) description type serial eeprom default 3:0 serdes_24 drive current level the following values represent the ratio of actual current/nominal current (selected in serdes nominal drive current select register) and apply to each drive: rws yes 0h 7:4 serdes_25 drive current level rws yes 0h 11:8 serdes_26 drive current level rws yes 0h 15:12 serdes_27 drive current level rws yes 0h 19:16 serdes_28 drive current level rws yes 0h 23:20 serdes_29 drive current level rws yes 0h 27:24 serdes_30 drive current level rws yes 0h 31:28 serdes_31 drive current level rws yes 0h register 11-76. 254h serdes drive equalization level select 1 (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default 3:0 serdes_0/serdes_16 drive equalization level the following values represent the percentage of drive current attributable to equalization curre nt and apply to each drive: rws yes 8h 7:4 serdes_1/serdes_17 drive equalization level rws yes 8h 11:8 serdes_2/serdes_18 drive equalization level rws yes 8h 15:12 serdes_3/serdes_19 drive equalization level rws yes 8h 19:16 serdes_4/serdes_20 drive equalization level rws yes 8h 23:20 serdes_5/serdes_21 drive equalization level rws yes 8h 27:24 serdes_6/serdes_22 drive equalization level rws yes 8h 31:28 serdes_7/serdes_23 drive equalization level rws yes 8h 0h = 1.00 1h = 1.05 2h = 1.10 3h = 1.15 4h = 1.20 5h = 1.25 6h = 1.30 7h = 1.35 8h = 0.60 9h = 0.65 ah = 0.70 bh = 0.75 ch = 0.80 dh = 0.85 eh = 0.90 fh = 0.95 i eq / i dr de-emphasis (db) 0h = 0.00 1h = 0.04 2h = 0.08 3h = 0.12 4h = 0.16 5h = 0.20 6h = 0.24 7h = 0.28 8h = 0.32 9h = 0.36 ah = 0.40 bh = 0.44 ch = 0.48 dh = 0.52 eh = 0.56 fh = 0.60 0.00 -0.35 -0.72 -1.11 -1.51 -1.94 -2.38 -2.85 -3.35 -3.88 -4.44 -5.04 -5.68 -6.38 -7.13 -7.96
february, 2007 physical layer registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 267 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: this register is reserved for port 0. port 8 parameters apply to serdes[24-31]. register 11-77. 258h serdes drive equalization level select 2 (only port 8 and nt port link interface) bit(s) description type serial eeprom default 3:0 serdes_24 drive equalization level the following values represent the percentage of drive current attributable to equalization current and apply to each drive: rws yes 8h 7:4 serdes_25 drive equalization level rws yes 8h 11:8 serdes_26 drive equalization level rws yes 8h 15:12 serdes_27 drive equalization level rws yes 8h 19:16 serdes_28 drive equalization level rws yes 8h 23:20 serdes_29 drive equalization level rws yes 8h 27:24 serdes_30 drive equalization level rws yes 8h 31:28 serdes_31 drive equalization level rws yes 8h i eq / i dr de-emphasis (db) 0h = 0.00 1h = 0.04 2h = 0.08 3h = 0.12 4h = 0.16 5h = 0.20 6h = 0.24 7h = 0.28 8h = 0.32 9h = 0.36 ah = 0.40 bh = 0.44 ch = 0.48 dh = 0.52 eh = 0.56 fh = 0.60 0.00 -0.35 -0.72 -1.11 -1.51 -1.94 -2.38 -2.85 -3.35 -3.88 -4.44 -5.04 -5.68 -6.38 -7.13 -7.96
pex 8524 transparent mode port registers plx technology, inc. 268 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-78. 260h serial eeprom status and control (only port 0) bit(s) description type serial eeprom default serial eeprom control 12:0 serial eeprom block address serial eeprom block address for 32 kb. rw yes 0000h 15:13 serial eeprom command commands to the serial eeprom controller. 001b = data from serial eeprom st atus[31:24] bits written to the serial eeprom internal status register 010b = write four bytes of data from the serial eeprom buffer into the memory location pointed to by the serial eeprom block address field 011b = read four bytes of data from the memory location pointed to by the serial eeprom block address field into the serial eeprom buffer 100b = reset write enable latch 101b = data from serial ee prom internal status re gister written to the serial eeprom status[31:24] bits 110b = set write enable latch all other values are reserved . note: for value of 001b, only bits [31, 27:26] can be written into the serial eeprom?s internal status register. rw yes 000b serial eeprom status 17:16 serial eeprom present serial eeprom present status, unless bit 21 ( crc disable bit) is set to ignore crc checking (not recommended) . 00b = not present 01b = serial eeprom present ? no crc error 10b = reserved 11b = serial eeprom present, but with crc error ? unless bit 21 ( crc disable bit) is set to ignore crc checking (not recommended) ro yes 00b 19:18 serial eeprom command status 00b = serial eeprom command complete 01b = serial eeprom command not complete 10b = serial eeprom command complete with crc error 11b = reserved ro yes 00b 20 serial eeprom block address upper bit serial eeprom block address upper bit 13. extends serial eeprom to 64 kb. rw yes 0 21 crc disable 0 = serial eeprom input data uses crc 1 = serial eeprom i nput data crc disabled (not recommended) rw yes 0 23:22 reserved 00b
february, 2007 physical layer registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 269 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: within the serial eeprom?s status register, only bits [31, 27:26] can be written. status data from serial eeprom 24 serial eeprom_rdy# 0 = serial eeprom ready to transmit data 1 = write cycle in progress rw yes 0 25 serial eeprom_wen 0 = serial eeprom write disabled 1 = serial eeprom write enabled rw yes 0 27:26 serial eeprom_bp[1:0] serial eeprom block-write protect bits. rw yes 00b 30:28 serial eeprom write status value is 000b when serial eeprom is not in an internal write cycle. note: definition of this field varies am ong serial eeprom manufacturers. reads of the serial eeprom internal status register can return 000b or 111b, depending on the serial eeprom that is used. ro yes 000b 31 serial eeprom_wpen serial eeprom write protect enable. when: = 0 and serial eeprom_wen = 1, the serial eeprom status register is writable. = 1, serial eeprom status register is protected. note: this bit is not implemented in certain seri al eeproms. refer to the serial eeprom manuf acturer?s data sheet. rw yes 0 register 11-79. 264h serial eeprom buffer (only port 0) bit(s) description type serial eeprom default 31:0 serial eeprom buffer rw yes 0-0h register 11-78. 260h serial eeprom status and control (only port 0) (cont.) bit(s) description type serial eeprom default bp[1:0] level array addresses protected 16-kb device 32-kb device 64-kb device 00b 0 none none none 01b 1 (top 1/4) 3000h - 3fffh 6000h - 7fffh ? 10b 2 (top 1/2) 2000h - 3fffh 4000h - 7fffh ? 11b 3 (all) 0000h - 3fffh 0000h - 7fffh ?
pex 8524 transparent mode port registers plx technology, inc. 270 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.3 cam routing registers the cam routing registers contain mirror copies of the registers used for: bus number cam (content-addressable memory) ? used to determine configuration tlp completion route these registers contain mirror copies of the primary bus number , secondary bus number and subordinate bus number registers of each pex 8524 port. i/o cam ? used to determine i/o request routing these registers contain mirror copies of the i/o base and i/o limit registers of each pex 8524 port. amcam (address-mapping cam) ? used to determine memory request route these registers contain mirror copies of the memory base and limit address . prefetchable memory base and limit address , prefetchable memory upper base address[63:32] , and prefetchable memory uppe r limit address[63:32] register of each pex 8524 port. note: these registers are automatically updated by hardware. modifying these registers by writing to the addresses listed here is not recommended. table 11-17. plx-specific cam routing register map (only ports 0 and 8) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved bus number cam 0 2c8h reserved bus number cam 1 2cch reserved 2d0h ? 2e4h reserved bus number cam 8 2e8h reserved bus number cam 9 2ech reserved bus number cam 10 2f0h reserved bus number cam 11 2f4h reserved 2f8h ? 304h i/o cam_1 i/o cam_0 308h reserved 30ch ? 314h i/o cam_9 i/o cam_8 318h i/o cam_11 i/o cam_10 31ch reserved 320h ? 344h amcam_0 memory limit and base 348h amcam_0 prefetchable memo ry limit and base[31:0] 34ch amcam_0 prefetchable memory base[63:32] 350h amcam_0 prefetchable memory limit[63:32] 354h amcam_1 memory limit and base 358h amcam_1 prefetchable memo ry limit and base[31:0] 35ch amcam_1 prefetchable memory base[63:32] 360h amcam_1 prefetchable memory limit[63:32] 364h reserved 368h ? 3c4h
february, 2007 cam routing registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 271 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 amcam_8 memory limit and base 3c8h amcam_8 prefetchable memory limit and base[31:0] 3cch amcam_8 prefetchable memory base[63:32] 3d0h amcam_8 prefetchable memory limit[63:32] 3d4h amcam_9 memory limit and base 3d8h amcam_9 prefetchable memory limit and base[31:0] 3dch amcam_9 prefetchable memory base[63:32] 3e0h amcam_9 prefetchable memory limit[63:32] 3e4h amcam_10 memory limit and base 3e8h amcam_10 prefetchable limit and memory base[31:0] 3ech amcam_10 prefetchable memory base[63:32] 3f0h amcam_10 prefetchable memory limit[63:32] 3f4h amcam_11 memory limit and base 3f8h amcam_11 prefetchable limit and memory base[31:0] 3fch amcam_11 prefetchable memory base[63:32] 400h amcam_11 prefetchable memory limit[63:32] 404h reserved 408h ? 65ch ingress control 660h reserved 664h ingress port enable 668h reserved 66ch ? 67ch i/ocam_0 upper port 0 680h i/ocam_1 upper port 1 684h reserved 688h ? 69ch i/ocam_8 upper port 8 6a0h i/ocam_9 upper port 9 6a4h i/ocam_10 upper port 10 6a8h i/ocam_11 upper port 11 6ach reserved 6b0h ? 6bch table 11-17. plx-specific cam routing register map (only ports 0 and 8) (cont.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210
pex 8524 transparent mode port registers plx technology, inc. 272 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.3.1 bus number cam registers register 11-80. 2c8h bus number cam 0 (only ports 0 and 8) bit(s) description type serial eeprom default 7:0 primary bus number mirror copy of port 0 primary bus number . rw yes 00h 15:8 secondary bus number mirror copy of port 0 secondary bus number. rw yes ffh 23:16 subordinate bus number mirror copy of port 0 subordinate bus number. rw yes 00h 31:24 reserved 00h register 11-81. 2cch bus number cam 1 (only ports 0 and 8) bit(s) description type serial eeprom default 7:0 primary bus number mirror copy of port 1 primary bus number. rw yes 00h 15:8 secondary bus number mirror copy of port 1 secondary bus number. rw yes ffh 23:16 subordinate bus number mirror copy of port 1 subordinate bus number. rw yes 00h 31:24 reserved 00h
february, 2007 cam routing registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 273 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-82. 2e8h bus number cam 8 (only ports 0 and 8) bit(s) description type serial eeprom default 7:0 primary bus number mirror copy of port 8 primary bus number. rw yes 00h 15:8 secondary bus number mirror copy of port 8 secondary bus number. rw yes ffh 23:16 subordinate bus number mirror copy of port 8 subordinate bus number. rw yes 00h 31:24 reserved 00h register 11-83. 2ech bus number cam 9 (only ports 0 and 8) bit(s) description type serial eeprom default 7:0 primary bus number mirror copy of port 9 primary bus number. rw yes 00h 15:8 secondary bus number mirror copy of port 9 secondary bus number. rw yes ffh 23:16 subordinate bus number mirror copy of port 9 subordinate bus number. rw yes 00h 31:24 reserved 00h register 11-84. 2f0h bus number cam 10 (only ports 0 and 8) bit(s) description type serial eeprom default 7:0 primary bus number mirror copy of port 10 primary bus number. rw yes 00h 15:8 secondary bus number mirror copy of port 10 secondary bus number. rw yes ffh 23:16 subordinate bus number mirror copy of port 10 subordinate bus number. rw yes 00h 31:24 reserved 00h register 11-85. 2f4h bus number cam 11 (only ports 0 and 8) bit(s) description type serial eeprom default 7:0 primary bus number mirror copy of port 11 primary bus number. rw yes 00h 15:8 secondary bus number mirror copy of port 11 secondary bus number. rw yes ffh 23:16 subordinate bus number mirror copy of port 11 subordinate bus number. rw yes 00h 31:24 reserved 00h
pex 8524 transparent mode port registers plx technology, inc. 274 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.3.2 i/o cam registers register 11-86. 308h i/o cam_0 (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 i/o addressing capability 0h = 16-bit i/o addressing 1h = 32-bit i/o addressing ro yes 1h 7:4 i/o base mirror copy of port 0 i/o base value. rw yes fh 11:8 i/o addressing capability 0h = 16-bit i/o addressing 1h = 32-bit i/o addressing ro yes 1h 15:12 i/o limit mirror copy of port 0 i/o limit value. rw yes 0h register 11-87. 30ah i/o cam_1 (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 i/o addressing capability 0h = 16-bit i/o addressing 1h = 32-bit i/o addressing ro yes 1h 7:4 i/o base mirror copy of port 1 i/o base value. rw yes fh 11:8 i/o addressing capability 0h = 16-bit i/o addressing 1h = 32-bit i/o addressing ro yes 1h 15:12 i/o limit mirror copy of port 1 i/o limit value. rw yes 0h
february, 2007 cam routing registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 275 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-88. 318h i/o cam_8 (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 i/o addressing capability 0h = 16-bit i/o addressing 1h = 32-bit i/o addressing ro yes 1h 7:4 i/o base mirror copy of port 8 i/o base value. rw yes 0h 11:8 i/o addressing capability 0h = 16-bit i/o addressing 1h = 32-bit i/o addressing ro yes 1h 15:12 i/o limit mirror copy of port 8 i/o limit value. rw yes 0h register 11-89. 31ah i/o cam_9 (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 i/o addressing capability 0h = 16-bit i/o addressing 1h = 32-bit i/o addressing ro yes 1h 7:4 i/o base mirror copy of port 9 i/o base value. rw yes fh 11:8 i/o addressing capability 0h = 16-bit i/o addressing 1h = 32-bit i/o addressing ro yes 1h 15:12 i/o limit mirror copy of port 9 i/o limit value. rw yes 0h
pex 8524 transparent mode port registers plx technology, inc. 276 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-90. 31ch i/o cam_10 (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 i/o addressing capability 0h = 16-bit i/o addressing 1h = 32-bit i/o addressing ro yes 1h 7:4 i/o base mirror copy of port 10 i/o base value. rw yes fh 11:8 i/o addressing capability 0h = 16-bit i/o addressing 1h = 32-bit i/o addressing ro yes 1h 15:12 i/o limit mirror copy of port 10 i/o limit value. rw yes 0h register 11-91. 31eh i/o cam_11 (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 i/o addressing capability 0h = 16-bit i/o addressing 1h = 32-bit i/o addressing ro yes 1h 7:4 i/o base mirror copy of port 11 i/o base value. rw yes fh 11:8 i/o addressing capability 0h = 16-bit i/o addressing 1h = 32-bit i/o addressing ro yes 1h 15:12 i/o limit mirror copy of port 11 i/o limit value. rw yes 0h
february, 2007 cam routing registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 277 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.3.3 amcam (address- mapping cam) registers amcam registers contain mirror copies of the memory base and limit address . prefetchable memory base and limit address , prefetchable memory up per base address[63:32] , and prefetchable memory uppe r limit address[63:32] registers of each pex 8524 port. register 11-92. 348h amcam_0 memory limit and base (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 reserved 0h 15:4 memory base mirror copy of port 0 memory base value. rw yes fffh 19:16 reserved 0h 31:20 memory limit mirror copy of port 0 memory limit value. rw yes 000h register 11-93. 34ch amcam_0 prefetchable memory limit and base[31:0] (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 addressing support 0h = 32-bit addressing supported 1h = 64-bit addressing supported ro yes 1h 15:4 prefetchable memory base amcam_0 port 0 prefetchable memory base[31:20]. rw yes fffh 19:16 addressing support 0h = 32-bit addressing supported 1h = 64-bit addressing supported ro yes 1h 31:20 prefetchable memory limit amcam_0 port 0 prefetchable memory limit[31:20]. rw yes 000h register 11-94. 350h amcam_0 prefetchable memory base[63:32] (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 prefetchable memory base[63:32] amcam_0 port 0 prefetchable memory base[63:32]. rw yes ffff_ffffh register 11-95. 354h amcam_0 prefetchable memory limit[63:32] (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 prefetchable memory limit[63:32] amcam_0 port 0 prefetchab le memory limit[63:32]. rw yes 0-0h
pex 8524 transparent mode port registers plx technology, inc. 278 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-96. 358h amcam_1 memory limit and base (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 reserved 0h 15:4 memory base mirror copy of port 1 memory base value. rw yes fffh 19:16 reserved 0h 31:20 memory limit mirror copy of port 1 memory limit value. rw yes 000h register 11-97. 35ch amcam_1 prefetchable memory limit and base[31:0] (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 addressing support 0h = 32-bit addressing supported 1h = 64-bit addressing supported ro yes 1h 15:4 prefetchable memory base amcam_1 port 1 prefetchable memory base[31:20]. rw yes fffh 19:16 addressing support 0h = 32-bit addressing supported 1h = 64-bit addressing supported ro yes 1h 31:20 prefetchable memory limit amcam_1 port 1 prefetchab le memory limit[31:20]. rw yes 000h register 11-98. 360h amcam_1 prefetchable memory base[63:32] (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 prefetchable memory base[63:32] amcam_1 port 1 prefetchable memory base[63:32]. rw yes ffff_ffffh register 11-99. 364h amcam_1 prefetchable memory limit[63:32] (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 prefetchable memory limit[63:32] amcam_1 port 1 prefetchab le memory limit[63:32]. rw yes 0-0h
february, 2007 cam routing registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 279 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-100. 3c8h amcam_8 memory limit and base (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 reserved 0h 15:4 memory base mirror copy of port 8 memory base value. rw yes fffh 19:16 reserved 0h 31:20 memory limit mirror copy of port 8 memory limit value. rw yes 000h register 11-101. 3cch amcam_8 prefetchable memory limit and base[31:0] (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 addressing support 0h = 32-bit addressing supported 1h = 64-bit addressing supported ro yes 1h 15:4 prefetchable memory base amcam_8 port 8 prefetchab le memory base[31:20]. rw yes fffh 19:16 addressing support 0h = 32-bit addressing supported 1h = 64-bit addressing supported ro yes 1h 31:20 prefetchable memory limit amcam_8 port 8 prefetchable memory limit[31:20]. rw yes 000h register 11-102. 3d0h amcam_8 prefetchable memory base[63:32] (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 prefetchable memory base[63:32] amcam_8 port 8 prefetchab le memory base[63:32]. rw yes ffff_ffffh register 11-103. 3d4h amcam_8 prefetchable memory limit[63:32] (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 prefetchable memory limit[63:32] amcam_8 port 8 prefetchable memory limit[63:32]. rw yes 0-0h
pex 8524 transparent mode port registers plx technology, inc. 280 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-104. 3d8h amcam_9 memory limit and base (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 reserved 0h 15:4 memory base mirror copy of port 9 memory base value. rw yes fffh 19:16 reserved 0h 31:20 memory limit mirror copy of port 9 memory limit value. rw yes 000h register 11-105. 3dch amcam_9 prefetchable memory limit and base[31:0] (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 addressing support 0h = 32-bit addressing supported 1h = 64-bit addressing supported ro yes 1h 15:4 prefetchable memory base amcam_9 port 9 prefetchable memory base[31:20]. rw yes fffh 19:16 addressing support 0h = 32-bit addressing supported 1h = 64-bit addressing supported ro yes 1h 31:20 prefetchable memory limit amcam_9 port 9 prefetchable memory limit[31:20]. rw yes 000h register 11-106. 3e0h amcam_9 prefetchable memory base[63:32] (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 prefetchable memory base[63:32] amcam_9 port 9 prefetchable memory base[63:32]. rw yes ffff_ffffh register 11-107. 3e4h amcam_9 prefetchable memory limit[63:32] (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 prefetchable memory limit[63:32] amcam_9 port 9 prefetchable memory limit[63:32]. rw yes 0-0h
february, 2007 cam routing registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 281 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-108. 3e8h amcam_10 memory limit and base (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 reserved 0h 15:4 memory base mirror copy of port 10 memory base value. rw yes fffh 19:16 reserved 0h 31:20 memory limit mirror copy of port 10 memory limit value. rw yes 000h register 11-109. 3ech amcam_10 prefetchable limit and memory base[31:0] (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 addressing support 0h = 32-bit addressing supported 1h = 64-bit addressing supported ro yes 1h 15:4 prefetchable memory base amcam_10 port 10 prefetchab le memory base[31:20]. rw yes fffh 19:16 addressing support 0h = 32-bit addressing supported 1h = 64-bit addressing supported ro yes 1h 31:20 prefetchable memory limit amcam_10 port 10 prefetchab le memory limit[31:20]. rw yes 000h register 11-110. 3f0h amcam_10 prefetchable memory base[63:32] (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 prefetchable memory base[63:32] amcam_10 port 10 prefetchab le memory base[63:32]. rw yes ffff_ffffh register 11-111. 3f4h amcam_10 prefetchable memory limit[63:32] (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 prefetchable memory limit[63:32] amcam_10 port 10 prefetchab le memory limit[63:32]. rw yes 0-0h
pex 8524 transparent mode port registers plx technology, inc. 282 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-112. 3f8h amcam_11 memory limit and base (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 reserved 0h 15:4 memory base mirror copy of port 11 memory base value. rw yes fffh 19:16 reserved 0h 31:20 memory limit mirror copy of port 11 memory limit value. rw yes 000h register 11-113. 3fch amcam_11 prefetchable limit and memory base[31:0] (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 addressing support 0h = 32-bit addressing supported 1h = 64-bit addressing supported ro yes 1h 15:4 prefetchable memory base amcam_11 port 11 prefetchable memory base[31:20]. rw yes fffh 19:16 addressing support 0h = 32-bit addressing supported 1h = 64-bit addressing supported ro yes 1h 31:20 prefetchable memory limit amcam_11 port 11 prefetchab le memory limit[31:20]. rw yes 000h register 11-114. 400h amcam_11 prefetchable memory base[63:32] (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 prefetchable memory base[63:32] amcam_11 port 11 prefetchable memory base[63:32]. rw yes ffff_ffffh register 11-115. 404h amcam_11 prefetchable memory limit[63:32] (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 prefetchable memory limit[63:32] amcam_11 port 11 prefetchable memory limit[63:32]. rw yes 0-0h
february, 2007 ingress control registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 283 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.4 ingress control registers table 11-18. plx-specific ingress control register map (only ports 0 and 8) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ingress control 660h reserved 664h ingress port enable 668h register 11-116. 660h ingress control (only ports 0 and 8) bit(s) description type serial eeprom default 0 enable csr access by downstream devices silicon revision aa enables acceptance of conf iguration requests from a reque ster that is downstream from a transparent port, targeting any downstream transparent port?s type 1 header registers or nt po rt virtual interface type 0 header registers ( such as for peer configuration access). 0 = configuration requests from a downstre am device that ar e targeting pex 8524 registers are not supported ; the downstream port flags an uncorrectable error, and, returns a completion with unsupported request (ur) specified in the completion status field, to the downstream requester. only this mode is pci express base r1.0a -compliant. 1 = the following types of configurat ion requests from downstream requesters are allowed: type 0 requests targeting the type 1 head er registers in that downstream port type 1 requests targeting the type 1 he ader registers in other downstream transparent ports, and type 1 requests targeting the type 0 header registers in the nt port virtual interface the upstream port registers are not accessible from the downstream port. silicon revisions bb/bc enables acceptance of both configuratio n and memory requests from a requester that is downstream from a transparent port, targeting any pex 8524 registers. 0 = configuration requests from a downstream device are not supported ; the downstream port flags an uncorrectab le error, and, returns a completion with unsupported request (ur) specified in the completion status field, to the downstream request er. only this mode is pci express base r1.0a -compliant. 1 = configuration and memory requests from downstream requesters, targeting any pex 8524 registers in any port, are allowed. note: this bit can be initially set only th rough the upstream port, the nt port link interface, or serial eeprom, to enabl e register access through the downstream transparent ports; a requester downstream from a transparent port cannot set the bit to grant itself (or peer s) access to pex 8524 regist ers. configuration requests can access those registers that are define d by pci-sig specific ations, and generally cannot access device-s pecific registers othe r than the nt port cursor mechanism registers. memory requests can access all pe x 8524 registers. rw yes 0 1 disable unsupported request response for reserved configuration registers 1 = disables completions with an uns upported request (ur) status from being returned when configuration writes are attempted on plx-specific registers rw yes 0
pex 8524 transparent mode port registers plx technology, inc. 284 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 24:2 fac tor y te st on ly rw yes 0-0h 25 fac tor y te st on ly silicon revision aa rw yes 0 disable upstream port bar0 and bar1 registers silicon revisions bb/bc 0 = enables upstream base address 0 and base address 1 registers ( bar0 and bar1 , offsets 10h and 14h , respectively) 1 = disables upstream base address 0 and base address 1 registers ( bar0 and bar1 , offsets 10h and 14h, respectively) rw yes 0 26 fac tor y te st on ly rw yes 0 27 reserved silicon revision aa 0 bios enumeration fix disable silicon revisions bb/bc for nt failover in silicon revisions bb/bc, this bit must be set. rw yes 0 31:28 fac tor y te st on ly rw yes 0h register 11-116. 660h ingress control (only ports 0 and 8) (cont.) bit(s) description type serial eeprom default
february, 2007 ingress control registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 285 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-117. 668h ingress port enable (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 ingress port enable the value of this register depends on the number of ports used, which is dependent on the port configuration register port configuration field (offset 224h [4:0]) value or strap_stn0_portcfg[4:0] and strap_stn1_portcfg[3:0] balls. set the upper 16 bits to ffffh. for the lower 16 bits, set each bit positi on that corresponds to an enabled port. when a port is enabled in the correspondi ng station configuration, the bit is set to 1; otherwise, the bit is cleared to 0. for example : if station 0 is configur ed as x8x4x4, bits [3:0]=0111b if station 0 is configur ed as x16, bits [3:0]=0001b if station 0 is configur ed as x8x8, bits [3:0]=0011b if station 0 is configured as x4x4x4x4, bits [3:0]=1111b table 11-19 provides a sample mapping, based on the port configuration value. note: this register in both stations (ports 0 and 8) must be programmed to the same value, to reflect th e configuration of all ports. rw yes ffff_0f0fh table 11-19. pex 8524 ingress port configurations port configuration register value (port 0 or 8, offset 224h[4:0]) lane width per port ingress port enable register value (port 0 or 8, offset 668h) station 0 station 1 0 1 8 9 10 11 0h x4 x4 x4 x4 x4 x4 ffff_0f03h 1h x16 a a. ports 8 and 9 can be combined to create a 16-lane (x16) port. ffff_0103h 2h x8 x8 x8 ffff_0303h 3h x8 x4 x4 ffff_0703h 4h x8 x4 x2 x2 ffff_0f03h 5h x8 x2 x2 x4 ffff_0f03h 6h x8 x2 x4 x2 ffff_0f03h
pex 8524 transparent mode port registers plx technology, inc. 286 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.5 i/o cam base and limi t upper 16 bits registers table 11-20. plx-specific i/o cam base and limit upper 16 bits register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 i/o cam_0 limit[31:16] upper port 0 i/o cam_0 base[31:16 ] upper port 0 680h i/o cam_1 limit[31:16] upper port 1 i/o cam_1 base[31:16 ] upper port 1 684h reserved 688h ? 69ch i/o cam_8 limit[31:16] upper port 8 i/o cam_8 base[31:16] upper port 8 6a0h i/o cam_9 limit[31:16] upper port 9 i/o cam_9 base[31:16] upper port 9 6a4h i/o cam_10 limit[31:16] upper port 10 i/ o cam_10 base[31:16] upper port 10 6a8h i/o cam_11 limit[31:16] upper port 11 i/ o cam_11 base[31:16] upper port 11 6ach reserved 6b0h ? 6bch register 11-118. 680h i/ocam_0 upper port 0 (only ports 0 and 8) bit(s) description type serial eeprom default 15:0 i/ocam base[31:16] i/o base upper 16 bits. rw yes ffffh 31:16 i/ocam limit[31:16] i/o limit upper 16 bits. rw yes 0000h register 11-119. 684h i/ocam_1 upper port 1 (only ports 0 and 8) bit(s) description type serial eeprom default 15:0 i/ocam base[31:16] i/o base upper 16 bits. rw yes ffffh 31:16 i/ocam limit[31:16] i/o limit upper 16 bits. rw yes 0000h
february, 2007 i/o cam base and limit upper 16 bits registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 287 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-120. 6a0h i/ocam_8 upper port 8 (only ports 0 and 8) bit(s) description type serial eeprom default 15:0 i/ocam base[31:16] i/o base upper 16 bits. rw yes ffffh 31:16 i/ocam limit[31:16] i/o limit upper 16 bits. rw yes 0000h register 11-121. 6a4h i/ocam_9 upper port 9 (only ports 0 and 8) bit(s) description type serial eeprom default 15:0 i/ocam base[31:16] i/o base upper 16 bits. rw yes ffffh 31:16 i/ocam limit[31:16] i/o limit upper 16 bits. rw yes 0000h register 11-122. 6a8h i/ocam_10 upper port 10 (only ports 0 and 8) bit(s) description type serial eeprom default 15:0 i/ocam base[31:16] i/o base upper 16 bits. rw yes ffffh 31:16 i/ocam limit[31:16] i/o limit upper 16 bits. rw yes 0000h register 11-123. 6ach i/ocam_11 upper port 11 (only ports 0 and 8) bit(s) description type serial eeprom default 15:0 i/ocam base[31:16] i/o base upper 16 bits. rw yes ffffh 31:16 i/ocam limit[31:16] i/o limit upper 16 bits. rw yes 0000h
pex 8524 transparent mode port registers plx technology, inc. 288 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.6 base address registers (bars) the registers defined in table 11-21 contain a shadow copy of the two type 1 configuration base address registers for each pex 8524 port. table 11-21. plx-specific base address register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 bar0 for port 0 6c0h bar1 for port 0 6c4h bar0 for port 1 6c8h bar1 for port 1 6cch reserved 6d0h ? 6fch bar0 for port 8 700h bar1 for port 8 704h bar0 for port 9 708h bar1 for port 9 70ch bar0 for port 10 710h bar1 for port 10 714h bar0 for port 11 718h bar1 for port 11 71ch reserved 720h ? 73ch register 11-124. 6c0h bar0 for port 0 (only ports 0 and 8) bit(s) description type serial eeprom default 0 memory space indicator 0 = memory bar 1 = i/o bar reads 0, and ignores writes. only value of 0 is allowed. ro no 0 2:1 memory mapping_0 range memory mapping for port 0. 00b = 32 bits 10b = 64 bits 01b, 11b = reserved rw yes 00b 3 prefetchable 0 = not prefetchable 1 = prefetchable reads 0, and ignores writes. ro yes 0 15:4 reserved 000h 31:16 base address_0 shadow copy of base address 0 for port 0. where bar0 [15:4] = reserved . rw yes 0000h
february, 2007 base address registers (bars) expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 289 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-125. 6c4h bar1 for port 0 (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 base address_1[63:32] when port 0 bar0 [2:1] = 10b, becomes a shadow copy of port 0 base address_1 [63:32]. rw yes 0000_0000h register 11-126. 6c8h bar0 for port 1 (only ports 0 and 8) bit(s) description type serial eeprom default 0 memory space indicator 0 = memory bar 1 = i/o bar reads 0, and ignores writes. only value of 0 is allowed. ro no 0 2:1 memory mapping_1 range memory mapping for port 1. 00b = 32 bits 10b = 64 bits 01b, 11b = reserved rw yes 00b 3 prefetchable 0 = not prefetchable 1 = prefetchable reads 0, and ignores writes. ro yes 0 15:4 reserved 000h 31:16 shadow copy of base address 0 for port 1. where bar0 [15:4] = reserved . rw yes 0000h register 11-127. 6cch bar1 for port 1 (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 base address_1[63:32] when port 1 bar0 [2:1] = 10b, becomes a shadow copy of port 1 base address_1 [63:32]. rw yes 0000_0000h
pex 8524 transparent mode port registers plx technology, inc. 290 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-128. 700h bar0 for port 8 (only ports 0 and 8) bit(s) description type serial eeprom default 0 memory space indicator 0 = memory bar 1 = i/o bar reads 0, and ignores writes. only value of 0 is allowed. ro no 0 2:1 memory mapping_8 range memory mapping for port 8. 00b = 32 bits 10b = 64 bits 01b, 11b = reserved rw yes 00b 3 prefetchable 0 = not prefetchable 1 = prefetchable reads 0, and ignores writes. ro yes 0 15:4 reserved 000h 31:16 base address_0 shadow copy of base address 0 for port 8. where bar0 [15:4] = reserved . rw yes 0000h register 11-129. 704h bar1 for port 8 (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 base address_1[63:32] when port 8 bar0 [2:1] = 10b, becomes a shadow copy of port 8 base address_1 [63:32]. rw yes 0000_0000h
february, 2007 base address registers (bars) expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 291 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-130. 708h bar0 for port 9 (only ports 0 and 8) bit(s) description type serial eeprom default 0 memory space indicator 0 = memory bar 1 = i/o bar reads 0, and ignores writes. only value of 0 is allowed. ro no 0 2:1 memory mapping_9 range memory mapping for port 9. 00b = 32 bits 10b = 64 bits 01b, 11b = reserved rw yes 00b 3 prefetchable 0 = not prefetchable 1 = prefetchable reads 0, and ignores writes. ro yes 0 15:4 reserved 000h 31:16 base address_0 shadow copy of base address 0 for port 9. where bar0 [15:4] = reserved . rw yes 0000h register 11-131. 70ch bar1 for port 9 (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 base address_1[63:32] when port 9 bar0 [2:1] = 10b, becomes a shadow copy of port 9 base address_1 [63:32]. rw yes 0-0h
pex 8524 transparent mode port registers plx technology, inc. 292 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-132. 710h bar0 for port 10 (only ports 0 and 8) bit(s) description type serial eeprom default 0 memory space indicator 0 = memory bar 1 = i/o bar reads 0, and ignores writes. only value of 0 is allowed. ro no 0 2:1 memory mapping_10 range memory mapping for port 10. 00b = 32 bits 10b = 64 bits 01b, 11b = reserved rw yes 00b 3 prefetchable 0 = not prefetchable 1 = prefetchable reads 0, and ignores writes. ro yes 0 15:4 reserved 000h 31:16 base address_0 shadow copy of base address 0 for port 10. where bar0 [15:4] = reserved . rw yes 0000h register 11-133. 714h bar1 for port 10 (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 base address_1[63:32] when port 10 bar0 [2:1] = 10b, becomes a shadow copy of port 10 base address_1 [63:32]. rw yes 0-0h
february, 2007 base address registers (bars) expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 293 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-134. 718h bar0 for port 11 (only ports 0 and 8) bit(s) description type serial eeprom default 0 memory space indicator 0 = memory bar 1 = i/o bar reads 0, and ignores writes. only value of 0 is allowed. ro no 0 2:1 memory mapping_11 range memory mapping for port 11. 00b = 32 bits 10b = 64 bits 01b, 11b = reserved rw yes 00b 3 prefetchable 0 = not prefetchable 1 = prefetchable reads 0, and ignores writes. ro yes 0 15:4 reserved 000h 31:16 base address_0 shadow copy of base address 0 for port 11. where bar0 [15:4] = reserved . rw yes 0000h register 11-135. 71ch bar1 for port 11 (only ports 0 and 8) bit(s) description type serial eeprom default 31:0 base address_1[63:32] when port 11 bar0 [2:1] = 10b, becomes a shadow copy of port 11 base address_1 [63:32]. rw yes 0-0h
pex 8524 transparent mode port registers plx technology, inc. 294 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.7 shadow virtual channe l (vc) capability registers table 11-22. plx-specific shadow virtual channel (vc) capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 vc0 port 0 capability 740h vc1 port 0 capability 744h vc0 port 1 capability 748h vc1 port 1 capability 74ch reserved 750h ? 77ch vc0 port 8 capability 780h vc1 port 8 capability 784h vc0 port 9 capability 788h vc1 port 9 capability 78ch vc0 port 10 capability 790h vc1 port 10 capability 794h vc0 port 11 capability 798h vc1 port 11 capability 79ch reserved 7a0h ? 83ch port 0 vc capability_1 840h port 1 vc capability_1 844h reserved 848h ? 85ch port 8 vc capability_1 860h port 9 vc capability_1 864h port 10 vc capability_1 868h port 11 vc capability_1 86ch reserved 870h ? 9ech
february, 2007 shadow virtual ch annel (vc) capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 295 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-136. 740h vc0 port 0 capability (all ports) bit(s) description type serial eeprom default 0 tc_vc0_0 map[0] always mapped to virtual channel 0. reads 1, and ignores writes. ro yes 1 7:1 tc_vc0_0 map[7:1] mapped to virtual channel 0 by defaul t. software can change this field during enumeration or when assigning traffic to the traffic class. rw yes 7fh 23:8 reserved 000h 24 vc0_0 id port 0 virtual channel 0 id. ro yes 0 30:25 reserved 00h 31 vc0_0 enable port 0 virtual channel 0 enable. ro yes 1 register 11-137. 744h vc1 port 0 capability (only ports 0 and 8) bit(s) description type serial eeprom default 0 reserved 0 7:1 tc_vc1_0 map[7:1] mapped to virtual channel 1 by default. software can change this field during enumeration or when quiescing the traffic to the traffic class. rw yes 00h 23:8 reserved 000h 24 vc1_0 id port 0 virtual channel 1 id. rw yes 1 30:25 reserved 000h 31 vc1_0 enable port 0 virtual channel 1 enable. rw yes 0
pex 8524 transparent mode port registers plx technology, inc. 296 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-138. 748h vc0 port 1 capability (only ports 0 and 8) bit(s) description type serial eeprom default 0 tc_vc0_1 map[0] always mapped to virtual channel 0. reads 1, and ignores writes. ro yes 1 7:1 tc_vc0_1 map[7:1] mapped to virtual channel 0 by default. software can change this field during enumeration or when quiescing the traffic to the traffic class. rw yes 7fh 23:8 reserved 000h 24 vc0_1 id port 1 virtual channel 0 id. ro yes 0 30:25 reserved 000h 31 vc0_1 enable port 1 virtual channel 0 enable. ro yes 1 register 11-139. 74ch vc1 port 1 capability (only ports 0 and 8) bit(s) description type serial eeprom default 0 reserved 0 7:1 tc_vc1_1 map[7:1] mapped to virtual channel 1 by default. software can change this field during enumeration or when quiescing the traffic to the traffic class. rw yes 00h 23:8 reserved 000h 24 vc1_1 id port 1 virtual channel 1 id. rw yes 1 30:25 reserved 000h 31 vc1_1 enable port 1 virtual channel 1 enable. rw yes 0
february, 2007 shadow virtual ch annel (vc) capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 297 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-140. 780h vc0 port 8 capability (only ports 0 and 8) bit(s) description type serial eeprom default 0 tc_vc0_8 map[0] always mapped to virtual channel 0. reads 1, and ignores writes. ro yes 1 7:1 tc_vc0_8 map[7:1] mapped to virtual channel 0 by default. software can change this field during enumeration or when quiescing the traffic to the traffic class. rw yes 7fh 23:8 reserved 000h 24 vc0_8 id port 8 virtual channel 0 id. ro yes 0 30:25 reserved 000h 31 vc0_8 enable port 8 virtual channel 0 enable. ro yes 1 register 11-141. 784h vc1 port 8 capability (only ports 0 and 8) bit(s) description type serial eeprom default 0 reserved 0 7:1 tc_vc1_8 map[7:1] mapped to virtual channel 1 by default. software can change this field during enumeration or when quiescing the traffic to the traffic class. rw yes 00h 23:8 reserved 000h 24 vc1_8 id port 8 virtual channel 1 id. rw yes 1 30:25 reserved 000h 31 vc1_8 enable port 8 virtual channel 1 enable. rw yes 0
pex 8524 transparent mode port registers plx technology, inc. 298 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-142. 788h vc0 port 9 capability (only ports 0 and 8) bit(s) description type serial eeprom default 0 tc_vc0_9 map[0] always mapped to virtual channel 0. reads 1, and ignores writes. ro yes 1 7:1 tc_vc0_9 map[7:1] mapped to virtual channel 0 by default. software can change this field during enumeration or when quiescing the traffic to the traffic class. rw yes 7fh 23:8 reserved 000h 24 vc0_9 id port 9 virtual channel 0 id. ro yes 0 30:25 reserved 000h 31 vc0_9 enable port 9 virtual channel 0 enable. ro yes 1 register 11-143. 78ch vc1 port 9 capability (only ports 0 and 8) bit(s) description type serial eeprom default 0 reserved 0 7:1 tc_vc1_9 map[7:1] mapped to virtual channel 1 by default. software can change this field during enumeration or when quiescing the traffic to the traffic class. rw yes 00h 23:8 reserved 000h 24 vc1_9 id port 9 virtual channel 1 id. rw yes 1 30:25 reserved 000h 31 vc1_9 enable port 9 virtual channel 1 enable. rw yes 0
february, 2007 shadow virtual ch annel (vc) capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 299 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-144. 790h vc0 port 10 capability (only ports 0 and 8) bit(s) description type serial eeprom default 0 tc_vc0_10 map[0] always mapped to virtual channel 0. reads 1, and ignores writes. ro yes 1 7:1 tc_vc0_10 map[7:1] mapped to virtual channel 0 by default. software can change this field during enumeration or when quiescing the traffic to the traffic class. rw yes 7fh 23:8 reserved 000h 24 vc0_10 id port 10 virtual channel 0 id. ro yes 0 30:25 reserved 000h 31 vc0_10 enable port 10 virtual channel 0 enable. ro yes 1 register 11-145. 794h vc1 port 10 capability (only ports 0 and 8) bit(s) description type serial eeprom default 0 reserved 0 7:1 tc_vc1_10 map[7:1] mapped to virtual channel 1 by default. software can change this field during enumeration or when quiescing the traffic to the traffic class. rw yes 00h 23:8 reserved 000h 24 vc1_10 id port 10 virtual channel 1 id. rw yes 1 30:25 reserved 000h 31 vc1_10 enable port 10 virtual channel 1 enable. rw yes 0
pex 8524 transparent mode port registers plx technology, inc. 300 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-146. 798h vc0 port 11 capability (only ports 0 and 8) bit(s) description type serial eeprom default 0 tc_vc0_11 map[0] always mapped to virtual channel 0. reads 1, and ignores writes. ro yes 1 7:1 tc_vc0_11 map[7:1] mapped to virtual channel 0 by default. software can change this field during enumeration or when quiescing the traffic to the traffic class. rw yes 7fh 23:8 reserved 000h 24 vc0_11 id port 11 virtual channel 0 id. ro yes 0 30:25 reserved 000h 31 vc0_11 enable port 11 virtual channel 0 enable. ro yes 1 register 11-147. 79ch vc1 port 11 capability (only ports 0 and 8) bit(s) description type serial eeprom default 0 reserved 0 7:1 tc_vc1_11 map[7:1] mapped to virtual channel 1 by default. software can change this field during enumeration or when quiescing the traffic to the traffic class. rw yes 00h 23:8 reserved 000h 24 vc1_11 id port 11 virtual channel 1 id. rw yes 1 30:25 reserved 000h 31 vc1_11 enable port 11 virtual channel 1 enable. rw yes 0
february, 2007 shadow virtual ch annel (vc) capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 301 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-148. 840h port 0 vc capability_1 (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 reserved 0h 4 low-priority extended vc count low-priority virtual channel count. rw yes 0 31:5 reserved 0-0h register 11-149. 844h port 1 vc capability_1 (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 reserved 0h 4 low-priority extended vc count low-priority virtual channel count. rw yes 0 31:5 reserved 0-0h
pex 8524 transparent mode port registers plx technology, inc. 302 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-150. 860h port 8 vc capability_1 (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 reserved 0h 4 low-priority extended vc count low-priority virtual channel count. rw yes 0 31:5 reserved 0-0h register 11-151. 864h port 9 vc capability_1 (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 reserved 0h 4 low-priority extended vc count low-priority virtual channel count. rw yes 0 31:5 reserved 0-0h register 11-152. 868h port 10 vc capability_1 (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 reserved 0h 4 low-priority extended vc count low-priority virtual channel count. rw yes 0 31:5 reserved 0-0h register 11-153. 86ch port 11 vc capability_1 (only ports 0 and 8) bit(s) description type serial eeprom default 3:0 reserved 0h 4 low-priority extended vc count low-priority virtual channel count. rw yes 0 31:5 reserved 0-0h
february, 2007 ingress credit handler (inch) registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 303 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.8 ingress credit ha ndler (inch) registers changing credits values from default re gister values must be done carefully. credits must be programmed properly, otherwise the device will not function as expected. al so, there are minimal required header credits for all the flows, which are required to achieve reasonable performance. (refer to the pex 85xx eeprom ? pex 8532/8524/8516 design note , s ection 6.9, ?internal credit handler vcnt threshold registers,? for details.) the minimum initial payload credits for posted and completions must exceed the required cr edits for a maximum payload size tlp by 8. table 11-23. plx-specific ingress credit handler (inch) register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved 9f0h inch fc update pending timer 9f4h reserved 9f8h reserved inch mode 9fch inch threshold port 0 or 8 vc0 posted a00h inch threshold port 0 or 8 vc0 non-posted a04h inch threshold port 0 or 8 vc0 completion a08h inch threshold port 0 or 8 vc1 posted a0ch inch threshold port 0 or 8 vc1 non-posted a10h inch threshold port 0 or 8 vc1 completion a14h inch threshold port 1 or 9 vc0 posted a18h inch threshold port 1 or 9 vc0 non-posted a1ch inch threshold port 1 or 9 vc0 completion a20h inch threshold port 1 or 9 vc1 posted a24h inch threshold port 1 or 9 vc1 non-posted a28h inch threshold port 1 or 9 vc1 completion a2ch inch threshold port 10 vc0 posted a30h inch threshold port 10 vc0 non-posted a34h inch threshold port 10 vc0 completion a38h inch threshold port 10 vc1 posted a3ch inch threshold port 10 vc1 non-posted a40h inch threshold port 10 vc1 completion a44h inch threshold port 11 vc0 posted a48h inch threshold port 11 vc0 non-posted a4ch inch threshold port 11 vc0 completion a50h inch threshold port 11 vc1 posted a54h inch threshold port 11 vc1 non-posted a58h inch threshold port 11 vc1 completion a5ch reserved ac0h ? b7ch
pex 8524 transparent mode port registers plx technology, inc. 304 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-154. 9f4h inch fc update pending timer (only ports 0 and 8) bit(s) description type serial eeprom default 7:0 port 0 or 8 update timer update pending timer for po rt 0 or 8. port 0 copy controls port 0, and port 8 copy controls port 8. (refer to table 11-24 .) for implementation, a value of 01h or 00h into the csr results in waiting 255 symbol times. values are automatically set at reset according to the device control register maximum payload size (offset 70h [ 7:5 ]) and link status register negotiated link width (offset 78h [ 25:20 ]) fields. programmable by serial eeprom if the associated inch mode register pending timer source bit (offset 9fch [20]) is set. rw yes 00h 15:8 port 1 or 9 update timer update pending timer for po rt 1 or 9. port 1 copy controls port 1, and port 9 copy controls port 9. (refer to table 11-24 .) for implementation, a value of 01h or 00h into the csr results in waiting 255 symbol times. values are automatically set at reset according to the device control register maximum payload size (offset 70h[7:5]) and link status register negotiated link width (offset 78h[25:20]) fields. program mable by serial eeprom if the associated inch mode register pending timer source bit (offset 9fch[21]) is set. rw yes 00h 23:16 port 10 update timer update pending time r for port 10. reserved for station 0. (refer to table 11-24 .) for implementation, a value of 01h or 00h into the csr results in waiting 255 symbol times. values are automatically set at reset according to the device control register maximum payload size (offset 70h[7:5]) and link status register negotiated link width (offset 78h[25:20]) fields. program mable by serial eeprom if the associated inch mode register pending timer source bit (offset 9fch[22]) is set. rw yes 00h 31:24 port 11 update timer update pending time r for port 11. reserved for station 0. (refer to table 11-24 .) for implementation, a value of 01h or 00h into the csr results in waiting 255 symbol times. values are automatically set at reset according to the device control register maximum payload size (offset 70h[7:5]) and link status register negotiated link width (offset 78h[25:20]) fields. program mable by serial eeprom if the associated inch mode register pending timer source bit (offset 9fch[23]) is set. rw yes 00h
february, 2007 ingress credit handler (inch) registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 305 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 table 11-24. fc update pending timer guidelines maximum packet size link width recommended timer count 128 bytes x1 76h x2 40h x4 24h x8 21h x16 (station 1 only) 18h 256 bytes x1 d0h x2 6ch x4 3bh x8 36h x16 (station 1 only) 24h register 11-155. 9fch inch mode (only ports 0 and 8) bit(s) description type serial eeprom default 7:0 maximum mode enable factory test only ro yes ffh 15:8 reserved 0h 19:16 factory test only rw yes 0h 23:20 pending timer source 0 = inch fc update pending timer register (offset 9f4h ) uses default value 1 = inch fc update pending timer register (offset 9f4h) uses serial eeprom value bit port 0 port 8 20 port 0 pending timer source port 8 pending timer source 21 port 1 pending timer source port 9 pending timer source 22 reserved port 10 pending timer source 23 reserved port 11 pending timer source rw yes 0-0h 31:24 reserved 00h
pex 8524 transparent mode port registers plx technology, inc. 306 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.8.1 inch threshold port virtual channel registers there are six ingress credit handler (inch) threshold port vc regist ers, which are du plicated for each port. these registers represent the maximum number of headers or payload cred its allocated per port, virtual channel, and type. the register names and address/location are defined in table 11-23 . the following registers describe the data that applies to these registers. register 11-156. a00h, a18h, a30h, a48h inch threshold port n vc0 posted (only ports 0 and 8, where n = 0 through 1 for station 0 ports, and n = 8 through 11 for station 1 ports) bit(s) description type serial eeprom default posted credits are used for virtual channel 0 (vc0) memory write and message transactions. 2:0 reserved aa ? 0a58h bb/bc ? 1890h 8:3 payload reserved bits [2:0] force the payload credits to be a multiple of 8. minimum value = maximum payload size (mps; encoded in offset 70h [7:5]) divided by 16, rounded up to a multiple of 8. minimum value for 256 mps is 0_0001_0b; otherwise, the minimum value is 0_0000_1b. silicon revision aa payload = 0_0101_1b = bh, shifted left 3 bits is 58h = 88 payload credits (1,408 bytes). silicon revisions bb/bc payload = 0_1001_0b = 12h, shifted left 3 bits is 90h = 144 payload credits (2,304 bytes). rw yes 13:9 header minimum value = 00_001b. silicon revision aa header = 00_101b = 5h = 5 header credits. silicon revisions bb/bc header = 01_100b = ch = 12 header credits. 31:14 reserved 0-0h
february, 2007 ingress credit handler (inch) registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 307 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-157. a04h, a1ch, a34h , a4ch inch threshold port n vc0 non-posted (only ports 0 and 8, where n = 0 through 1 for station 0 ports, and n = 8 through 11 for station 1 ports) bit(s) description type serial eeprom default non-posted credits are used for virt ual channel 0 (vc0) memory read, i/o read, i/o write, configuration read, and configuration wr ite transactions. 8:0 payload minimum value = 0_0000_0001b. silicon revision aa payload = 0_0000_1001b = 9 payload credits (144 bytes). silicon revisions bb/bc payload = 0_0000_0111b = 7 payload credits (112 bytes). rw yes aa ? 1209h bb/bc ? 0e07h 13:9 header minimum value = 00_001b. silicon revision aa header = 01_001b = 9 header credits. silicon revisions bb/bc header = 00_111b = 7 header credits. 31:14 reserved 0-0h register 11-158. a08h, a20h, a38h, a50h inch threshold port n vc0 completion (only ports 0 and 8, where n = 0 through 1 for station 0 ports, and n = 8 through 11 for station 1 ports) bit(s) description type serial eeprom default completion credits are used for virtual channel 0 (vc0) memory read, i/o read, i/o write, configuration read, and configuration write tr ansaction completions. 2:0 reserved aa ? 0a58h bb/bc ? 1480h 8:3 payload reserved bits [2:0] force the payload credits to be a multiple of 8. minimum value = maximum payload size (mps; encoded in offset 70h [7:5]) or size of largest read request (whichever is smaller), divided by 16, rounded up to a multiple of 8. minimum value for mps or largest read request greater than 128 bytes is 0_0001_0b; otherwis e, the minimum value is 0_0000_1b. silicon revision aa payload = 0_0101_1b = bh, shifted left 3 bits is 58h = 88 payload credits (1,408 bytes). silicon revisions bb/bc payload = 0_1000_0b = 10h, shifted left 3 bits is 00h = 128 payload credits (2,048 bytes). rw yes 13:9 header minimum value = 00_001b. silicon revision aa header = 00_101b = 5h = 5 header credits. silicon revisions bb/bc header = 01_010b = ah = 10 header credits. 31:14 reserved 0-0h
pex 8524 transparent mode port registers plx technology, inc. 308 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-159. a0ch, a24h, a3ch, a54h inch threshold port n vc1 posted (only ports 0 and 8, where n = 0 through 1 for station 0 ports, and n = 8 through 11 for station 1 ports) bit(s) description type serial eeprom default posted credits are used for virtual channel 1 (vc1) memory wr ite and message transactions. a port does not advertise vc1 credit s unless its vc1 is enabled, by setting the port?s vc1 resource control register vc1 enable bit (offset 168h [ 31 ]=1). 2:0 reserved 210h 8:3 payload payload = 0_0001_0b = 2h, shifted left 3 bits to be a multiple of 8, for 10h = 16 payload credits (256 bytes). rw yes 13:9 header header = 00_001b = 1 header credit. 31:14 reserved 0-0h register 11-160. a10h, a28h, a40h, a58h inch threshold port n vc1 non-posted (only ports 0 and 8, where n = 0 through 1 for station 0 ports, and n = 8 through 11 for station 1 ports) bit(s) description type serial eeprom default non-posted credits are used for virtual channel 1 (vc1) memory read, i/o read, i/o write, configuration read, and configuration write transactions. a port does not advertise vc 1 credits unless its vc1 is enab led, by setting the port?s vc1 resource control register vc1 enable bit (offset 168h [ 31 ]=1). 8:0 payload payload = 0_0000_0001b = 1 payload credit (112 bytes). rw yes 0201h 13:9 header header = 00_001b = 1 header credit. 31:14 reserved 0-0h register 11-161. a14h, a2ch, a44h , a5ch inch threshold port n vc1 completion (only ports 0 and 8, where n = 0 through 1 for station 0 ports, and n = 8 through 11 for station 1 ports) bit(s) description type serial eeprom default completion credits are used for virtual channel 1 (vc1) memory read, i/o read, i/o write, configuration read, and configuration write transa ction completions. a port does not advertise vc1 credits unless its vc1 is enabled, by setting the port?s vc1 resource control register vc1 enable bit (offset 168h [ 31 ]=1). 2:0 reserved 210h 8:3 payload payload = 0_0001_0b = 2h, shifted left 3 bits to be a multiple of 8, for 10h = 16 payload credits (256 bytes). rw yes 13:9 header header = 00_001b = 1 header credit. 31:14 reserved 0-0h
february, 2007 ingress one-bit ecc error count register expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 309 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.9 ingress one-bit ecc error count register table 11-25. plx-specific ingress one-bit ecc error count register map (only ports 0 and 8) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ingress one-bit ecc error count reserved be8h register 11-162. be8h ingress one-bit ecc error count (only ports 0 and 8) bit(s) description type serial eeprom default 15:0 reserved 0000h 23:16 ingress packet ram 1-bit ecc count record number of 1-bit correctable erro rs that occurred in ingress ram. counter increments for each 1-bit soft error detected in ram. ro no 00h 31:24 ingress pointer linked list ram 1-bit ecc count record number of 1-bit correctable e rrors that occurred in the ingress pointer linked list ram. counter incr ements for each 1-bit soft error detected in ram. ro no 00h
pex 8524 transparent mode port registers plx technology, inc. 310 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.10 relaxed completion ordering (ingress) register ? silicon revisions bb/bc only table 11-26. plx-specific relaxed completion orderi ng (ingress) register map (only ports 0 and 8, silicon revisions bb/bc only) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 plx-specific relaxed co mpletion ordering (ingress) bech register 11-163. bech plx-specific relaxed completion ordering (ingress) (only ports 0 and 8, silicon revisions bb/bc only) bit(s) description type serial eeprom default 0 enable plx-specific relaxed completion ordering silicon revision aa not supported silicon revisions bb/bc enables plx-specific relaxed co mpletion ordering on ingress ports identified by the plx-specific relaxed ordering mode (ingress) register (offset bfch ). rw yes 0 31:1 reserved 0-0h
february, 2007 relaxed ordering mode (ingress) register expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 311 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.11 relaxed ordering mode (ingress) register table 11-27. plx-specific relaxed ordering mode (ingress) register map (only ports 0 and 8) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved bf0h ? bf8h plx-specific relaxed ordering mode (ingress) bfch register 11-164. bfch plx-specific relaxed ordering mode (ingress) (only ports 0 and 8) bit(s) description type serial eeprom default 7:0 enable_rlx_ordering port 0 or 8 when any of these bits are set, the corresponding traffic class for this port allows plx-specific relaxe d ordering on port 0 or 8. rw yes 00h 15:8 enable_rlx_ordering port 1 or 9 when any of these bits are set, the corresponding traffic class for this port allows plx-specific relaxe d ordering on port 1 or 9. rw yes 00h 23:16 enable_rlx_ordering port 10 when any of these bits are set, the corresponding traffic class for this port allows plx-specific rela xed ordering on port 10. reserved for station 0. rw yes 00h 31:24 enable_rlx_ordering port 11 when any of these bits are set, the corresponding traffic class for this port allows plx-specific rela xed ordering on port 11. reserved for station 0. rw yes 00h
pex 8524 transparent mode port registers plx technology, inc. 312 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.13.12 internal credit handler (itch) vc&t threshold registers the itch virtual channel (vc) and type [p (p osted), np (non-posted), and cpl (completion)] (vc&t) threshold registers in each station define internal credits and mechanisms that are used to prevent egress packet ram (containing outgoing packet s to be transmitted by ports in a station) from being overflowed by packets from the ingress p acket ram (containing incoming packets received by ports in a station). the egress packet ram can become filled due to lack of ingress credits from the external device, or insufficient bandwidth to transm it packets as fast as they arrive. the internal mechanisms prevent overflow by applying backpressu re from the egress ram to the ingress ports (and ultimately to external devices by withholding additional ingress credits). table 11-28 defines the itch vc&t (virtual channel threshold register map. the pex 8524 uses one of two backpressure mechanisms, depending on the itch vc&t register values: deadlock avoidance mode (silicon revisions aa, bb, and bc) ? enabled as the default backpressure mode, when the itch vc&t values are the default register values (in which the threshold values do not correspond to physical locations within the egress packet ram). in deadlock avoidance mode, once the switch port? s egress queue fills to 75% of capacity, the switch gives priority to posted traffic, to avoid deadlock. pex 8524 silicon revisions aa, ba and bb should operate in deadlock avoidance mode, with the itch vc&t registers programmed only to default register values, unless threshold mode is needed to resolve a requester completion timeout issue in applications where completions are delayed when deadlock avoidance mode activat es (due to the egress packet ram becoming more than 75% full). threshold mode (silicon revision bc only) ? enabled when the itch vc&t registers are programmed to non-default packet coun t values. the non-defau lt register values effectively partition the egress ram into separa te sections for posted, non-posted and/or completion packets. in threshold mode, if the egress packet ram fills with packets of a particular vc&t beyond the programmed upper packet count value for that vc&t, internal forwarding of additional packets of that vc&t from ingress packet ram to egress packet ram is halted. when sufficient packets of that same vc&t are emptie d from the egress packet ram (by the egress ports in the station) such that the egress p acket ram contains fewer packets of that vc&t than the programmed lower packet count for th at vc&t, internal forwarding of packets (of that same vc&t) to egress packet ram from ingress packet ram resumes. note: previously scheduled packets arrive in their entirety, completely unaffected by the cut-off signal. all ports in a station share the egress packet ram, as well as the same itch vc&t threshold register values; therefore, the itch vc&t threshold register values allocat e the ram equally among all enabled ports within the station. table 11-28. pex 8524 plx-specific internal credit handler (itch) vc&t threshold register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 itch vc&t threshold_1 c00h itch vc&t threshold_2 c04h itch vc&t threshold_3 c08h
february, 2007 internal credit handle r (itch) vc&t threshold registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 313 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 while deadlock avoidance mode can allow blocking of completion p ackets if the egress packet ram fills to 75% of capacity, recommende d register values for threshold mode allow completion packets to potentially make comparatively further forwar d progress (than in deadlock avoidance mode). therefore, for applicati ons that can potentially experience conges tion within the egress packet ram, threshold mode is recommended for pex 8524 silicon revision bc, to reduce the possibility of completion timeout (by a requester of read requests). generally, it is sufficient to program only the post ed packet counts, and le ave the non-posted and completion packet counts at default values. programming only the posted packet counts prevents clogging of the egress ram for any combination of packets, al lowing non-posted and completion transactions to make forward progress from the ingress packet ram into the egress packet ram, regardless of whether the egress packet ram is filled with posted packets. for calculating itch vc&t threshold register values, each station contains 40,960 bytes of egress packet ram, structured as 2,048, 20-byte beats, and each unit in the itch vc&t threshold register values corresponds to eight, 20-byte beats. therefor e, a programmed value of 1 represents 160 bytes, 2 is 320 bytes, and so forth. the entire tlp (header, payload, and ecrc, if any) is used to determine a total byte size, and the total byte size is divided by 20 and rounded up to the nearest integer to ascertain the number of beats. recommended register values for threshold mode are based upon the number of ports enabled in a station (as configured in the port configuration register, offset 224h ). a port is considered enabled, regardless of whether it is used. the number of enabled ports is usually the same as the physical layer status register number of ports enumerated field (offset 220h [ 22:20 ]), which the pex 8524 automatically updates after a reset. table 11-29 lists the recommended posted upper packet count values (for offset c00h [ 7:0 ] for vc0, and offset c04h [ 23:16 ] for vc1). the posted lower packet count values must be at l east 5 or 6 less than the posted upper packet count. table 11-30 lists the recommended posted lower p acket count values (for offset c00h[ 15:8 ] for vc0, and offset c04h[ 31:24 ] for vc1), which are 12 less than the posted upper packet count. table 11-29. itch vc&t posted upper packet count number of enabled ports port configuration register value (port 0 or 8, offset 224h[4:0]) vc0 value (offset c00h[7:0]) vc1 value (offset c04h[23:16]) 11heeh 22h6eh 3 3h 43h 4 0h, 4h, 5h, 6h 2eh table 11-30. itch vc&t posted lower packet count number of enabled ports port configuration register value (port 0 or 8, offset 224h[4:0]) vc0 value (offset c00h[15:8]) vc1 value (offset c04h[31:24]) 11he2h 2 2h 62h 3 3h 37h 4 0h, 4h, 5h, 6h 22h
pex 8524 transparent mode port registers plx technology, inc. 314 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-165. c00h itch vc&t threshold_1 (only ports 0 and 8) bit(s) description type serial eeprom default 7:0 vc0 posted upper packet count vc0 posted upper packet beat limit. rw yes ffh 15:8 vc0 posted lower packet count vc0 posted lower pa cket beat limit. rw yes 7fh 23:16 vc0 non-posted upper packet count vc0 non-posted upper packet beat limit. rw yes ffh 31:24 vc0 non-posted lower packet count vc0 non-posted lower packet beat limit. rw yes 7fh register 11-166. c04h itch vc&t threshold_2 (only ports 0 and 8) bit(s) description type serial eeprom default 7:0 vc0 completion upper packet count vc0 completion upper packet beat limit. rw yes ffh 15:8 vc0 completion lower packet count vc0 completion lower packet beat limit. rw yes 7fh 23:16 vc1 posted upper packet count vc1 posted upper packet beat limit. rw yes ffh 31:24 vc1 posted lower packet count vc1 posted lower pa cket beat limit. rw yes 7fh register 11-167. c08h itch vc&t threshold_3 (only ports 0 and 8) bit(s) description type serial eeprom default 7:0 vc1 non-posted upper packet count vc1 non-posted upper packet beat limit. rw yes ffh 15:8 vc1 non-posted lower packet count vc1 non-posted lower packet beat limit. rw yes 7fh 23:16 vc1 completion upper packet count vc1 completion upper pa cket beat limit. rw yes ffh 31:24 vc1 completion lower packet count vc1 completion lower packet beat limit. rw yes 7fh
february, 2007 advanced error reporting capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 315 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 11.14 advanced error reporting capability registers table 11-31. advanced error reporting capability register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next capability offset ( 138h ) capability ve r s i o n ( 1h ) pci express extended capability id ( 0001h )fb4h uncorrectable error status fb8h uncorrectable error mask fbch uncorrectable error severity fc0h correctable error status fc4h correctable error mask fc8h advanced error capa bilities and control fcch header log_0 fd0h header log_1 fd4h header log_2 fd8h header log_3 fdch reserved fe0h ? ffch
pex 8524 transparent mode port registers plx technology, inc. 316 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-168. fb4h pci express enhanced capability header (all ports) bit(s) description type serial eeprom default 15:0 pci express extended capability id ro yes 0001h 19:16 capability version ro yes 1h 31:20 next capability offset ro yes 138h register 11-169. fb8h uncorrectable error status (all ports) bit(s) description type serial eeprom default 0 training error status 0 = no error detected 1 = error detected rw1cs yes 0 3:1 reserved 000b 4 data link protocol error status 0 = no error detected 1 = error detected rw1cs yes 0 11:5 reserved 0000_000b 12 poisoned tlp status 0 = no error detected 1 = error detected rw1cs yes 0 13 reserved rw1cs yes 0 14 reserved note: bit 14 is not applicable to switches; therefore, the pci express base r1.0a provides exemption from supporting this bit. 0 15 completer abort status 0 = no error detected 1 = error detected rw1cs yes 0 16 reserved rw1cs yes 0 17 receiver overflow status 0 = no error detected 1 = error detected rw1cs yes 0 18 malformed tlp status 0 = no error detected 1 = error detected rw1cs yes 0 19 ecrc error status 0 = no error detected 1 = error detected rw1cs yes 0 20 unsupported request error status 0 = no error detected 1 = error detected rw1cs yes 0 31:21 reserved 0-0h
february, 2007 advanced error reporting capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 317 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-170. fbch uncorrectable error mask (all ports) bit(s) description type serial eeprom default 0 training error mask 0 = no mask is set 1 = error reporting, first error upda te, and header logging are masked for this error rws yes 0 3:1 reserved 000b 4 data link protocol error mask 0 = no mask is set 1 = error reporting, first error upda te, and header logging are masked for this error rws yes 0 11:5 reserved 0000_000b 12 poisoned tlp mask 0 = no mask is set 1 = error reporting, first error upda te, and header logging are masked for this error rws yes 0 13 reserved rws yes 0 14 reserved note: bit 14 is not applicable to switches; therefore, the pci express base r1.0a provides exemption from supporting this bit. 0 15 completer abort mask 0 = no mask is set 1 = error reporting, first error upda te, and header logging are masked for this error rws yes 0 16 reserved rws yes 0 17 receiver overflow mask 0 = no mask is set 1 = error reporting, first error upda te, and header logging are masked for this error rws yes 0 18 malformed tlp mask 0 = no mask is set 1 = error reporting, first error upda te, and header logging are masked for this error rws yes 0 19 ecrc error mask 0 = no mask is set 1 = error reporting, first error upda te, and header logging are masked for this error rws yes 0 20 unsupported request error mask 0 = no mask is set 1 = error reporting, first error upda te, and header logging are masked for this error rws yes 0 31:21 reserved 0-0h
pex 8524 transparent mode port registers plx technology, inc. 318 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-171. fc0h uncorrectable error severity (all ports) bit(s) description type serial eeprom default 0 training error severity 0 = error reported as non-fatal 1 = error reported as fatal rws yes 1 3:1 reserved 000b 4 data link protocol error severity 0 = error reported as non-fatal 1 = error reported as fatal rws yes 1 11:5 reserved 0-0h 12 poisoned tlp severity 0 = error reported as non-fatal 1 = error reported as fatal rws yes 0 13 reserved rws yes 1 14 reserved note: bit 14 is not applicable to switches; therefore, the pci express base r1.0a provides ex emption from supporting this bit. 0 15 completer abort severity 0 = error reported as non-fatal 1 = error reported as fatal rws yes 0 16 reserved rws yes 0 17 receiver overflow severity 0 = error reported as non-fatal 1 = error reported as fatal rws yes 1 18 malformed tlp severity 0 = error reported as non-fatal 1 = error reported as fatal rws yes 1 19 ecrc error severity 0 = error reported as non-fatal 1 = error reported as fatal rws yes 0 20 unsupported request error severity 0 = error reported as non-fatal 1 = error reported as fatal rws yes 0 31:21 reserved 0-0h
february, 2007 advanced error reporting capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 319 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-172. fc4h correctable error status (all ports) bit(s) description type serial eeprom default 0 receiver error status 0 = no error detected 1 = error detected rw1cs yes 0 5:1 reserved 0-0h 6 bad tlp status 0 = no error detected 1 = error detected rw1cs yes 0 7 bad dllp status 0 = no error detected 1 = error detected rw1cs yes 0 8 replay number rollover status 0 = no error detected 1 = error detected rw1cs yes 0 11:9 reserved 000b 12 replay timer timeout status 0 = no error detected 1 = error detected rw1cs yes 0 31:13 reserved 0-0h register 11-173. fc8h correctable error mask (all ports) bit(s) description type serial eeprom default 0 receiver error mask 0 = error reporting not masked 1 = error reporting masked rws yes 0 5:1 reserved 0-0h 6 bad tlp mask 0 = error reporting not masked 1 = error reporting masked rws yes 0 7 bad dllp mask 0 = error reporting not masked 1 = error reporting masked rws yes 0 8 replay number rollover mask 0 = error reporting not masked 1 = error reporting masked rws yes 0 11:9 reserved 000b 12 replay timer timeout mask 0 = error reporting not masked 1 = error reporting masked rws yes 0 31:13 reserved 0-0h
pex 8524 transparent mode port registers plx technology, inc. 320 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 11-174. fcch advanced error capabilities and control (all ports) bit(s) description type serial eeprom default 4:0 first error pointer identifies the bit position of the first error reported in the uncorrectable error status register. ros yes 1_1111b 5 ecrc generation capable 0 = ecrc generation not supported 1 = ecrc generation supported, but must be enabled ro yes 1 6 ecrc generation enable 0 = ecrc generation disabled 1 = ecrc generation enabled rws yes 0 7 ecrc checking capable 0 = ecrc checking not supported 1 = ecrc checking supported, but must be enabled ro yes 1 8 ecrc checking enable 0 = ecrc checking disabled 1 = ecrc checking enabled rws yes 0 31:9 reserved 0-0h register 11-175. fd0h header log_0 (all ports) bit(s) description type serial eeprom default 31:0 tlp header_0 first dword header. tlp header associated with error. ros yes 0-0h register 11-176. fd4h header log_1 (all ports) bit(s) description type serial eeprom default 31:0 tlp header_1 second dword header. tlp header associated with error. ros yes 0-0h register 11-177. fd8h header log_2 (all ports) bit(s) description type serial eeprom default 31:0 tlp header_2 third dword header. tlp header associated with error. ros yes 0-0h register 11-178. fdch header log_3 (all ports) bit(s) description type serial eeprom default 31:0 tlp header_3 fourth dword header. tlp header associated with error. ros yes 0-0h
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 321 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 12 non-transparent (nt) bridging 12.1 introduction the following are key elements of pex 8524 nt bridging (ntb): device type identification non-transparent port (nt port) reset scratchpad registers doorbell registers bar setup registers address translation 12.1.1 device type identification devices identify themselves by way of the conventional pci csr header class code register. a transparent pci-to-pci bridge identifies itself as a class code 060400h . an nt bridge identifies itself as ?other,? 068000h , with a type 0 header. this identification is consistent with the use of other non-transparent bridges av ailable in the industry. the pci express capability list and capabilities register includes a device/port type field. in this register, a transparent bridge/switc h port identifies itself as an ups tream or downstream port, while an nt bridge/switch nt port identifies itself as a pci express endpoint.
non-transparent (nt) bridging plx technology, inc. 322 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12.1.2 non-transparent port (nt port) reset the section discusses non-transparent mode ex ceptions and enhancements to transparent mode pci express (standard) reset behavior. 12.1.2.1 fundamental reset (pex_perst#) pex_perst# resets all pex 8524 states, including nt port states. all sticky bits and configuration registers in virtual and link spaces are initi alized to default values by this reset. 12.1.2.2 intelligent a dapter mode nt port reset in intelligent adapte r mode, when a hot reset is received by the transparent-side upstream port, the pex 8524 propagates the reset to all transparent downstream ports to reset them, resets the internal fabric and nt port virtual interface states. there is no reset propagation to th e nt port and its link-side remains intact. the pex 8524 supports an option that allows these hot reset conditions at its transparent upstream port to be masked (disabled), by setting the port 0 debug control register upstream port hot reset and link down reset propagation disable bit (offset 1dch [20]). when the nt port link interface receives a hot rese t, the nt port link interface registers are reset. this reset type does not reset the transparent port s nor nt port virtual inte rface. instead, when the nt port link interface receives a hot rese t (or enters the dl _down condition), the pex_nt_reset# signal is asserted low for 1 s. the system can us e this signal to trigger a reset of the entire local subsystem (transparent side). when software writes to the pex 8524 transparent side upstream port bridge control register secondary bus reset bit (offset 3ch [ 22 ]), the resulting secondary bus re set is (as above) propagated to all pex 8524 transparent downstream ports, and th e port states and nt port virtual interface states are reset. 12.1.2.3 dual-host mode nt port reset dual-host mode reset behavior is the same as in intelligent adapter mode, with the following exception ? in dual-host mode, a hot reset received from the active host as seen at the pex 8524 transparent upstream port (or dl_down condition) does not reset the transparent ports, the internal switch-fabric nor the nt port virtual interface. the queues? intern al operation and downstre am ports remain intact, allowing the backup host to take over (as described in section 4.4.2, ?dual-host mode? ). there is no reset propagation onto the nt port. 12.1.2.4 reset propagation reset propagation, during a hot reset or by way of the bridge control register secondary bus reset mechanism is limited to transparent downstream ports. in an nt bridge, this reset cannot be propagated across the bridge (across the nt port). (refer to chapter 5, ?reset and initialization,? for details regarding pex 8524 transparent mode reset behavior.)
february, 2007 scratchpad registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 323 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12.1.3 scratchpad registers scratchpad registers are readable and wr itable from both sides of the nt bridge, providing a generic means for inter-host communicatio ns. a block of eight registers ar e provided, accessible in memory or i/o space from the nt port virtual and link inte rfaces. these registers pass control and status information between virtual and link interface devices or they can be generic r/w registers. reading or writing scratchpad registers does not cause interrupt assertion ? doorbell registers are used for this purpose. 12.1.4 doorbell registers doorbell registers are used to transmit interrupts from one side of the nt bridge to the other. this section describes a typical set of doorbell control registers. a 16-bit software-controlled interrupt request regi ster and associated 16- bit mask register are implemented for the nt port virt ual and link interfaces. these registers can be accessed from the nt port virtual and link interfaces, in memory or i/o space. the doorbell mech anisms consist of the following registers: set virtual interface irq clear virtual interface irq set virtual interface irq mask clear virtual interface irq mask set link interface irq clear link interface irq set link interface irq mask clear link interface irq mask an interrupt is asserted on the nt port virtual interface when one or more of the irq set/clear register bits are set to 1 and their corresponding mask register bits are cleared to 0. the link interface works identically. the interrupt is de-asserted when all set bits are masked or cleared. in a pci express switch, interrupt state transitions (from setting to clearing, or vice versa) result in packets being transmitted upstream on the ap propriate side of the bridge when int x is enabled. standard pci express capability structures allow th ese interrupts to be configured as msi or int x . when msi is enabled, packets are transmitted only when interr upts transition from clear irq to set irq. internally, the set irq and clear irq registers are the same register. one location is used to set bits and the other is used to clear bits. the st atus can be read from either register. the pex 8524 virtual interrupts are also disabled/r emoved when the link to the other device is down.
non-transparent (nt) bridging plx technology, inc. 324 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12.1.5 bar setup registers all nt port virtual and link interface bars incl ude programmable window sizes, with the exception of bar0 and bar1 (on both inte rfaces), which provide memory and/or i/o-mapped access to the csrs. the bar setup registers are used to pr ogram the window size of each bar. a detailed description of the nt po rt virtual and link interface bars follows. 12.1.5.1 nt port virtual interface bars table 12-1 defines the nt port virtual interface bars. table 12-1. nt port virtual interface bars register description bar0 reserved . all pex 8524 port configuration registers are mapped into memory space using transparent upstream port type 1 sp ace bar0 and bar1 registers. the local host, connected to the transparent ports, can use the transparent upstream port bars to access the pex 8524 port configuration registers. bar1 bar1 is reserved . bar2 configured by the nt port virtual interface bar2 setup register. bar2 is always a 32-bit bar and uses direct address translation . bar3 configured by the nt port virtual interface bar3 setup register. bar3 is always a 32-bit bar and uses lookup table-base d address translation described in section 12.1.6.2, ?lookup table- based address translation.? bar4 configured by the nt port virtual interface bar4/5 setup register. bar4 can be implemented as a 32-bit bar or lower half of a 64-bit bar by combining it with bar5. bar4 uses direct address translation . bar5 enabled only when bar4 is configured as a 64-bit bar. holds the upper 32-bit base address of the 64-bit memory address range. the nt port virtual interface bar4/ 5 setup register defines the size. bar5 is not implemented as a 32-bit only bar. bar5 uses direct address translation .
february, 2007 bar setup registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 325 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12.1.5.2 nt port link interface bars table 12-2 defines the nt port link interface bars. 12.1.5.3 bar li mit registers the base address register (bar) address range si ze is a power of two (bars can be assigned only memory resources in ?power of two? granularity). a limit register is used to reduce the address rang e size. when a limit regist er is implemented, the address range extends from the base register to the li mit register, instead of to the base register plus an offset of 2 n ? 1, where n is the number of bits in the offset (as defined by the setup register). the nt port forwards the transacti on when the transaction address falls within the range of the bar lower address limit value to the bar limit register value. if the transaction address is outside this range, the nt port reports an ?unsupported requ est? and discards the transaction. figure 12-1. limit register application table 12-2. nt port link interface bars register description bar0 maps all pex 8524 port confi guration registers into syst em host memory space. bar0 is always enabled. bar1 maps only nt port virtual interface and li nk interface configuration registers into system host i/o space. bars can be di sabled (enabled by default) by the nt port link interface bar0/bar1 setup register. bar2 configured by the nt port link interface bar2/3 setup register. bar2 can be implemented as a 32-bit bar or lower half of a 64-bit bar by combining it with bar3. bar2 uses direct address translation . bar3 enabled only when bar2 is configured as a 64-bit bar. holds the upper 32-bit base address of the 64-bit memory address range. the nt port link interface bar3 setup register defines the size. bar3 is not implemented as a 32-bit only bar. bar3 uses direct address translation . bar4 configured by the nt port link interface bar4/5 setup register. bar4 can be implemented as a 32-bit bar or lower half of a 64-bit bar by combining it with bar5. bar4 uses direct address translation . bar5 enabled only when bar4 is configured as a 64-bit bar. holds the upper 32-bit base address of the 64-bit memory address range. the nt port link interface bar5 setup register defines the size. bar5 is not implemented as a 32-bit only bar. bar5 uses direct address translation . target address map source address map decode window translated base accesses within the window, but above the limit, do not pass through the bridge. base limit
non-transparent (nt) bridging plx technology, inc. 326 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12.1.6 address translation the transparent bridge uses base and limit regist ers in i/o space, non-prefetchable memory space, and prefetchable memory space to map transactions in the downstream direc tion across the bridge. all downstream devices must be mapped in contiguous address regions, such that a single address range in each space is sufficient. upstream mapping is done by way of inverse decode, relative to the same registers. a transparent bridge does not translate the addresses of forwarded transactions/packets. address domain is unique per host. if a transaction originates in one host dom ain and targets a device in another host domain, it must travel through the nt port. if the nt port does not process address translation, the transaction travels to a non-targeted device on a second ho st domain, or is rejected by the nt port upstream bridge. transactions crossing the ad dress domain must be ad dress-translated by the nt port before transmitting the transaction to the target host domain. the nt bridge uses the conventional pci set of bars in its type 0 csr header to define address ranges into the memory space on the other side of th e bridge. bars define resource address ranges that allow transaction forwarding to the opposite (other side) interface. there are two sets of bars ? one each for the virt ual and link interfaces. bars contain a setup and address translation register: bar setup registers enable/disab le the bar and define the address range size and type. certain bars contain a limit register, which is used to re strict its address range size to less than a power of two. bar setup registers must be programmed prior to allowing configuration software to assign a resource for these bars. bar address translation register s must be programmed before generating traffic across the nt port. this programming is typically done by information downloaded from the serial eeprom or by software. the pex 8524 nt port virtual interface supp orts two types of address translation: direct address translation lookup table-based address translation the pex 8524 nt port link interface suppor ts only direct address translation.
february, 2007 address translation expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 327 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12.1.6.1 direct address translation the bar setup registers define a mask that splits the address into an upper base field and a lower offset field. translation then consists of replacing, under the maskable portion of the setup register, the address base bits with the corresponding address translation register bits. figure 12-2 illustrates direct address translation. the device(s) on the originating- host domain can communicate to a single device or multiple devices mapped to consecutive memory address space on the target host domain, by using the direct address translation mechanism. figure 12-3 illustrates the entire address ma p, claimed by the nt port, mapped into the single target device. figure 12-4 illustrates the entire address map claimed by the nt port, mapped into multiple target devices. multiple devices must be in contiguous memory ranges. figure 12-2. direct address translation figure 12-3. nt port mapped into single target device figure 12-4. nt port mapped into multiple target devices source address map target address map base + offset translated base + offset base contents of base translation register nt-port address map target address map 20 mb 52 mb 800 mb 832 mb nt-port address map target address map 20 mb 52 mb 800 mb 832 mb 808 mb 816 mb 824 mb device 1 address map device 2 address map device 3 address map device 4 address map
non-transparent (nt) bridging plx technology, inc. 328 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 address translation example assume the following: 1. nt port virtual inte rface bar2 claims 128 kb memory space. 2. configuration software assigns the 5f00_0000h address value to nt port virtual interface bar2 and it is within the transparent upstream port memory window. 3. device driver software programs the bar2 address translation register to 2754_0000h. the pex 8524 receives a transaction to the nt port virtual interface with address 5f00_0080h. the received transaction address is attaining the nt po rt virtual interface bar2. the pex 8524 claims the transaction and executes the addr ess translation described in figure 12-5 . figure 12-5. address translation example note: nibble boundary-aligned hex address, bar_addr_xlation_reg[31:16], is 0010_0111_0101_0100b (2754h). 31 0 bar2 address translation register 2754h 0000h 2754_0000h 5f00h 0080h 5f00_0080h 2754h 0080h 2754_0080h 31 0 31 0 31 0 31 0 31 0 received tlp address split address into: 1. base ? software programmable portion of bar. 2. offset ? software read-only portion of bar. base drop tlp address base offset base offset translated address with base and offset address after address translation base offset 17 16 17 16 17 16
february, 2007 address translation expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 329 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12.1.6.2 lookup table-based address translation on the nt port virtual interface, bar3 uses a sp ecial lookup table-based address translation for transactions that fall within its window. the nt port virtual interface bar3 setup register defines the lookup table (lut) entry/page size. the nt port virtual interface bar3 size is determined by multiplying the page size by 64. this bar3 setup register defines a mask that splits the tr ansaction address into upper and lower/offset fields. the upper field is further divided into two portions ? the upper portion is termed ?base address? and lower portion is termed ?lookup table index.? the index field loca tion of the received tlp address varies, based on the page size selection. table 12-3 defines the lut entry/page size, corresponding bar size, and bit position of individual fi elds in the received transaction address. figure 12-6 describes the lookup table-based address tr anslation scheme. the received transaction address is divided into three parts, based on the bar setup register. the base address and lut index fields are compared against the ba r. if the transaction address atta ins the bar, the pex 8524 uses the lut index to select the lut entr y. the pex 8524 replaces the base address and lut index with the selected lookup table entry value, if the entry is valid. otherwise, the nt port virtual interface returns an unsupported request (ur) error condition. the pex 8524 pa sses the received transaction address offset into translated addres s offset without modification. applications can use the lookup table-based addr ess translation when the target device?s address range is scattered over 32-bit memory space. the nt port lookup table descriptions are discussed in section 15.13.2, ?nt port virtual interface lookup table-based address translation registers.?
non-transparent (nt) bridging plx technology, inc. 330 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 figure 12-6. lookup table-based address translation table 12-3. received transaction-address breakdown page size (bytes) window size (bytes) base address (bits) lut index (bits) offset (bits) 4k 256k [31:18] [17:12] [11:0] 8k 512k [31:19] [18:13] [12:0] 16k 1m [31:20] [19:14] [13:0] 32k 2m [31:21] [20:15] [14:0] 64k 4m [31:22] [21:16] [15:0] 128k 8m [31:23] [22:17] [16:0] 256k 16m [31:24] [23:18] [17:0] 512k 32m [31:25] [24:19] [18:0] 1m 64m [31:26] [25:20] [19:0] 2m 128m [31:27] [26:21] [20:0] 4m 256m [31:28] [27:22] [21:0] 8m 12m [31:29] [28:23] [22:0] 16m 1g [31:30] [29:24] [23:0] 32m 2g 31 [30:25] [24:0] translated base lookup table . . . translated base addr [index] translated base addr 00h . . 00h 01h 3fh translated base offset base offset index 31 31 0 0 14 13 14 13 2019 translated base addr 01h translated base addr 02h translated base addr 03h translated base addr 3eh translated base addr 3fh
february, 2007 requester id translation expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 331 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12.2 requester id translation configuration, message, an d completion transactions are id-routed instead of address-routed. of these, the nt port forwards only the completion trans action between the two host domains. pci express switches and bridges use the requester id [defin ed in completion transact ion layer packet (tlp) header] to route these packets. the requester id consists of the following: requester?s pci bus number device number function number the completer id consists of the following: completer?s pci bus number device number function number note: the pci bus number is unique for each host domain. figure 12-7 illustrates the memory re quest tlp header format. figure 12-8 illustrates the completion tlp header format. figure 12-7. memory request tlp header format figure 12-8. completion tlp header format 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 byte 0 byte 1 byte 2 byte 3 address[63:32] address[31:0] r r 1st dw be last dw be requester id tag tc r bytes 0-3 type r attr td ep r length bytes 4-7 bytes 8-11 bytes 12-15 fmtx1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 byte 0 byte 1 byte 2 byte 3 r byte count completer id tc r bytes 0-3 type r attr td ep r length bytes 4-7 bytes 8-11 fmt requester id bcm completer r tag lower address
non-transparent (nt) bridging plx technology, inc. 332 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12.2.1 transaction sequence to implement a transaction sequence: 1. requester inserts id information into the memory read tlp that it generates on the initiating host domain. 2. switches and bridges between the transaction initiator and pex 8524 nt port route this memory read tlp based on the address. 3. nt port replaces the memory read tlp requeste r id with its id, and conducts the address translation before it forwards this requester id-translated tlp to the target host domain, because the nt port is the transaction initiator in the target host domain. 4. switches and bridges between the pex 8524 nt port and target device route this memory read tlp, based on the address. 5. when the target device generates the completion tl p, it copies the memory read tlp requester id into the corresponding completion tlp requester id field and inserts its id into the tlp completer id field. 6. switches and bridges between the target device and pex 8524 nt port route the completion tlp, based on requester id information. 7. nt port restores the original re quester id value from the config uration register and implements another requester id and completer id translatio n for the completion tlp before it forwards the completion tlp to the requester-host domain. 8. switches and bridges between the pex 8524 nt po rt and requester route the completion tlp, based on the requester id. 9. requester accepts the comple tion tlp and processes it.
february, 2007 transaction orig inating in local host domain expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 333 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12.2.2 transaction originat ing in local host domain the translation of outgoing reques ts from the nt port virtual inte rface to the nt port link interface uses an 8-entry lut, as discussed in section 15.13.5, ?nt port virtual interface send lookup table entry registers.? each lut entry supports all outgoing requests and any number of outstanding requests made by a single device or function. if a device uses phantom f unction numbers to increase the maximum number of ou tstanding transactions, then each ph antom function consumes a lut entry. the lut must be configured, by a serial eeprom or local firmware, before it is possible to transmit requests to the system domain, which prov ides a measure of security and protection. when a memory request arrives at the nt port virtua l interface, the packet requester id is associated with this lut. if it attains one of the enabled lu t entries, the corresponding entry address (txindex) is inserted into the function number field of the packet?s requester id . conversely, if it does not attain one of the enabled lut entries, an uns upported request completion is returned. at the same time, the contents of the nt port link interface bus number and device number capture registers (the values used during the last cs r write to the port) are copied into the packet requester id bus number and device number fields. a completion, with translated requester id, retu rned from the system domain to the pex 8524, is recognized when its requ ester id bus and device numbers matc h the nt port link interface captured bus and device numbers. (refer to figure 12-9 .) when the original requester id is restored, the following occurs: 1. txindex is retrieved from the function number field of the completion tlp requester id. 2. txindex is used to look up the same 8-entry lut, to restore the original requester id. 3. if the selected entry is valid, the restored requester id is placed into the completion tlp requester field; otherwise, an unexpect ed completion is returned. 4. completion tlp completer id field is replaced by the nt port virtual interface captured bus, device, and func tion numbers. 5. translated completion tlp is forwarded to the original requester in the local domain.
non-transparent (nt) bridging plx technology, inc. 334 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 figure 12-9. requester id translation for request originating in local domain translated requester id in system domain requester id in outgoing request reqbusno [7:0] reqdev no [4:0] reqfun no [2:0] bus number capture register restored requester id in completion in requester?s local domain translation of an outgoing request at originating non-transparent bridge function device number capture register txindex reqbusno [7:0] reqdev no [4:0] reqfun no [2:0] txindex translation of an incoming completion back at originating non-transparent bridge function lut if {busno, devno,funno} hit in lut, use txindex; else return ur source capbus no source capdev tx index busno busno busno devno devno devno funno funno funno 8 entries lut look up requester id based on txindex in packet busno busno busno devno devno devno funno funno funno 8 entries
february, 2007 system host domain transaction originating expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 335 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12.2.3 system host domain transaction originating transactions originating in system host domain use a second lut, with 32 entries, as illustrated in figure 12-10 . this data structure supports up to 32 devices (elsewhere in the system domain) that are transmitting requests through the associated nt port. because the function number is not used in the lut association, a separate lut entry is not required for each requesting or phantom function device. the lut must be configured before transmitting requests through the nt port. this requester registration process, which cannot be accomplished by a peer, is an effective security and protection mechanism. when a request is received from the system domain and routed to the nt port, its requester id is again translated ? bus and device numb ers, but not function number. th e received memory request tlp requester id is associated with this lut, and the address (rxindex) of the corresponding matching entry is substituted into the device number field of the memory request?s tlp requester id field. if no match is found, or the matched entry is not enabled, the request receives a ur response. if a match is found, and matched entry is enable d, the pex 8524 internal virtual pci bus number is copied into the packet requester id?s bus number field. the translated memory request tlp is address-translated and forw arded into the local domain. the pex 8524 internal virtual pci bus number is sufficient to route the completion from the completer back to the nt port in the completer?s domain, becau se the nt port is the only possible requester on the switch internal virtual bus. elsewhere in the pci express hierarchy, the bu s number is sufficient to route the completion back into the switch containing the nt port. the inverse translation occurs when a completion pa sses through the nt bridge from the local domain to the system domain. the rxindex is retrieved from the device number field of the received completion tlp requester id header field, and used to look up the 32-entry lut. the completion tlp requester id , bus number and device number fields are replaced by the decoded lut-entry bus number and device number values if the entry is valid; otherwise, an unexpected completion is returned. the completion tlp completer id is replaced by the nt port link interface captured bus number, captured device number and function number values before forwarding the completion tlp to the system domain.
non-transparent (nt) bridging plx technology, inc. 336 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 figure 12-10. requester id translation for request originating in system domain requester id in outgoing completion in system domain reqbusno [7:0] reqdev no [4:0] reqfun no [2:0] requester id in incoming request from host or device in system domain reqbusno [7:0] reqdev no [4:0] reqfun no [2:0] translated requester id in target?s local domain host switch virtbusno [7:0] translation of an incoming request at target non-transparent bridge function t r a n s l a t i o n o f a n o u t g o i n g c o m p l e t i o n a t t a r g e t n o n - t r a n s p a r e n t b r i d g e f u n c t i o n funno [2:0] {busno, devno} rxindex rxindex {busno, devno} rxindex lut use rxindex to look up reqbusno and reqdevno lut if {busno, devno} hit in cam, use rxindex; else return ur busno devno busno devno busno devno busno devno busno devno busno devno 32 entries 32 entries
february, 2007 nt port po wer management handling expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 337 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12.3 nt port power management handling 12.3.1 active-state power management (aspm) when nt mode is enabled (intelligent adapter or dual-host mode), the pex 8524 does not enter into active power management states l0s and l1 on any of its ports, although the pex 8524 nt link interface type 0 endpoint, nt virtual interface type 0 endpoint, and transparent type 1 ports are enabled for aspm by programming the link control register active state power management (aspm) control field. the pex 8524 nt link interface type 0 endpoint and transparen t upstream port do not enter l0s nor request an aspm l1 entry on its tran smit direction. similarly, the pex 8524 transparent downstream ports do not enter l0s on their transmit direction. if an aspm l1 request is received on a pex 8524 transparent downstream port, a pm_activ e_state_nak message is transmitted downstream, irrespective of the link control register active state power management (aspm) control field value. the pex 8524 allows all ports to recei ve a lane entry to the l0s state. 12.3.2 pci-pm and pme turn off support when nt mode is enabled, the nt port link inte rface type 0 endpoint behaves as other endpoints in the d3hot pci-pm power states. on ce in the d3hot state, the pex 8524 nt port link interface type 0 endpoint requests pci_pm l1 entry and finally settles in the l1 link state. only configuration accesses and messages to the nt port link interface type 0 endpoint are supported in the d3hot state. nt host software can transmit pme_turn_off messages when the nt host decides to turn off the main power and main reference clock. the pex 8524 nt link in terface type 0 endpoint indicates its readiness to lose power by transmitting a pme_to_ack message toward the upstream device. the pme_to_ack message is transmitted when there is no pending tlp waiting to be transmitted in the pex 8524 nt port link interface upstream dir ection. the port requests the l2/l 3 ready state, by transmitting pm_enter_l23 dllp to the upstream device after transmitting pme_to_ack tlp. the port settles into the l3 link state when the power controller removes the main power and reference clock. when the pme_turn_off message is received on the pex 8524 transparent upstream port, the port broadcasts this message to all pex 8524 downstream devices, including the nt port virtual interface type 0 endpoint. after the pme_to_ack message is received from all down stream devices and from the pex 8524 nt port virtual interface type 0 e ndpoint, the pex 8524 transparent upstream port transmits an aggregated pme_to_ack message to the upstream componen t after it finishes transmitting all pending tlps to the upstream co mponent. when nt mode is en abled, the pex 8524 transparent downstream ports allow the attached devices to enter the pci-pm-compatible l1 state. the pex 8524 nt port virtual interface type 0 endpoint never enters the pci-pm l1 state. 12.3.3 message generation the pex 8524 nt port link interface type 0 end point never generates pm_pme messages. the pex 8524 nt port virtual interface type 0 endpoint never receives set_slot_power_limit messages and never generates pm_pme messages.
non-transparent (nt) bridging plx technology, inc. 338 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12.4 nt hot plug support the pex 8524 transparent downstream ports, with nt m ode enabled, behave in the same way when nt mode is disabled. the pex 8524 nt port virtual interface type 0 endpoint never receives nor generates hot plug messages. the pex 8524 nt port link interface type 0 endpoint generates and receives hot plug messages that an endpoint (o r switch upstream port) receives/generates. the pex 8524 nt port link interface t ype 0 endpoint and transparent ups tream port implements hot plug client features. attention button present device, attention indicator present device, and power indicator present device registers and their functionality are implemented on the pex 8524 nt port link interface type 0 endpoint and pex 8524 do wnstream ports. the pex 8524 nt port virtual interface type 0 endpoint does not implement hot plug control nor hot plug client functionality, because it is an endpoint device no t connected to a physical link. figure 12-11. sample intelligent adapter mode hot plug view local host downstream port 1 downstream port 11 downstream device downstream device system host downstream device pci bus virtual pci bus nt port 8 link side nt bridge downstream port 9 hot plug controller hot plug controller hot plug controller hot plug device hot plug client hot plug controller hot plug client upstream port number register (port 0) hot plug device hot plug device virtual side nt bridge type 0 type 0 type 1 idle upstream port 0 (t)
february, 2007 nt hot plug support expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 339 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 figure 12-12. sample dual-host mode hot plug view active host downstream port 1 downstream port 11 downstream device downstream device backup host downstream device pci bus virtual pci bus nt port 8 link side nt bridge downstream port 9 hot plug controller hot plug controller hot plug controller hot plug device hot plug device hot plug controller hot plug client upstream port number register (port 0) hot plug device hot plug device virtual side nt bridge type 0 type 0 type 1 idle upstream port 0 (t)
non-transparent (nt) bridging plx technology, inc. 340 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 12.4.1 hot plug sequence during host-failover hot plugging the complete active host domain into the backup host is similar to hot plugging the endpoint device into the downstream port of a switch or root port. if the backup host is dead, it is not a problem. if the active host is dead, the backup host first completes the hot plug insertion sequence before it starts the failover sequence. the active host can service none or a portion of the hot plug sequence on a transparent downstream port and dies before servicing the remaining sequence. the downstream port hot plug controller module previously transmitted an interrupt for the next hot plug sequence to the failed transparent upstream port and it did not receive service from faile d active host. the backup host disables ?msi and int x interrupt generation? before it starts the failov er sequence. after the backup host finishes the failover sequence, it enables ?msi and/or int x interrupt generation? for the transparent downstream port. this interrupt generation re -enabling generates interrupt asse rtion messages (or msi) to the self-promoted backup (active) host. the self-promo ted backup (active) host continues the remaining hot plug insertion/removal sequen ce from the failed active host.
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 341 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 13 nt port interrupts 13.1 introduction nt port virtual and link sides can generate msi or int x interrupts, which are enabled by the command register interrupt disable or message control register msi enable bits (offsets 04h [ 10 ] or 48h [ 16 ], respectively). because they are endpoints, the nt port virtual and link sides cannot receive interrupt messages; therefore, if an interrupt message is received, it is reported as an error condition. the nt port virtual side generates interrupts to th e local host/active host for device-specific errors reported by nt port egress modules or doorbell interrupts. the nt port link side generates interrupts to the sy stem/inactive secondary ho st when device-specific errors are reported by nt port ingress modules. 13.2 doorbell interrupts by default, all interrupt sources are masked. if software processes an interrupt, it first clears the interrupt mask register for the interrupt source. the asserted int x virtual wires are de-asserted, when the software clears the ev ent status bit that caused the assertion. the interrupt handler has two set of registers ? one set for virtual side type 0 configuration space and another set for link side type 0 configuration space of the nt port. further details regarding msi and intx interrupts are provided in chapter 6, ?interrupts.?
nt port interrupts plx technology, inc. 342 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 13.3 doorbell registers a 16-bit software-controlled interrupt request register and associated 16-bit mask register are implemented for the nt port virt ual and link interfaces. these regi sters can be accessed from the nt port virtual or link interface, in memory or i/ o space. the doorbell mechanisms consist of the following registers: set virtual interface irq clear virtual interface irq set virtual interface irq mask clear virtual interface irq mask set link interface irq clear link interface irq set link interface irq mask clear link interface irq mask an interrupt is asserted on the nt port vi rtual interface when one or more of the irq set/clear register bits are set to 1 and their corresponding mask register bits are cleared to 0. the nt port link interface works identically. the inte rrupt is de-asserted when all se t bits are masked or cleared. the irq set/clear registers are internally the same physical interrupt request register, which includes two separate dwords ? one dword is used to set bits, the other is used to clear bits. the status can be read from either register. the irq set/clear mask registers are also internal ly the same register ? one interface is used to set a mask register bit, the other is used to clear a mask register bit.
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 343 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 14 non-transparent bridging software architecture 14.1 introduction this chapter focuses on system configuration and data transfer through the nt port. the pex 8524 supports two types of nt modes: intelligent adapter dual-host the nt port and nt-mode type are described in chapter 12, ?non-transparent (nt) bridging.? the pex 8524 nt feature and mode (intelligent adap ter or dual-host) are enabled using board-level strapping balls. the pex 8524 requires software support for the following: system configuration data transfer through nt port quality of service (qos) management in a switch performance tuning in a switch interrupt service routine hot plug routine power management routine error handling routine 14.2 system configuration the pci express configuration model su pports two configuration mechanisms: pci-compatible configuration pci express-enhan ced configuration the pci-compatible mechanism supports 100% binary compatibility with the pci r2.3 or later operating systems and corresponding bus enumeration and configuration software. the pci express-enhanced mechanism is provided to increase the size of available configuration space and optimize configuration mechanisms.
non-transparent bridging software architecture plx technology, inc. 344 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 14.2.1 pex 8524 intelligent adapter mode figure 14-1 describes a sample system view with pex 8524 nt intelligent adapter mode enabled. the pex 8524 transparent ports are pci-to-pci bridges, and the pex 8524 nt port is two type 0 endpoint devices connected back-to-back. pci express devices must include an assigned unique id (bus, device, and function numbers). each pex 8524 transparent port has its own 4-kb pc i express configuration registers and the nt port includes an 8-kb configuration space ? 4 kb for th e nt port virtual interface type 0 endpoint and another 4 kb for the nt port link interf ace type 0 endpoint. at power-up, one of pex 8524 ports is selected as the upstream port and one of pex 8524 downstream ports is selected as the nt port, using boa rd-level strapping balls or a serial eeprom. the bios running in the local host configures th e pex 8524 upstream port, downstream ports, and nt port virtual interface type 0 endpoint. the bios running in the system host configures the nt port link interface type 0 endpoint. the local host-connected root complex initiates a type 0 configuration request to configure only the pex 8524 upstream port and initiates type 1 config uration requests to configure the pci express hierarchy behind the pex 8524 upstream port, including the pex 8524 nt port virtual interface type 0 endpoint. the local host is not allowed to configure the nt port link interface type 0 endpoint using type 0/type 1 configuration requests. the system host-connected root complex initiates a type 0 configuration request to configure only the pex 8524 nt port li nk interface type 0 endpoin t. if this root complex initiates type 1 configuration requests, the nt port link interface t ype 0 endpoint rejects the cycles as unsupported request (ur) errors. figure 14-1. sample system configuration with non-transparent pex 8524 p-p p-p p-p p-p p-p endpoint endpoint endpoint endpoint endpoint endpoint configuration to transparent domain and nt port virtual interface configuration to nt port link interface local host memory memory root port root port system host root complex root complex upstream port downstream p-p bridges upstream p-p bridge downstream ports nt port nt port virtual interface nt port link interface
february, 2007 pex 8524 intelligent adapter mode expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 345 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 nt port virtual and link interface type 0 endpoint ba r2 through bar5 are disa bled, by default. each bar includes a corresponding bar setup register. th is bar setup register controls the corresponding bar, in the following manner: 1. enables/disables bar. 2. programs bar size. 3. maps bar group into 32- or 64-bit address space. 4. maps bar into prefetchable or non-prefetchable memory space. refer section 12.1.5, ?bar setup registers,? for a detailed description of bars and bar setup registers. use a serial eeprom to enable the necessary bars for inter-host-domain traffic by default; otherwise, system software/bios and device dr iver software must work togeth er to enable the nt port type 0 endpoint bars before assigning resources to the bars. the pex 8524 implements the following two configuration register bits to take advantage of software layer resource assignment for th e nt port. the nt port includes debug control register link interface access enable and virtual interface access enable device-specific configuration register bits, mapped to pex 8524 port 0, at offset 1dch [29:28], respectively. by default, the virtual interface access enable configuration bit is set to 1, and the link interface access enable configuration bit is cleared to 0. the serial eeprom overrides these default values. if the virtual interface access enable configuration bit is cleared to 0, the nt port virtual interface type 0 endpoint returns a ?configuration retry stat us (crs)? response (completion with crs status) for the received configur ation request from the local host. otherwise, it accesses the corresponding configuration registers. if the link interface access enable configuration bit is cleared to 0, the nt port link interface type 0 endpoint returns a ?configuration retry status (crs)? response (com pletion with crs status) for the received configuration request from the system host. otherwise, it accesses the corresponding configuration registers.
non-transparent bridging software architecture plx technology, inc. 346 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 14.2.2 sample pex 8524 configuration steps the pex 8524 can be configured using a serial eeprom or software. to configure the pex 8524: 1. select pex 8524 operating mode: a. use strap_mode_sel[1:0] balls to select pex 8524 operating mode. (refer to table 3-7, ?pex 8524vaa/bb/bc strapping signals, 680-ball pbga ? 24 balls,? or table 3-14, ?pex 8524bb/bc strapping signals, 644-ball pbga ? 24 balls,? for the operating mode encoding values.) b. serial eeprom is used to override the strapping ball selection. 2. select port configuration: a. select strap_stn0_portcfg[4:0] for pex 8524 station 0 port configuration, and strap_stn1_portcfg[3:0] for pex 8524 station 1 port configuration. (refer to table 4-1, ?pex 8524 port configurations,? for the strapping ball encoded values.) b. serial eeprom is used to override the strapping ball selection. 3. select upstream port: a. strap_upstrm_portsel[3:0] selects one of pex 8524 ports as an upstream port. b. serial eeprom is used to override the strapping ball selection. 4. nt port selection: a. strap_nt_upstrm_portsel[3:0] selects one of the pex 8524 downstream ports as an nt port. b. serial eeprom is used to override the strapping ball selection. 5. power-up the system. 6. software enumeration directives: a. locating root port devices and root complex integrated endpoint devices within a root complex are impl ementation-specific. b. root complex is allowed more than one root port. c. pci express hierarchy starts from root complex root port. d. local host bios and system host bios scans the device presence behind root port, using type 0 configuration request. e. bios reads key configuration registers ( for example , header type , class code , pci express device/port type field, and so forth) to lo cate the device and header types. f. pex 8524 nt port link interface type 0 endp oint responds to the configuration access with crs, as its ?link in terface access enable,? is disabled by default. g. system host connected root complex later retries this configuration request to the pex 8524 nt port link interface type 0 endpoint. h. pex 8524 nt port link interface type 0 endp oint continues to retry the configuration request until it comprehends that ?li nk interface access enable? is enabled. i. pex 8524 upstream port accesses the corres ponding configuration registers and returns a successful completion. j. bios detects a pci-to-pci bridge device behind local host connected root complex and programs the pex 8524 upstream port primary bus number , secondary bus number , and subordinate bus number registers. k. bios commences scanning devices behind the pex 8524 upstream port, using a type 1 configuration request.
february, 2007 sample pex 8524 configuration steps expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 347 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 l. if the received type 1 configuration request bus number is equal to the pex 8524 upstream port secondary bus number register value, and the type 1 configuration request device number is equal to the down stream port number or nt po rt number, pex 8524 accesses the corresponding port configuration register. (d ownstream ports ?port number? and nt port ?port number? are equal to device number on the pex 8524 internal pci bus. nt port virtual interface type 0 endpoint device number is the nt port ?port number? and nt port link interface type 0 endpoint device number is the device number assigned by the upstream device.) m. if bios locates a pci-to-pci device (downstr eam port) on the pex 8524 internal pci bus, it commences the depth-first device scan behind the pex 8524 downstream port, by programming pex 8524 downstream port?s primary bus number , secondary bus number , and subordinate bus number registers. n. pex 8524 upstream port rout es received type 1 configur ation request to a pex 8524 downstream port, if the received type 1 configur ation request bus number is greater than the pex 8524 upstream port secondary bus number and less than or equal to pex 8524 upstream port subordinate bus number, as well as within the pex 8524 downstream port secondary bus number and subordinate bus number window. o. if the received type 1 configuration request bus number is equal to pex 8524 downstream port secondary bus number, the pex 8524 downstream converts this type 1 configuration access to a type 0 configuration access, if the type 1 configurat ion request device number is 0. if the type 1 configuration request device number is non-zero, the pex 8524 downstream port returns an unsupported request (ur) error. p. if the received type 1 configuration request bus number is greater than the pex 8524 downstream port secondary bus number and less than or equal to the pex 8524 downstream port subordinate bus number, the pex 8524 downstream port forwards this type 1 configuration request to the downstream device, unmodified. q. if bios locates an nt port virtual interf ace type 0 endpoint of the pex 8524 internal pci bus, it stops scanning behind the nt port, because it is an endpoint and the pci express hierarchy ends in an endpoint. r. after locating all devices within the pci ex press hierarchy, bios commences resource assignment ( for example , memory, i/o, and/or interrupt resource). s. if the application is not using a serial eepr om, system software/bios requires modification to implement the following: ? assign a memory, i/o, and/or interrupt resource to the pex 8524 upstream port bar0 (memory bar) or pex 8524 nt port virtual interface bar1 (i/o bar) before assigning memory resources to pex 8524 nt port virt ual interface type 0 endpoint bar2 to bar5 ? use memory/i/o-mapped cycle (refer to section 15.2, ?register access,? for details) to program the pex 8524 nt port virtual interface type 0 endpoint bar setup register ? assign a resource to the pex 8524 nt po rt virtual interface type 0 endpoint t. use memory/i/o-mapped cycle to program the nt port link interface type 0 endpoint bar setup register. u. use memory-mapped cycle to enable link interface access enable configuration bit. v. after enabling the pex 8524 nt port link interface type 0 endpoint, system host bios is allowed to enumerate and assign a resource to the pex 8524 nt port link interface type 0 endpoint. w. use a memory/i/o-mapped cycle to program the pex 8524 nt port type 0 endpoint address translation regist ers. (refer to chapter 15, ?nt port virtual interface registers,? and chapter 16, ?nt port link interface registers,? for details.)
non-transparent bridging software architecture plx technology, inc. 348 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 x. use memory/i/o-mapped cycle to program the pex 8524 nt port type 0 endpoint bar limit registers if application is to effici ently use the memory resource. (refer to chapter 15, ?nt port virtual interface registers,? and chapter 16, ?nt port link interface registers,? for details.) y. use memory/i/o-mapped cycle to program the pex 8524 nt port type 0 endpoint ?send lut entry? and ?receive lut entry? registers. (refer to chapter 15, ?nt port virtual interface registers,? and chapter 16, ?nt port link interface registers,? for details.) 14.2.3 pex 8524 dual-host mode pex 8524 nt dual-host mode is similar to the pex 8524 nt intelligent adapter mode, except the default values of the nt port link interface access enable and virtual interface access enable bits (offset 1dch [29:28], respectively) are set to 1. both hosts connected to the pex 8524 upstream port and nt port link interface type 0 endpoint can concur rently enumerate the de vices. the pex 8524 does not generate a crs response in nt dual-host mode. 14.2.4 host-failover application the host-failover application is based on the basic dual-host configuration, and dynamic swapping of the upstream and nt ports is supported on ports 0 and 8. the active host periodically transmits heartbeat messages, by way of the pex 8524 to th e backup host, to indicate that it remains active. when the backup host fails to receive heartbeat messa ges before its fail detect timer expires, it starts the failover process. the backup host halts cross- domain traffic before it starts the failover. the backup host uses the memory-mapped access to the pci express capabilities register (offset 68h ) to execute the failover. the backup host foll ows the ensuing procedure to take control: 1. failover detected: a. backup host detects the active host?s failur e condition, then starts the failover process ( such as , heartbeat message reception timeout). b. upstream port remains active in this state. 2. upstream port demotion: a. pex 8524 is not in reset when the failover process starts. b. debug control register upstream port hot reset and link down reset propagation disable bit (port 0, offset 1dch [ 20 ]) can disable reset generation due to a hot reset and the upstream port dl_down condition. the bit is asserted, by default, for dual-host mode. c. silicon revisions bb/bc only ? the serial eeprom must be programmed with the port 0, offset 1dch, value in port 0 and th e nt port virtual interface, and the ingress control register bios enumeration fix disable bit ( 660h [ 27 ]) must be set to 1. d. as one of the first steps in the failover pr ocess, the backup host demotes the upstream port by writing 0000b into the pci express capabilities register (pci express endpoint) device/port type field (offset 68h [ 23:20 ]). e. transaction layer ingress sno ops this access and informs event d detection to the tlp-destined transparent upstream port. f. event e causes the upstream port physical layer to bring down its upstream link, which generates the upstream port dl_down condition. g. event e also causes the upstream port to change its device/port type field to ?pci express endpoint?, and changes the pci class code to ?other bridged de vices?. the transparent upstream port becomes a pci express endpoint. h. upstream port transaction layer egress module drops all outgoing packets to the upstream device when it comprehends the upstream port dl_down condition. i. debug control register upstream port number and nt port number fields (offset 1dch[11:8 and 27:24], respectively) remain unchanged in this state.
february, 2007 host-failover application expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 349 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 j. downstream port internal modules forward/ge nerate the packet for the upstream device, which is transmitted to the previous upstream port, and the packets are dropped by the demoted upstream port transaction layer egress module due to this dl_down condition. k. when a transaction layer ingress module receives tlps from the demoted upstream connected device, the module processes the normal upstream port type of address decoding and forwards the packet to the destination port, based on amcam, iocam, or busnocam lookup. 3. nt port (self) promotion as a new upstream port: a. software can disable the i/o access enable , memory access enable , bus master enable , interrupt generation on the nt port virtual interface, and error message generation enable csr bits, if it does not want to receive spur ious traffic immediately after self-promotion. refer to the pci-to-pci bridge r1.1 command register for these csr descriptions and the device control register for error message generation enable csr bits. b. backup host promotes itself as an active host by writing 0101b into the nt port virtual interface type 0 configuration pci express capabilities register (transparent upstream port) device/port type field (offset 68h [ 23:20 ]). c. pex 8524 swaps the debug control register upstream port number and nt port number fields (offset 1dch[11:8 and 27:24], respectivel y) values when a transaction layer ingress informs event b of this condition. d. pex 8524 processes the port transition. pex 852 4 converts the demoted transparent upstream port to the nt port, and the previous nt port to the transparent upstream port. e. new upstream port retrieves previously programmed nt port virtual interface type 0 csr values. f. pex 8524 does not swap the configuration space value from previous upstream port to new upstream port by itself after failover. software running in promoted active host should follow the ensuing procedure to bring the system into a co mmunicating state: ? copy the previous upstream port configuration space value to a new upstream port configuration space value. ? copy the previous nt port virtual inte rface type 0 endpoint configuration space value to a new nt port virtual interface type 0 endpoint configuration space value. ? if possible, reset the entire hierarchy a nd restart the system, using full software re-enumeration.
non-transparent bridging software architecture plx technology, inc. 350 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 14.3 data transfer through nt port the following discusses the configuration registers mainly programmed for data transfer through the nt port. to transfer data from nt port virtual interface to nt port link interface direction: 1. assign memory space to nt port virtual interface type 0 endpoint bars. 2. enable nt port virtual interface type 0 endpoint memory access enable bit (offset 04h [1]). 3. enable nt port link inte rface type 0 endpoint bus master enable bit (offset 04h [2]). 4. program nt port virtual interface type 0 endpoint address translation regi sters with transaction completer (target) bar value. if the application is using lookup table-ba sed address translation, it must enable the corresponding lut entry as we ll. address translation register values can be dynamically changed by a device driver, dependin g on where the requester is located. before changing the address translation register values, the device driver must ensure an outstanding request is not pending to the nt port. 5. enable and program nt port virtual interface ?s end lut entry? registers with requester id (bus, device, and function numbers). ?send lut entry? register values can be dynamically changed by a device driver, depending on the request enabled to communicate through the pex 8524 nt port. before changing the ?send lut entry,? the device driver must ensure an outstanding request is not pending for that requester. to transfer data from nt port link interface to nt port virtual interface direction: 1. assign memory space to nt port link interface type 0 endpoint bars. 2. enable nt port link inte rface type 0 endpoint memory access enable bit (offset 04h [1]). 3. enable nt port virtual interface type 0 endpoint bus master enable bit (offset 04h [2]). 4. program nt port link interface type 0 endpoint ad dress translation registers with transaction completer (target) bar value. address translation register values can be dynamically changed by a device driver, depending on where the requester lo cated the virtual link side. before changing the address translation register values, the device dr iver must ensure an outstanding request is not pending to the nt port. 5. enable and program nt port link interface ?receive lut entry? registers with requester bus number and device number values. ?receive lut entry? register values can be dynamically changed by a device driver, depending on the request enabled to communicate through the pex 8524 nt port. before changing the ?receive lut entry,? the device driver must ensure an outstanding request is not pending for that requester.
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 351 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 15 nt port virtual interface registers 15.1 introduction this chapter defines the registers for the pex 8 524 non-transparent (nt) port virtual interface (interface) registers. the nt port includes two sets of configuration, capability, control, and status registers to support the virtual and link interfaces. nt port virtual interface register mapping is defined in table 15-1 . nt port link interface registers are defined in chapter 16, ?nt port li nk interface registers.? transparent mode registers are defined in chapter 11, ?pex 8524 transpar ent mode port registers.? for further details regarding register names and descriptions, refer to the following specifications: pci r2.3 pci power mgmt. r1.1 pci express base r1.0a
nt port virtual interface registers plx technology, inc. 352 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 table 15-1. nt port virtual interface type 0 register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 00h ? configuration header registers new capability pointer (40h) 34h ? 3ch next capabili ty pointer ( 48h ) capability id ( 01h ) 40h power management capability registers 44h next capability pointer ( 68h ) capability id ( 05h ) 48h message signaled interrupt capability registers ? 64h next capability pointer ( 00h ) capability id ( 10h ) 68h pci express capability registers ? 80h reserved 84h ? 8ch nt port registers 90h ? ffh next capability offset ( fb4h ) 1h extended capability id ( 0003h ) 100h device serial number exte nded capability registers 104h 108h reserved 10ch ? 134h next capability offset ( 148h ) 1h extended capability id ( 0004h ) 138h power budgeting extended capability registers ? 144h next capability offset ( 000h ) 1h extended capability id ( 0002h ) 148h virtual channel extended capability registers ? 1c4h plx-specific registers 1c8h ? c08h pex 8524 non-transparent bridging-specific registers c3ch ? fb0h next capability offset ( 138h ) 1h pci express extended capability id ( 0001h )fb4h advanced error reporting capability registers ? ffch
february, 2007 register access expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 353 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.2 register access the pex 8524 nt port virtual interface implements a 4-kb configuration space. the lower 256 bytes (offsets 00h through ffh) is the pci-compatible configuration space, and the upper 960 dwords (offsets 100h through fffh) is the pci e xpress extended configurati on space. the pex 8524 supports four mechanisms for accessing nt po rt virtual interface registers: pci express base r1.0a configuration mechanism plx-specific memory-mapped configuration mechanism plx-specific i/o-mapped co nfiguration mechanism plx-specific cursor mechanism 15.2.1 pci express base r1.0a configuration mechanism the pci express configuration mechanism is divided into two mechanisms: pci r2.3 -compatible configuration pci express enhanced configuration the pci r2.3 -compatible configuration mechanism provides standard access to the first 256 bytes (the bytes at offsets 00h through ffh) of the nt po rt virtual interface configuration register space. the pci express enhanced configuration mechanis m provides access to the remaining 4 kb (offsets 100h through fffh). 15.2.1.1 pci r2.3 -compatible configuration mechanism the pci r2.3 -compatible configuration m echanism provides standard access to the pex 8524 nt port virtual interface?s first 256 bytes (the bytes at offsets 00h through ffh) of the pci express configuration space. (refer to figure 15-1 .) this mechanism is used to access the pex 8524 nt port virtual interface type 0 (pci endpoint) registers: configuration header registers power management capability registers message signaled interrupt capability registers pci express capability registers the pci r2.3 -compatible configuration mechanism uses pci type 0 and type 1 configuration transactions to access the pex 85 24 configuration registers. the pex 8524 upstream port captures the bus and device numbers assigned by the upstream device on the pci expr ess link attached to thepex 8524 upstream port, as required by the pci express base r1.0a . the pex 8524 decodes all type 1 conf iguration accesses received on its up stream port, when any of the following conditions exist: if the bus number specified in the configuration access is the nu mber of the pex 8524 internal virtual pci bus, the pex 8524 au tomatically converts the type 1 configuration access into the appropriate type 0 configuratio n access for the specified device. ? if the specified device corresponds to the nt port virtual interface (or to the pci-to-pci bridge in one of the pex 8524 downstream transparent ports), the pex 8524 processes the read or write request to the downstream po rt register specified in the original type 1 configuration access. ? if the specified device number does not correspond to any of the pex 8524 downstream port device numbers, the pex 8524 responds with an unsupported request (ur).
nt port virtual interface registers plx technology, inc. 354 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 because the pci r2.3 -compatible configuration mechanism is limited to the first 256 bytes of the nt port virtual interface configur ation register space, one of the following must be used to access beyond byte ffh: pci express enhanced configuration mechanism plx-specific memory-mapped configuration mechanism plx-specific cursor mechanism the pci r2.3 -compatible configuration mechanism us es the same request format as the pci express enhanced configuration mechanism . for pci-compatible configuration requests, the extended register address field mu st be all zeros (0). do not use this mechanism to access the pe x 8524 device-specific configuration registers. 15.2.1.2 pci express enhanced configuration mechanism the pci express enhanced configuration mechan ism uses a flat, root complex memory-mapped address space to access device config uration registers. in this case, the memory address determines the configuration register accessed, and the memory data returns the addressed register?s contents. the root complex converts the memory transaction into a configuration transaction. this mechanism is used to access the nt port virtual interface type 0 registers: configuration header registers power management capability registers message signaled interrupt capability registers pci express capability registers device serial number extended capability registers power budgeting extended capability registers virtual channel extended capability registers advanced error reporting capability registers do not use this mechanism to access the pe x 8524 device-specific configuration registers.
february, 2007 plx-specific memory-mapped configuration mechanism expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 355 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.2.2 plx-specific memory-m apped configuration mechanism the plx-specific memory-mapped configuration mechanism provides a method to access the pex 8524 port configuration registers of all ports in a single memory map, as illustrated in figure 15-1 . the registers of each port are contained within a 4-kb range. when the nt port is enabled at fundamental rese t, the nt port virtual interface and link interface configuration registers are used in place of th e type 1 configuration registers for that port. to utilize the plx-specific memory-map ped configuration mechanism, use the pci r2.3 -compatible configuration mechanism to prog ram the pex 8524 upstream port base address 0 and base address 1 registers. after the pex 8524 upstream po rt memory-mapped register base address is set, the upstream port register is accessed with memo ry reads from and writes to the configuration space registers. the nt port registers are accessed with memory reads from and writes to the 4-kb range, starting at offset 64 kb for the virtual interface registers and of fset 68 kb for the link interface registers. this mechanism is used to access al l pex 8524 configuration registers. figure 15-1. pex 8524 register offset from upstream port bar0/1 base address (non-transparent mode) port 0 port 1 reserved port 8 port 9 port 10 port 11 reserved reserved pex 8524 nt port virtual interface nt port link interface 0 kb 4 kb 8 kb 32 kb 36 kb 40 kb 44 kb 48 kb 64 kb 72 kb 68 kb 128 kb
nt port virtual interface registers plx technology, inc. 356 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.2.3 plx-specific i/o-map ped configuration mechanism the first 256 bytes of nt port virtual interface co nfiguration space registers are directly accessible by i/o transaction. the nt port virt ual interface bar1 register is used for i/o-mapped access. (refer to figure 15-2 .) extended configuration space re gisters are accessed by using the cursor mechanism in i/o space. figure 15-2. i/o-mapped configuration space view 15.2.4 plx-specific cursor mechanism in figure 15-2 , the software uses the configuration address window (cfgaddr) register to point to the nt port virtual or link interface config uration space registers, including the extended space register. software uses the configuration data window (cfgdata) register to write to or read from the selected configurat ion space registers. refer to section 15.8.4, ?nt port cursor mechanism control registers,? for the register descriptions. 15.3 register descriptions the remainder of this chapter details the pex 8 524 nt port virtual interface registers, including: bit/field names description of register functions in the pex 8524 nt port virtual and link interfaces type ( such as rw or hwinit; refer to table 11-3, ?register types, grouped by user accessibility.? for type descriptions) whether the power-on/reset value can be modified, by way of the pex 8524 serial eeprom initialization feature default power-on/reset value cfgaddr cfgdata 00h f4h f8h fch 100h ffch pci-compatible configuration space extended configuration space bar1 (i/o bar) 31 0 7 32 bits
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 357 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.4 configuration header registers table 15-2. type 0 configuration space header register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 device id vendor id 00h status command 04h class code revision id 08h bist (not supported) configuration layout type and function type master latency timer cache line size 0ch reserved 10h base address 1 14h base address 2 18h base address 3 1ch base address 4 20h base address 5 24h reserved 28h subsystem id subsystem vendor id 2ch reserved 30h reserved new capability pointer (40h) 34h reserved 38h reserved interrupt pin interrupt line 3ch register 15-1. 00h product identification bit(s) description type serial eeprom default 15:0 vendor i d unless overwritten by the serial eeprom, returns the plx pci-sig-assigned vendor id. the pex 8524 serial eeprom register initialization capability is used to replace the plx vendor id with another vendor id. hwinit yes 10b5h 31:16 device id unless overwritten by the serial eeprom, 8532h is returned by the pex 8524v and 8524h is returned by the pex 8524, the plx-assigned device id. th e serial eeprom register initialization capability is used to replace the plx-assigned device id with another device id. hwinit yes 8532h (pex 8524v) 8524h (pex 8524)
nt port virtual interface registers plx technology, inc. 358 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-2. 04h status/command bit(s) description type serial eeprom default command 0 i/o access enable 0 = pex 8524 ignores i/o requests on the nt port virtual interface 1 = pex 8524 accepts i/o requests receiv ed on the nt port virtual interface rw yes 0 1 memory access enable 0 = pex 8524 ignores memory request s on the nt port virtual interface 1 = pex 8524 accepts memory request s received on the nt port virtual interface rw yes 0 2 bus master enable controls memory reque st forwarding in the upstream direction. does not affect message forwarding nor completi ons in the upstream direction. 0 = pex 8524 handles memory requests re ceived on the nt port?s link interface as unsupported requests (ur); for non- posted requests, pex 8524 returns a completion with ur completion status 1 = pex 8524 forwards memory requests in the upstream direction rw yes 0 3 special cycle enable cleared to 0, as required by the pci express base r1.0a . ro no 0 4 memory write and invalidate cleared to 0, as required by the pci express base r1.0a . ro no 0 5 vga palette snoop cleared to 0, as required by the pci express base r1.0a . ro no 0 6 parity error response enable controls the master data parity error . rw yes 0 7 idsel stepping/wait cycle control cleared to 0, as required by the pci express base r1.0a . ro no 0 8 serr# enable controls the signaled system error bit. when 1, enables reporting of fatal and non-fatal errors detected by the nt port virtual interface to the root complex. rw yes 0 9 fast back-to-back transactions enabled cleared to 0, as required by the pci express base r1.0a . ro no 0 10 interrupt disable 0 = nt port virtual interfac e enabled to generate int x interrupt messages 1 = nt port virtual interface prevented from generating int x interrupt messages rw yes 0 15:11 reserved 00h
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 359 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 status 18:16 reserved 000b 19 interrupt status 0 = no int x interrupt pending 1 = int x interrupt pending internally to nt port virtual interface ro yes 0 20 capabilities list set to 1, as required by the pci express base r1.0a . ro yes 1 21 66 mhz capable cleared to 0, as required by the pci express base r1.0a . ro no 0 22 reserved 0 23 fast back-to-back transactions capable cleared to 0, as required by the pci express base r1.0a . ro no 0 24 master data parity error if the parity error response enable bit is set to 1, the nt port virtual interface sets this bit to 1 when the nt port: forwards the poisoned tlp write reque st from the link interface to the virtual interface, or receives a completion marked as poisoned on the virtual interface if the parity error response enable bit is cleared to 0, the pex 8524 never sets this bit. this error is natively reported by the uncorrectable error status register poisoned tlp status bit (offset fb8h [12]), which is mapped to this bit for conventional pci backward compatibility. rw1c yes 0 26:25 devsel timing not supported always cleared to 00b. ro no 00b 27 signaled target abort set to 1, when the nt port forwards a completion with completer abort (ca) status from the link interfac e to the virtual interface. note: when set during a forwarded completion, the uncorrectable error status register completer abort status bit (offset fb8h [ 15 ]) is not updated, because the nt port does not log the requests that it forwards. rw1c yes 0 register 15-2. 04h status/command (cont.) bit(s) description type serial eeprom default
nt port virtual interface registers plx technology, inc. 360 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 28 received target abort cleared to 0, as required by the pci express base r1.0a . ro no 0 29 received master abort cleared to 0, as required by the pci express base r1.0a . ro no 0 30 signaled system error when the serr# enable bit is set to 1, the nt port virtual interface sets signaled system error to 1 when it transmits an err_fatal or err_nonfatal message to its upstream port. this error is natively reported by the device status register fatal error detected and non-fatal error detected bits (offset 70h [18:17], respectively), which are mapped to this bit for conventional pci backward compatibility. rw1c yes 0 31 detected parity error the nt port virtual interface sets this bit to 1 when it receives a poisoned tlp, regardless of the parity error response enable bit state. this error is natively reported by the uncorrectable error status register poisoned tlp status bit (offset fb8h [12]), which is mapped to this bit for conventional pci backward compatibility. rw1c yes 0 register 15-3. 08h class code and revision id bit(s) description type serial eeprom default 7:0 revision id unless overwritten by the serial eeprom, returns the silicon revision (aah, bbh, or bch for pex 8524v; bbh or bch for pex 8524), the plx-assigned revision id for this version of th e pex 8524. the pex 8524 serial eeprom register initialization capa bility is used to replace the plx revision id with another revision id. note: silicon revision bb only ? bit 0 is hardwired to 1 and is not programmable by serial eeprom. silicon revi sion bc only ? bits [2:0] are hardwired to 100b and are not programmable by serial eeprom. ro ye s (refer to note) aah, bbh, or bch (pex 8524v) or bbh or bch (pex 8524) class code 068000h 15:8 programming interface reserved , as required by the pci r2.3. ro yes 00h 23:16 sub-class code other bridge devices. ro yes 80h 31:24 base class code bridge devices. ro yes 06h register 15-2. 04h status/command (cont.) bit(s) description type serial eeprom default
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 361 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-4. 0ch miscellaneous control bit(s) description type serial eeprom default 7:0 cache line size implemented as a read-wr ite field for conventional pci compatibility purposes and does not impact pe x 8524 functionality. rw yes 00h 15:8 master latency timer not supported cleared to 00h. ro no 00h 22:16 configuration layout type type 0 configuration header for nt port. ro yes 00h 23 function type 0 = pex 8524 is a single-function device ro yes 0 31:24 bist not supported ro no 00h
nt port virtual interface registers plx technology, inc. 362 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: when software writes to the nt port virtual interface base address 1 ( bar1 ) register, the value is automatically copied to the nt port virtual interface bar1 shadow register (offset d6ch ). software (device driver) must copy the bar1 register value to the bar1 shadow register in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in the nt port virtual interface, offset 14h or d6ch, and write the value to port 8, offset d6ch if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset 14h or d6ch, and write the value to port 0, offset d6ch note: when software writes to the nt port virtual interface base address 2 ( bar2 ) register, the value is automatically copied to the nt port virtual interface bar2 shadow register (offset d70h ). software (device driver) must copy the bar2 register value to the bar2 shadow register in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in the nt port virtual interface, offset 18h or d70h, and write the value to port 8, offset d70h if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset 18h or d70h, and write the value to port 0, offset d70h register 15-5. 14h base address 1 bit(s) description type serial eeprom default 0 i/o space indicator i/o bar when offset d0h [1:0] = 11b; otherwise, reserved . ro yes 1 7:1 reserved 0h 31:8 i/o base address 256-byte i/o space base address when offset d0h[1:0] = 11b; otherwise, reserved . rw yes 0000_00h register 15-6. 18h base address 2 bit(s) description type serial eeprom default 0 memory space indicator 0 = memory bar ? only value supported ro yes 0 2:1 memory map type 00b = mappable anywhere in 32-bit memory space 01b, 10b, 11b = reserved ro yes 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable ro yes 0 11:4 reserved 00h 31:12 base address 2 contains the software-assigned memory space base address: enabled and sized by the nt port virtual interface bar2 setup register used for memory transac tions crossing the nt port minimum address range requested is 4 kb uses direct address translation includes a limit register rw yes 0000_0h
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 363 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: when software writes to the nt port virtual interface base address 3 ( bar3 ) register, the value is automatically copied to the nt port virtual interface bar3 shadow register (offset d74h ). software (device driver) must copy the bar3 register value to the bar3 shadow register in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in the nt port virtual interface, offset 1ch or d74h, and write the value to port 8, offset d74h if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset 1ch or d74h, and write the value to port 0, offset d74h register 15-7. 1ch base address 3 (nt port virtual interface memory space) bit(s) description type serial eeprom default 0 memory space indicator 0 = memory bar ? only value supported ro yes 0 2:1 memory map type 00b = mappable anywhere in 32- bit memory address space 01b, 10b, 11b = not allowed ro yes 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable ro yes 0 17:4 reserved 0000h 31:18 base address 3 contains the software-assigne d memory space base address: enabled and sized by the nt port virtual interface bar3 setup register no limit register used for memory transactions crossing the nt port minimum address range requested is 256 kb uses lut address translation rw yes 0000h
nt port virtual interface registers plx technology, inc. 364 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: when software writes to the nt port virtual interface base address 4 ( bar4 ) register, the value is automatically copied to the nt port virtual interface bar4 shadow register (offset d78h ). software (device driver) must copy the bar4 register value to the bar4 shadow register in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in the nt port virtual interface, offset 20h or d78h, and write the value to port 8, offset d78h if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset 20h or d78h, and write the value to port 0, offset d78h note: when software writes to the nt port virtual interface base address 5 ( bar5 ) register, the value is automatically copied to the nt port virtual interface bar5 shadow register (offset d7ch ). software (device driver) must copy the bar5 register value to the bar5 shadow register in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in the nt port virtual interface, offset 24h or d7ch, and write the value to port 8, offset d7ch if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset 24h or d7ch, and write the value to port 0, offset d7ch register 15-8. 20h base address 4 bit(s) description type serial eeprom default 0 memory space indicator 0 = memory bar ? only value supported ro yes 0 2:1 memory map type 00b = bar is mapped anywhere in 32-bit memory space 10b = bar is mapped anywhere in 64-bit memory space 01b, 11b = reserved ro yes 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable ro yes 0 11:4 reserved 00h 31:12 base address 4 contains the software-assigne d memory space base address: enabled and sized by the nt port virtual interface bar4/5 setup register used for memory transact ions crossing the nt port minimum address range requested is 4 kb uses direct address translation rw yes 0000_0h register 15-9. 24h base address 5 bit(s) description type serial eeprom default 31:0 base address 5 nt port virtual interface upper 32-bit address if bar4/5 is implemented as a 64-bit bar; otherwise, reserved . rw, based on the nt port virtual interface bar5 setup register. the bar4/5 group uses direct address translation. contains a limit register. rw yes 0-0h
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 365 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-10. 2ch subsystem id and subsystem vendor id bit(s) description type serial eeprom default 15:0 subsystem vendor id unless overwritten by the serial eeprom, returns the plx pci-sig-assigned vendor id. the pex 8524 serial eeprom register initialization capability is used to replace the plx vendor id with another vendor id. hwinit yes 10b5h 31:16 subsystem id unless overwritten by the serial eeprom, the pex 8524 returns 8532h (pex 8524v) or 8524h (pex 8524), the plx-assigned device id. the pex 8524 serial eeprom register initialization capability is used to replace the plx-assigned device id with another device id. hwinit yes 8532h (pex 8524v) 8524h (pex 8524) register 15-11. 34h new capabilities pointer bit(s) description type serial eeprom default 7:0 new capability pointer default 40h points to the power management capabilities register. ro yes 40h 31:8 reserved 0000_00h register 15-12. 3ch interrupt bit(s) description type serial eeprom default 7:0 interrupt line interrupt line routing valu e communicates interrupt li ne routing information. values in this register are programmed by system software and are system architecture-specific. the value is used by device drivers and operating systems. rw yes 00h 15:8 interrupt pin identifies the conventional pci interrupt message(s) that the device (or device function) uses. when values = 01h, 02h, 03h, and 04h, maps to conventional pci interrupt messages for inta#, intb#, intc#, and intd#, respectively. when 00h, indicates that the de vice does not use conventional pci interrupt message(s). only values 00h or 01h are allowed in the pex 8524. ro yes 01h 31:16 reserved 0000h
nt port virtual interface registers plx technology, inc. 366 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.5 power management capability registers this section details the nt port virtual interface power management registers. the register map is defined in table 15-3 . table 15-3. power management capability register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 power management capabilities next capability pointer ( 48h ) capability id ( 01h ) 40h data power management control/ status bridge extensions power management st atus and control 44h register 15-13. 40h power management capabilities bit(s) description type serial eeprom default 7:0 capability id default = 01h ? only value allowed. indicates that the data structure currently being pointed to is the pci power management data structure. ro yes 01h 15:8 next capability pointer default 48h points to the message signaled interrupt capability register. ro yes 48h 18:16 ver s i o n default = 010b ? only value allowed. ro yes 010b 19 pme clock cleared to 0, as required by the pci express base r1.0a . ro no 0 20 reserved 0 21 device-specific initialization default 0 indicates that devi ce-specific initialization is not required. ro yes 0 24:22 aux current not supported default 000b indicates that the pex 8524 does not support auxiliary current requirements. ro yes 000b 25 d1 support not supported default 0 indicates that the pex 8524 does not support the d1 power state. ro no 0 26 d2 support not supported default 0 indicates that the pex 8524 does not support the d2 power state. ro no 0 31:27 pme support default 0000_0b indicates that the nt port does not forward pme messages. ro yes 0000_0b
february, 2007 power manage ment capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 367 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-14. 44h power management status and control bit(s) description type serial eeprom default power management status and control 1:0 power state this field is used to determine the curren t power state of the port, and to set the port into a new power state. 00b = d0 01b = d1 ? not supported 10b = d2 ? not supported 11b = d3hot if software attempts to write an unsupported state to this field, the write operation completes normally; however, the data is discarded and no st ate change occurs. rw yes 00b 7:2 reserved ro no 0h 8 pme enable 0 = disables pme generation ro no 0 a a. because the pex 8524 does not suppor t auxiliary power, this bi t is not sticky, and is always cleared to 0 at power-on reset. 12:9 data select rw by serial eeprom mode only b . bits [12:9] select the data and data scale registers. 0h = d0 power consumed 3h = d3hot power consumed 4h = d0 power dissipated 7h = d3hot power dissipated ro yes 0h 14:13 data scale rw by serial eeprom mode only b . there are four internal data scale registers per port. bits [12:9], data select , select the data scale register. ro yes 00b 15 pme status 0 = pme is not being ge nerated by the nt port ro no 0 a power management control/s tatus bridge extensions 21:16 reserved 0-0h 22 b2/b3 support cleared to 0, as required by the pci express base r1.0a . ro no 0 23 bus power/clock control enable cleared to 0, as required by the pci express base r1.0a . ro no 0 power management data 31:24 data rw by serial eeprom mode only b . there are four internal data registers per port. bits [12:9], data select , select the data register. b. with no serial eeprom, reads return 0h for the data scale and data registers (for al l data selects). ro yes 00h
nt port virtual interface registers plx technology, inc. 368 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.6 message signaled interrupt capability registers the message signaled interrupt (msi) ca pability registers are defined in section 11.8, ?message signaled interrupt capability registers.? table 15-4 defines the register map used by the nt port virtual interface. table 15-4. message signaled interrupt capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 message control next capability pointer ( 68h ) capability id ( 05h ) 48h message address[31:0] 4ch message upper address[63:32] 50h reserved message data 54h reserved 58h ? 64h
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 369 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.7 pci express capability registers this section details the pex 8524 pci express capability registers. the hot plug capabilities, command, status, and ev ents are included in these register s. the register map is defined in table 15-5 . table 15-5. pci express capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 pci express capabilities next capability pointer ( 00h ) capability id ( 10h ) 68h device capabilities 6ch device status device control 70h link capabilities 74h link status link control 78h reserved 7ch ? 8ch register 15-15. 68h pci express capability list and capabilities bit(s) description type serial eeprom default pci express capability list 7:0 capability id set to 10h by default, as required by the pci express base r1.0a . ro yes 10h 15:8 next capability pointer 00h = pci express capability is the la st capability in the first 256-byte configuration space of the pex 8524 nt po rt virtual interfac e capability list the pex 8524 nt port virtual interface extended capabilitie s list starts at 100h . ro yes 00h pci express capabilities 19:16 capability version set to 1h. ro yes 1h 23:20 device/port type pci express endpoint device. ro yes 0h 24 slot implemented not valid for pci expr ess endpoint devices. ro no 0 29:25 interrupt me ssage number the serial eeprom writes 0000_0b, because the base message and msi messages are the same. ro yes 0000_0b 31:30 reserved 00b
nt port virtual interface registers plx technology, inc. 370 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-16. 6ch device capabilities bit(s) description type serial eeprom default 2:0 maximum payload size supported 000b = nt port virtual interface supp orts 128-byte maximum payload 001b = nt port virtual interface supp orts 256-byte maximum payload no other values are supported. note: serial eeprom must not load greater than 256 bytes maximum payload size. ro yes 001b 4:3 phantom functions supported not supported cleared to 00b. ro yes 00b 5 extended tag field supported not supported 0 = maximum tag field is 5 bits 1 = maximum tag field is 8 bits ro yes 0 8:6 endpoint l0s acceptable latency ro yes 000b 11:9 endpoint l1 acceptable latency ro yes 000b 12 attention button present no attention button present for nt virtual interface. ro no 0 13 attention indicator present no attention indicator presen t for nt virtual interface. ro no 0 14 power indicator present no power indicator present for nt virtual interface. ro no 0 17:15 reserved 000b 25:18 captured slot power limit value for the nt port virtual interface register, the upper limit on power supplied by the slot is determined by multiplying the value in this field by the value in the captured slot power limit scale field. ro yes 00h 27:26 captured slot power limit scale for the nt port virtual interface regist er, the upper limit on power supplied by the slot is determined by multiplying the value in this field by the value in the captured slot power limit value field. 00b = 1.0 01b = 0.1 10b = 0.01 11b = 0.001 ro yes 00b 31:28 reserved 0h
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 371 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-17. 70h device status and control bit(s) description type serial eeprom default device control 0 correctable error reporting enable 0 = disables 1 = enables nt port virtual interface to report correctable errors to local host rw yes 0 1 non-fatal error reporting enable 0 = disables 1 = enables nt port virtual interface to report non-fatal errors to local host rw yes 0 2 fatal error reporting enable 0 = disables 1 = enables nt port virtual interface to report fatal errors to local host rw yes 0 3 unsupported request reporting enable 0 = disables 1 = enables nt port virtual interface to report unsupported request errors to local host rw yes 0 4 relaxed ordering enable cleared to 0, as required by the pci express base r1.0a . ro no 0 7:5 maximum payload size the nt port virtual interfac e power-on/reset value is 000b, to support a maximum payload size of 128 bytes. software can ch ange this field to configure the nt port virtual interface to support other payload si zes; however, software cannot change this field to a value larger than that indicated by the device capabilities register maximum payload size supported field (offset 6ch [2:0]). for the virtual and link interfaces. (requester and completer domains must possess the same maximum payload size.) 000b = indicates that initially the pe x 8524 port is configured to support a maximum payload size of 128 bytes 001b = indicates that initially the pe x 8524 port is configured to support a maximum payload size of 256 bytes no other values are supported. note: software must halt all transactions through the nt port before changing this field. rw yes 000b
nt port virtual interface registers plx technology, inc. 372 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8 extended tag field enable not supported cleared to 0. ro no 0 9 phantom functions enable not supported cleared to 0. ro no 0 10 auxiliary (aux) power pm enable not supported cleared to 0. ro no 0 11 no snoop enable not supported cleared to 0. ro no 0 14:12 maximum read request size not supported cleared to 000b. ro no 000b 15 reserved 0 device status 16 correctable error detected 1 = nt port detected a correctable error set when the nt port virtual interface de tects a correctable error, regardless of the bit 0 ( correctable erro r reporting enable bit) state. rw1c yes 0 17 non-fatal error detected 1 = nt port virtual interface detected a non-fatal error set when the nt port virtual interface detects a non-fatal error, regardless of the bit 1 ( non-fatal error reporting enable bit) state. rw1c yes 0 18 fatal error detected 1 = nt port virtual interface detected a fatal error set when the nt port virtual interfac e detects a fatal error, regardless of the bit 2 ( fatal error reporting enable bit) state. rw1c yes 0 19 unsupported request detected 1 = nt port virtual interface detected an unsupported request set when the nt port virtual interf ace detects an unsupported request, regardless of the bit 3 ( unsupported request reporting enable bit) state. rw1c yes 0 20 auxiliary (aux) power detected not supported cleared to 0. ro no 0 21 transactions pending because the pex 8524 nt port is a bridging device, it does not track completion for the corresponding non-posted transactions. th erefore, the nt port virtual interface does not implement tr ansactions pending. ro no 0 31:22 reserved 000h register 15-17. 70h device status and control (cont.) bit(s) description type serial eeprom default
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 373 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-18. 74h link capabilities bit(s) description type serial eeprom default 3:0 maximum link speed set to 0001b for 2.5 gbps. ro yes 0001b 9:4 maximum link width actual link width is set by signal ball strapping opt ions. the pex 8524 maximum link width is x8 = 00_1000b (station 0), or x16 = 01_0000b (station 1). ro no strap levels 11:10 active state power management (aspm) support indicates the level of aspm supported by the port. 01b = l0s link power state entry is supported all other values are reserved . ro yes 01b 14:12 l0s exit latency 101b = nt port virtual interface l0s ex it latency is between 1 and 2 s ro no 101b 17:15 l1 exit latency 101b = nt port virtual interface l1 exit latency is between 16 and 32 s ro yes 101b 23:18 reserved 0-0h 31:24 port number the nt port number is selected by signal ball strapping options. refer to strap_nt_upstrm_portsel[3:0] for details. hwinit no set by strap levels
nt port virtual interface registers plx technology, inc. 374 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-19. 78h link status and control bit(s) description type serial eeprom default link control 1:0 active state power management (aspm) control not applicable to the nt port virtual interface, because no external port connection exists. rw yes 00b 2 reserved 0 3 read completion boundary (rcb) not supported cleared to 0. ro yes 0 4 link disable for nt port ? reserved. ro no 0 5 retrain link for nt port ? reserved. ro no 0 6 common clock configuration not applicable to the nt port virtual interface, because no external port connection exists. rw yes 0 7 extended sync not applicable to the nt port virtual interface, because no external port connection exists. rw yes 0 15:8 reserved 00h link status 19:16 link speed the nt port virtual interface is set to 1h for 2.5 gbps. ro yes 1h 25:20 negotiated link width not applicable to the nt port virtual interface, because no external port connection exists. ro yes 00_0001b 26 training error for endpoint devices ? reserved. ro no 0 27 link training for endpoint devices ? reserved. ro no 0 28 slot clock configuration because there is no extern al connection to the nt po rt virtual interface, slot clock configuration is always 0, which indicates that the pex 8524 uses an independent clock. hwinit yes 0 31:29 reserved 000b
february, 2007 nt port registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 375 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.8 nt port registers 15.8.1 nt port virtual inte rface irq doorbell registers this section details the pex 8524 nt port virtual interface interr upt request (irq) doorbell registers. the register map is defined in table 15-6 . table 15-6. nt port virtual interface interrupt request (irq) doorbell register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved set virtual interface irq 90h reserved clear virtual interface irq 94h reserved set virtual interface irq mask 98h reserved clear virtual interface irq mask 9ch reserved set link interface irq a0h reserved clear link interface irq a4h reserved set link interface irq mask a8h reserved clear link interface irq mask ach
nt port virtual interface registers plx technology, inc. 376 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-20. 90h set virtual interface irq bit(s) description type serial eeprom default 15:0 set virtual irq controls the state of the virtual interface doorbell interrupt request. reading returns the status of the bits. writing 0 to a bit in the register has no effect. writing 1 to a bit in the register se ts the corresponding interrupt request. the virtual interface interrupt is asse rted if the following conditions exist: this register (offset 90h or 94h ) value is non-zero, and, the corresponding mask bit in the set virtual interface irq mask or clear virtual interface irq mask register (offset 98h or 9ch , respectively) is not set, and, interrupts (either int x or msi) are enabled rw1s yes 0000h 31:16 reserved 0000h register 15-21. 94h clear virtual interface irq bit(s) description type serial eeprom default 15:0 clear virtual irq controls the state of the virtual interfac e doorbell interrupt re quest. reading returns the status of the bits. writing 0 to a bit in the register has no effect. writing 1 to a bit in the register cl ears the corresponding interrupt request. the virtual interface interrupt is asserted if the following conditions exist: this register (offset 94h or 90h ) value is non-zero, and, the corresponding mask bit in the set virtual interface irq mask or clear virtual interface irq mask register (offset 98h or 9ch , respectively) is not set, and, interrupts (either int x or msi) are enabled rw1c yes 0000h 31:16 reserved 0000h
february, 2007 nt port virtual interface irq doorbell registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 377 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-22. 98h set virtual interface irq mask bit(s) description type serial eeprom default 15:0 set virtual irq mask virtual interface interrupt ir q mask set. reading returns the state of the mask bits. 0 = corresponding interrupt request bit in the set virtual interface irq register (offset 90h ) is unmasked 1 = corresponding interrupt request bit in the set virtual interface irq register (offset 90h) is masked/disabled writing 0 to a bit in the register has no effect. writing 1 to a bit in the register clea rs the corresponding interrupt mask bit. rw1s yes ffffh 31:16 reserved 0000h register 15-23. 9ch clear virtual interface irq mask bit(s) description type serial eeprom default 15:0 clear virtual irq mask controls the state of the virtual interface interrupt request bits. reading returns the status of the bits. 0 = corresponding interrupt request bit in the clear virtual interface irq register (offset 94h ) is unmasked 1 = corresponding interrupt request bit in the clear virtual interface irq register (offset 94h) is masked/disabled writing 0 to a bit in the register has no effect. writing 1 to a bit in the register clea rs the corresponding interrupt mask bit. rw1c yes ffffh 31:16 reserved 0000h
nt port virtual interface registers plx technology, inc. 378 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-24. a0h set link interface irq bit(s) description type serial eeprom default 15:0 set link irq controls the state of the link interface doorbell interrupt re quest. reading returns the status of the bits. writing 0 to a bit in th e register has no effect. writing 1 to a bit in the register sets the corresponding interrupt request. the link interface interrupt is assert ed if the following conditions exist: this register (offset a0h or a4h ) value is non-zero, and, the corresponding mask bit in the set link interface irq mask or clear link interface irq mask register (offset a8h or ach , respectively) is not set, and, interrupts (either int x or msi) are enabled rw1s yes 0000h 31:16 reserved 0000h register 15-25. a4h clear link interface irq bit(s) description type serial eeprom default 15:0 clear link irq controls the state of the link interface d oorbell interrupt reque st. reading returns the status of the bits. writing 0 to a bit in the register has no effect. writing 1 to a bit in the register cl ears the corresponding interrupt request. the link interface interrupt is assert ed if the following conditions exist: this register (offset a4h or a0h ) value is non-zero, and, the corresponding mask bit in the set link interface irq mask or clear link interface irq mask register (offset a8h or ach, respectively) is not set, and, interrupts (either int x or msi) are enabled rw1c yes 0000h 31:16 reserved 0000h
february, 2007 nt port virtual interface irq doorbell registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 379 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-26. a8h set link interface irq mask bit(s) description type serial eeprom default 15:0 set link irq mask link interface interrupt irq mask set. re ading returns the state of the irq mask. 0 = corresponding interrupt request bit in the set link interface irq register (offset a0h ) is unmasked 1 = corresponding interrupt request bit in the set link interface irq register (offset a0h) is masked/disabled writing 0 to a bit in the register has no effect. writing 1 to a bit in the register sets the corresponding interrupt mask bit. rw1s yes ffffh 31:16 reserved 0000h register 15-27. ach clear link interface irq mask bit(s) description type serial eeprom default 15:0 clear link irq mask link interface interrupt irq mask clear. reading returns the state of the irq mask. 0 = corresponding interrupt request bit in the clear link interface irq register (offset a4h ) is unmasked 1 = corresponding interrupt request bit in the clear link interface irq register (offset a4h) is masked/disabled writing 0 to a bit in the register has no effect. writing 1 to a bit in the register cl ears the corresponding interrupt mask bit. rw1c yes ffffh 31:16 reserved 0000h
nt port virtual interface registers plx technology, inc. 380 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.8.2 nt port scratchpad (mailbox) registers the pex 8524 nt port scratchpad (mailbox) registers are defined in section 16.8.2, ?nt port scratchpad (mailbox) registers.? table 15-7 defines the register map used by the nt port virtual interface. table 15-7. pex 8524 nt port scratchpad (mailbox) register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 nt port scratchpad_0 b0h nt port scratchpad_1 b4h nt port scratchpad_2 b8h nt port scratchpad_3 bch nt port scratchpad_4 c0h nt port scratchpad_5 c4h nt port scratchpad_6 c8h nt port scratchpad_7 cch
february, 2007 nt port virtual interface bar setup registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 381 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.8.3 nt port virtual inte rface bar setup registers this section details the nt port virtual interface bar setup registers. the register map is defined in table 15-8 . the nt port virtual interface bar x setup (offsets d0h through e0h) register values are shadowed in the corresponding nt port virtual interface bar x setup shadow registers (offsets d80h through d90h , respectively). when software writes to an nt port virtual interface bar x setup register, the value is automatically copied to the corresponding nt port virtual interface bar x setup shadow register. if the nt port virtual interface bar x setup registers are programmed by serial eeprom, the nt port virtual interface bar x setup shadow registers must also be programmed by serial eeprom, to the same respective register values. table 15-8. pex 8524 nt port virtual interface bar setup register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 nt port virtual interface bar1 setup d0h nt port virtual interface bar2 setup d4h nt port virtual interface bar3 setup d8h nt port virtual interface bar4/5 setup dch nt port virtual interface bar5 setup e0h reserved e4h ? f4h
nt port virtual interface registers plx technology, inc. 382 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: software must copy the bar1 setup register value to the bar1 setup shadow register ( d80h ) in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in nt port virtual interface, offset d0h or d80h, and write the value to port 8, offset d80h if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset d0h or d80h, and write the value to port 0, offset d80h note: software must copy the bar2 setup register value to the bar2 setup shadow register ( d84h ) in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in nt port virtual interface, offset d4h or d84h, and write the value to port 8, offset d84h if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset d4h or d84h, and write the value to port 0, offset d84h register 15-28. d0h nt port virtual interface bar1 setup bit(s) description type serial eeprom default 1:0 i/o bar1 enable 11b = enables virtual interface bar1 as an i/o bar. all other values disable bar1 . rw yes 11b 31:2 reserved 0-0h register 15-29. d4h nt port virtual interface bar2 setup bit(s) description type serial eeprom default 0 reserved 0 2:1 bar2 type 00b = selects 32-bit memory bar no other values are allowed. rw yes 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable rw yes 0 11:4 reserved 00h 30:12 bar2 size specifies the address ra nge size requested by bar2 . 0 = corresponding bits in bar2 are read-only bits that always return 0, and writes are ignored 1 = corresponding bits in bar2 are rw bits rw yes 0000_0h 31 bar2 enable 0 = bar2 is disabled, all bits in bar2 read 0 1 = bar2 is enabled, size and type specified in this register rw yes 0
february, 2007 nt port virtual interface bar setup registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 383 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: software must copy the bar3 setup register value to the bar3 setup shadow register ( d88h ) in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in nt port virtual interface, offset d8h or d88h, and write the value to port 8, offset d88h if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset d8h or d88h, and write the value to port 0, offset d88h register 15-30. d8h nt port virtual interface bar3 setup bit(s) description type serial eeprom default 0 prefetchable 0 = non-prefetchable 1 = prefetchable rw yes 0 15:1 reserved 0-0h 19:16 bar3 lut page size selects the page size of the virtual interface bar3 address range. the total size of this range is dependent on the page size. when the bar3 lut page size extension bit value is 0, the en codings are as follows: when the bar3 lut page size extension bit value is 1, the encodings are as follows: 0h = 8 mb 1h = 16 mb 2h = 32 mb 3h to fh = reserved rw yes 0h 20 bar3 lut page size extension allows selection of larger page si zes when programming page size[19:16]. 0 = page sizes 4 kb through 4 mb are available in the page size[19:16] 1 = page sizes 8 through 32 mb are available in the page size[19:16] rw yes 0 31:21 reserved 000h 0h = disables bar3 ah = 128 kb 1h to 4h = reserved bh = 256 kb 5h = 4 kb ch = 512 kb 6h = 8 kb dh = 1 mb 7h = 16 kb eh = 2 mb 8h = 32 kb fh = 4 mb 9h = 64 kb
nt port virtual interface registers plx technology, inc. 384 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: software must copy the bar4 setup register value to the bar4 setup shadow register ( d8ch ) in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in nt port virtual interface, offset dch or d8ch, and write the value to port 8, offset d8ch if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset dch or d8ch, and write the value to port 0, offset d8ch register 15-31. dch nt port virtual interface bar4/5 setup bit(s) description type serial eeprom default 0 reserved 0 2:1 bar4 type 00b = bar4 is implemented as a 32-bit memory bar 10b = bar4/5 is implemented as a 64-bit memory bar note: it is illegal to program 10b and clear the nt port virtual interface bar5 setup register bar5 enable bit (offset e0h [31]). rw yes 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable rw yes 0 11:4 reserved 00h 30:12 bar4 size specifies the address ra nge size requested by bar4 . 0 = corresponding bits in bar4 are read-only bits that always return 0, and writes are ignored 1 = corresponding bits in bar4 are rw bits rw yes 0000_0h 31 bar4 enable when bits [2:1] = 00b, enables bar4 ; otherwise, belongs to the bar4 size [30:12] field. 0 = bar4 is disabled, all bits in bar4 read 0 1 = bar4 is enabled, size and type specified in this register rw yes 0
february, 2007 nt port virtual interface bar setup registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 385 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: software must copy the bar5 setup register value to the bar5 setup shadow register ( d90h ) in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in nt port virtual interface, offset e0h or d90h, and write the value to port 8, offset d90h if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset e0h or d90h, and write the value to port 0, offset d90h register 15-32. e0h nt port virtual interface bar5 setup bit(s) description type serial eeprom default 30:0 bar5 size together with the nt port virtual interface bar4/5 setup register bar4 size field (offset dch [31:12]), specifies the address range size requested by bar4/5 in 64-bit mode when the nt port virtual interface bar4/5 setup register bar4 type field (offset dch[2:1]) is set to 10b. 0 = corresponding bits in bar5 are read-only bits that always return 0, and writes are ignored 1 = corresponding bits in bar5 are rw bits rw yes 0-0h reserved when the nt port virtual interface bar4/5 setup register bar4 type field (offset dch[2:1]) is cleared to 00b. 0-0h 31 bar5 enable 0 = bar5 is disabled 1 = bar5 is enabled when the nt port virtual interface bar4/5 setup register bar4 type field (offset dch[2:1]) is set to 10b note: it is illegal to program the nt port virtual interface bar4/5 setup register bar4 type = 10b and clear this bit. rw yes 0 reserved when the nt port virtual interface bar4/5 setup register bar4 type field (offset dch[2:1]) is cleared to 00b. 0
nt port virtual interface registers plx technology, inc. 386 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.8.4 nt port cursor mechanism control registers this section details the nt port cursor mechanism c ontrol registers. the register map for the virtual and link interfaces is defined in table 15-9 . the cursor mechanism registers at offsets f8h/ fch provide a means for accessing pci express extended configuration space registers (100h thr ough fffh) within the nt port virtual and link interfaces, when only standard pci configuration tr ansactions (that do not support extended register number), and/or i/o request tran sactions (using the nt port bar1 address, if enab led) are available. the cursor mechanism can generally access only those registers that are defined by the pci express base r1.0a , and not the device-specific registers. however if port 0 is the nt port, the cursor mechanism in the nt port virtual inte rface registers can also access the device-specific registers. table 15-9. nt port cursor mechanism control register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 configuration address window reserved f8h configuration data window fch register 15-33. f8h configuration address window bit(s) description type serial eeprom default 15:0 reserved 0000h 25:16 offset register offset. rw yes 000h 30:26 reserved 0h 31 interface select 0 = access to nt port virtual interfac e type 0 configuration space register 1 = access to nt port link interface type 0 configuration space register rw yes 0 register 15-34. fch configuration data window bit(s) description type serial eeprom default 31:0 data window software selects a register by writing into the nt port configuration address window, then reads or writes to th at register using this register. rw yes 0-0h
february, 2007 device serial numb er extended capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 387 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.9 device serial number extended capability registers the nt port device serial number extended capability registers are the same as the pex 8524 transparent port registers, as defined in section 11.10, ?device serial number extended capability registers.? the register map is defined in table 15-10 and applies to the vi rtual and link interfaces. 15.10 power budgeting extended capability registers the nt port power budgeting extended ca pability registers are the same as the pex 8524 transparent port registers, as defined in section 11.11, ?power budgeting extended capability registers.? the register map is defined in table 15-11 and applies to the virtual and link interfaces. table 15-10. pex 8524 device serial number extended capability register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 next capability offset ( fb4h ) capability version ( 1h ) extended capability id ( 0003h ) 100h serial number (lower dw) 104h serial number (higher dw) 108h table 15-11. pex 8524 power budgeting extended capability register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 next capability offset ( 148h ) capability ve r s i o n ( 1h ) extended capability id ( 0004h ) 138h reserved data select 13ch power budgeting data 140h reserved power budget capability 144h
nt port virtual interface registers plx technology, inc. 388 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.11 virtual channel extended capability registers the nt port virtual channel extended ca pability registers are the same as the pex 8524 transparent port registers, as defined in section 11.12, ?virtual channel extended capability registers.? the register map is defined in table 15-12 and applies to the virtual and link interfaces. table 15-12. pex 8524 virtual channel extended capability register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 next capability offset ( 000h ) capability ve r s i o n ( 1h ) extended capability id ( 0002h ) 148h port vc capability 1 14ch port vc capability 2 150h port vc status port vc control 154h vc0 resource capability 158h vc0 resource control 15ch vc0 resource status reserved 160h vc1 resource capability 164h vc1 resource control 168h vc1 resource status reserved 16ch reserved 170h ? 1b4h virtual channel arbitration table 1b8h ? 1c4h
february, 2007 plx-specific registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 389 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.12 plx-specific registers the pex 8524 nt mode virtual interface plx-sp ecific registers are defined in section 11.13, ?plx- specific registers,? except as defined in table 15-13 through table 15-16 and/or their respective register tables. the entire register map is defined in table 15-13 . note: this register group is accesse d using a memory-mapped cycle. it is recommended that these register values not be changed. table 15-13. nt port virtual interface plx-specific register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 error checking and debug registers 1c8h ? 1fch physical layer registers 200h ? 2c4h cam routing registers 2c8h ? 344h nt port virtual interface ingress control register 660h ? 668h i/o cam base and limit upper 16 bits registers 680h ? 6ach base address registers (bars) 6c0h ? 73ch shadow virtual channel (v c) capability registers 740h ? 9ech ingress credit handler (inch) registers 9f0h ? b7ch reserved b80h ? bfch internal credit handler (itch ) vc&t threshold registers c00h ? c08h
nt port virtual interface registers plx technology, inc. 390 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.12.1 error checking and debug registers the nt mode virtual interface error check ing and debug registers are defined in section 11.13.1, ?error checking and debug registers,? except as defined in table 15-14 (offsets 1d4h through 1d8h and 1e0h are reserved ) and the register tables that follow. table 15-14. plx-specific error checking and debug register map (ports a ) a. some registers are port-specifi c, some are station-specific , and some are device-specific. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved 1c8h error handler 32-bit error status (factory test only) 1cch error handler 32-bit error mask (factory test only) 1d0h reserved 1d4h ? 1d8h debug control 1dch reserved 1e0h egress nt port virtual interface control and status 1e4h reserved 1e8h ? 1ech plx-specific relaxed ordering enable 1f0h software-controlle d lane status 1f4h reserved ack transmission latency limit 1f8h reserved 1fch
february, 2007 error checking and debug registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 391 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: all errors in register offset 1cch generate msi/intx interrupts, when enabled. note: error logging is enabled in register offset 1d0h, by default. register 15-35. 1cch error handler 32-bit error status (factory test only) bit(s) description type serial eeprom default 0 error handler completion fifo overflow status 0 = no overflow detected 1 = completion fifo overflow detected when 4-deep completion fifo for ingress, or 2-deep completi on fifo for egress, overflows rw1cs yes 0 10:1 reserved no 0h 11 credit update timeout status no useful credit update to make forward progress for 512 ms or 1s (disabled by default). 0 = no credit update timeout detected 1 = credit update timeout completed rw1cs yes 0 12 inch underrun error ingress credit underrun. 0 = no error detected 1 = credit underrun error detected rw1cs yes 0 31:13 reserved no 0h register 15-36. 1d0h error handler 32-bit error mask (factory test only) bit(s) description type serial eeprom default 0 error handler completion fifo overflow status masked 0 = no effect on reporting activity 1 = error handler completion fifo overflow status bit is masked/disabled rws yes 1 10:1 reserved no 0h 11 credit update timeout status masked 0 = no effect on reporting activity 1 = credit update timeout status bit is masked/disabled rws yes 1 12 inch underrun error masked 0 = no effect on reporting activity 1 = inch underrun error bit is masked/disabled rws yes 1 31:13 reserved no 0h
nt port virtual interface registers plx technology, inc. 392 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-37. 1e4h egress nt port virtual interface control and status bit(s) description type serial eeprom default 0 egress credit update timer enable 0 = disables egress credit update timer 1 = enables egress credit update timer rw yes 0 1 egress credit timeout value 0 = minimum 512 ms (maximum 768 ms) 1 = minimum 1,024 ms (maximum 1,280 ms) rw yes 0 2 egress debug factory test only rw yes 0 15:3 reserved 0-0h 19:16 vc&t encountered timeout 0h = vc0 posted 1h = vc0 non-posted 2h = vc0 completion 3h = vc1 posted 4h = vc1 non-posted 5h = vc1 completion ro yes 0h 31:20 reserved 000h register 15-38. 1f8h ack transmission latency limit bit(s) description type serial eeprom default 7:0 ack transmission latency limit if the serial eeprom is not present, the va lue of this register changes based upon the negotiated link width after the link is up. th e value of this register changes, based upon the negotiated link width of the nt port link interface. if the serial eeprom is present, program the serial eeprom to load the value based upon the programmed link width of the nt port link interface. rw yes ffh 15:8 hpc test bits fac t or y te st on ly. testing bits ? must be 00h. rw yes 00h 31:16 reserved 0000h
february, 2007 nt port virtual interface physical layer registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 393 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.12.2 nt port virtual interf ace physical layer registers the nt port virtual interface physical layer registers are defined in section 11.13.2, ?physical layer registers,? except as defined in table 15-15 . table 15-15. plx-specific nt port virtual interface physical layer register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved 200h ? 20ch phy user test pattern 0 210h phy user test pattern 4 214h phy user test pattern 8 218h phy user test pattern 12 21ch physical layer status ph ysical layer command 220h port configuration 224h physical layer test 228h reserved 22ch physical layer port command 230h skip ordered-set interval 234h quad 0 serdes diagnostic data 238h quad 1 serdes diagnostic data 23ch quad 2 serdes diagnostic data 240h quad 3 serdes diagnostic data 244h serdes nominal drive current select 248h serdes drive current level select 1 24ch serdes drive current level select 2 250h serdes drive equalization level select 1 254h serdes drive equalization level select 2 258h reserved 25ch ? 2c4h
nt port virtual interface registers plx technology, inc. 394 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.12.3 nt port virtual interf ace ingress control register the nt port virtual interface ingress control register is defined in section 11.13.4, ?ingress control registers,? with the addition of the ingress control register no snoop disable bit (bit 24) and bit 25 is changed to factory test only . the register map is defined in table 15-16 . table 15-16. plx-specific nt port virtual interface ingress control register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ingress control 660h reserved 664h ? 668h
february, 2007 nt port virtual interface ingress control register expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 395 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-39. 660h ingress control (only ports 0 and 8) bit(s) description type serial eeprom default 0 enable csr access by downstream devices silicon revision aa enables acceptance of configuration reques ts from a requester that is downstream from a transparent port, targeting any do wnstream transparent port?s type 1 header registers or nt port virtual interface type 0 header registers ( such as for peer configuration access). 0 = configuration requests fro m a downstream device are not supported ; the downstream port flags an uncorrectable error, and, returns a completion with unsupported request (ur) specified in the completion status field, to the downstream requester. only this mode is pci express base r1.0a -compliant. 1 = the following types of configurat ion requests from down stream requesters are allowed: type 0 requests targeting the type 1 head er registers in that downstream port type 1 requests targeting the type 1 he ader registers in other downstream transparent ports, and type 1 requests targeting the type 0 header registers in the nt port virtual interface the upstream port registers are not accessible from the downstream port. silicon revisions bb/bc enables acceptance of both configurati on and memory requests from a requester that is downstream from a transparent port, targeting any pex 8524 registers. 0 = configuration requests fro m a downstream device are not supported ; the downstream port flags an uncorrectab le error, and, returns a completion with unsupported request (ur) specified in the completion status field, to the downstream requester. only this mode is pci express base r1.0a -compliant. 1 = configuration and memory requests from downstream re questers, targeting any pex 8524 registers in any port, are allowed. notes: this bit can be initially set only th rough the upstream port, the nt port link interface, or serial eeprom, to enable register access through downstream transparent ports; a requester downstream fr om a transparent port cannot set the bit to grant itself (or peers) access to pex 8524 registers. configuration requests can access those registers that are defined by pci-sig specifications, and generally cannot access device-specific regi sters other than the nt port cursor mechanism registers. memory requests can access all pex 8524 registers. configuration requests can access the nt port cursor mechanism registers (offsets f8h / fch ) to provide indirect access to nt port offsets above 100h, for conventional pci requesters such as a pci master connected to a pci express-to- pci bridge, that cannot generate conf iguration requests c ontaining an extended register number. the nt port virtual in terface cursor mechanism (but not the nt port link interface cursor mechanism) can access device-speci fic registers that exist in the nt port; if port 0 is the nt port, the nt port virtual interface cursor mechanism can access the device-specific regi sters (which exist only in port 0) and the station 0 registers (which exist in po rt 0 for all enabled ports in station 0). rw yes 0 1 disable unsupported re quest response for reserved configuration registers rw yes 0 23:2 factory test only rw yes 0-0h
nt port virtual interface registers plx technology, inc. 396 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 24 no snoop disable silicon revision aa not supported silicon revisions bb/bc forces the packet header no snoop attribut e bit to 0, for all packets transferred between the nt link and virtual interf aces (across the nt boundary, in both directions). can be used to handle cach e coherency-related issues in a system. 0 = disables no snoop disable feature 1 = enables no snoop disable feature rw yes 0 26:25 factory test o nly rw yes 00b 27 reserved silicon revision aa 0 bios enumeration fix disable silicon revisions bb/bc for nt failover in silicon revisi ons bb/bc, this bit must be set. rw yes 0 31:28 factory test o nly rw yes 0h register 15-39. 660h ingress control (only ports 0 and 8) (cont.) bit(s) description type serial eeprom default
february, 2007 pex 8524 non-transparent bridging-specific registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 397 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.13 pex 8524 non-transparent bridging-specific registers table 15-17 defines the register map of the registers implemented to support the pex 8524 non-transparent bridging function. the nt station contains the main copy of these registers, and the transparent station contains the shadow copy of these registers. thes e registers are accessed by memory-mapped access to port 0, port 8, or nt port. table 15-17. nt port virtual interface nt bridging-specific register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 nt port virtual interface memory address translation and bar limit registers c3ch ? c58h nt port virtual interface lookup table- based address translation registers c5ch ? d58h nt port link interface vc registers (shadow copy) d5ch ? d64h nt port virtual interface base address registers (bars) and bar setup registers (shadow copy) d68h ? d90h nt port virtual interface send lookup table entry registers d94h ? db0h reserved db4h ? df0h nt port link interface capture and vi rtual interface control registers (shadow copy) df4h df8h reserved dfch ? fb0h
nt port virtual interface registers plx technology, inc. 398 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.13.1 nt port virtual interface memory address translation and bar limit registers the nt station contains the main copy of these registers, and the transparent station contains the shadow copies of these registers. program only the main copy. the shadow register is automatically updated. the reverse is not true. the register map is defined in table 15-18 . note: the nt port virtual interface memo ry bar address translation (offsets c3ch, c44h and c48h) and memory bar limit (offsets c4ch, c54h and c58h) register values are shadowed to both stations. if software writes to these registers, the shadow registers are automatically updated; however, if the serial eeprom programs these registers, the shadow registers are not updated. therefore, if the serial eeprom is used to program initial values into these registers, software must read the registers and write back the values, to automatically update the shadow registers. table 15-18. nt port virtual interface memory address translation (bar limit) register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 memory bar2 address translation[31:0] c3ch reserved c40h memory bar4/5 addr ess translation[31:0] c44h memory bar4/5 address translation[63:32] c48h memory bar2 limit[31:0] c4ch reserved c50h memory bar4/5 limit[31:0] c54h memory bar5 limit[63:32] c58h register 15-40. c3ch memory bar2 address translation[31:0] bit(s) description type serial eeprom default 11:0 reserved 0-0h 31:12 bar2 base translation address[31:12] nt port virtual interface base translation address when the nt port virtual interface bar2 setup register bar2 enable bit (offset d4h [31]) is set to 1. rw yes 0-0h register 15-41. c44h memory bar4/5 address translation[31:0] bit(s) description type serial eeprom default 11:0 reserved 0-0h 31:12 bar4 base translation address[31:12] nt port virtual interface base translation address when the nt port virtual interface bar4/5 setup register bar4 enable bit (offset dch [31]) is set to 1. rw yes 0-0h
february, 2007 nt port virtual interface memory address translation and bar limit registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 399 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-42. c48h memory bar4/5 address translation[63:32] bit(s) description type serial eeprom default 31:0 bar4/5 base translation address[63:32] nt port virtual interface base translation upper address when bar4/5 is enabled as a 64-bit bar [ nt port virtual interface bar4/5 setup register bar4 type (offset dch [2:1]) and bar4 setup shadow register bar4 type (offset d8ch [2:1]) fields are both set to 10b]. rw yes 0-0h read-only when the nt port virtual interface bar4/5 setup register bar4 type (offset dch[2:1]) and bar4 setup shadow register bar4 type (offset d8ch[2:1]) fields are both cleared to 00b. ro no 0-0h register 15-43. c4ch memory bar2 limit[31:0] bit(s) description type serial eeprom default 11:0 reserved 0-0h 31:12 bar2 limit[31:0] contains the address of the memory window upper limit defined in the bar2 setup register (offset d84h ). 1 mb granularity. when the limit is greater than the window size, the limit is ignored. rw yes 000h register 15-44. c54h memory bar4/5 limit[31:0] bit(s) description type serial eeprom default 11:0 reserved 0-0h 31:12 bar4/5 limit[31:0] contains the address of the memory window lower limit defined in the bar4 setup register (offset d8ch ). 1 mb granularity. when the limit is greater than the window size, the limit is ignored. rw yes 0-0h register 15-45. c58h memory bar5 limit[63:32] bit(s) description type serial eeprom default 31:0 bar5 limit[63:32] contains the address of the memory window upper limit defined in the bar5 setup register (offset d90h ) when the nt port virtual interface bar4/5 setup register bar4 type (offset dch [2:1]) and bar4 setup shadow register bar4 type (offset d8ch [2:1]) fields are both set to 10b]. 1 mb granularity. when the limit is greater than th e window size, the limit is ignored. rw yes 0-0h read-only when the nt port virtual interface bar4/5 setup register bar4 type (offset dch[2:1]) and bar4 setup shadow register bar4 type (offset d8ch[2:1]) fields are both cleared to 00b. ro no 0-0h
nt port virtual interface registers plx technology, inc. 400 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.13.2 nt port virtual in terface lookup table-based address translation registers there are 64 base-translation lookup table (lut) entry registers to support the lut-based address translation. these registers are accessed using port 0, port 8, and the nt port virtual interface memory- mapped or cursor mechanism. table 15-19 defines the register and ad dress locations. the register description that follows defines the bit definitions that apply to all 64 registers. the nt station contains the main copy of these registers, and the transparent station contains the shadow copies of these registers. program only the main copy. the shadow register is automatically updated. the reverse is not true. note: the nt port virtual interface lookup table-based address translation (offsets c5ch through d58h) register values are shadowed to both stat ions. if software writes to these registers, the shadow registers are automatically updated; however, if the serial eeprom programs these registers, the shadow registers are not updated. therefore, if the se rial eeprom is used to program initial values into these registers, software must read the registers and write back the values, to automatically update the shadow registers. table 15-19. base-translation lookup table entry_ n register locations addr location lookup table entry_ n addr location lookup table entry_ n addr location lookup table entry_ n addr location lookup table entry_ n c5ch 0 c60h 1 c64h 2 c68h 3 c6ch 4 c70h 5 c74h 6 c78h 7 c7ch 8 c80h 9 c84h 10 c88h 11 c8ch 12 c90h 13 c94h 14 c98h 15 c9ch 17 ca0h 17 ca4h 18 ca8h 19 cach 20 cb0h 21 cb4h 22 cb8h 23 cbch 24 cc0h 25 cc4h 26 cc8h 27 ccch 28 cd0h 29 cd4h 30 cd8h 31 cdch 32 ce0h 33 ce4h 34 ce8h 35 cech 36 cf0h 37 cf4h 38 cf8h 39 cfch 40 d00h 41 d04h 42 d08h 43 d0ch 44 d10h 45 d14h 46 d18h 47 d1ch 48 d20h 49 d24h 50 d28h 51 d2ch 52 d30h 53 d34h 54 d38h 55 d3ch 56 d40h 57 d44h 58 d48h 59 d4ch 60 d50h 61 d54h 62 d58h 63
february, 2007 nt port virtual interface lookup table-based address translation registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 401 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-46. c5ch - d58h base-translation lookup table entry_ n (where n = 0 through 63) bit(s) description type serial eeprom default 0 entry status 0 = invalid 1 = valid rws yes 0 2:1 reserved 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable rw yes 0 11:4 reserved 00h 31:12 base translation base translation address value. rw yes 0-0h
nt port virtual interface registers plx technology, inc. 402 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.13.3 nt port link interface vc registers the registers in this section are shadow copies and valid only for port 0 and port 8. if port 0 or port 8 is an nt port, the register is in virtual interface configuration space. modify ing these registers is not recommended . table 15-20 defines the register map. table 15-20. nt port link interface vc shadow register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 nt link interface vc0 resource control (shadow copy) d5ch nt link interface vc 1 resource control (shadow copy) d60h nt link interface vc capability 1 (shadow copy) d64h
february, 2007 nt port link interface vc registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 403 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 15-47. d5ch nt link interface vc0 resource control (shadow copy) bit(s) description type serial eeprom default 0 tcvc_map[0] always mapped to virtual channel 0. ro yes 1 7:1 tcvc_map[7:1] mapped to virtual channel 0 by default. software can change this field during enumeration or when quiescing the traffic to the traffic class. rw yes 7fh 23:8 reserved 0000h 24 vc_id virtual channel identification number. ro yes 0 30:25 reserved 00h 31 vc_enable virtual channel 0 enable. ro yes 1 register 15-48. d60h nt link interface vc1 resource control (shadow copy) bit(s) description type serial eeprom default 0 reserved no 0 7:1 tcvc_map[7:1] mapped to virtual channel 1 by default. software can change this field during enumeration or when quiescing the traffic to the traffic class. rw yes 00h 23:8 reserved yes 0000h 24 vc_id virtual channel identification number. rw yes 1 30:25 reserved yes 00h 31 vc_enable virtual channel 1 enable. rw yes 0 register 15-49. d64h nt link interface vc capability 1 (shadow copy) bit(s) description type serial eeprom default 3:0 reserved no 0h 6:4 low-priority virtual channel count indicates the number of virtual cha nnels mapped to the low-priority group. ro yes 000b 31:7 reserved no 0000_00h
nt port virtual interface registers plx technology, inc. 404 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.13.4 nt port virtual interface base address registers (bars) andbarsetupregisters the registers in this section are shadow copies and valid only for port 0 and port 8. if port 0 or port 8 is an nt port, the register is in virtual interface configuration space. modifying these registers is not recommended. table 15-21 defines the register map. table 15-21. nt port virtual interface base address register (bar) and bar setup register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 bar0 = reserved d68h bar1 d6ch bar2 d70h bar3 d74h bar4 d78h bar5 d7ch bar1 setup d80h bar2 setup d84h bar3 setup d88h bar4 setup d8ch bar5 setup d90h
february, 2007 nt port virtual interface base address registers (bars) and bar setup registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 405 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: software (device driver) must copy the bar1 register value to the bar1 shadow register in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in the nt port virtual interface, offset 14h or d6ch, and write the value to port 8, offset d6ch if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset 14h or d6ch, and write the value to port 0, offset d6ch note: software (device driver) must copy the bar2 register value to the bar2 shadow register in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in the nt port virtual interface, offset 18h or d70h, and write the value to port 8, offset d70h if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset 18h or d70h, and write the value to port 0, offset d70h register 15-50. d6ch bar1 ( 14h shadow copy) bit(s) description type serial eeprom default 0 i/o space indicator 256-byte i/o bar when the nt port virtual interface bar1 setup register i/o bar1 enable field (offset d0h [1:0]) is set to 11b. ro yes 1 reserved when the nt port virtual interface bar1 setup register i/ o bar1 enable field (offset d0h[1:0]) is not set to 11b. 0 7:1 reserved 0h 31:8 i/o base address 256-byte i/o space ba se address when the nt port virtual interface bar1 setup register i/o bar1 enable field (offset d0h[1:0]) is set to 11b. rw yes 0000_00h reserved when the nt port virtual interface bar1 setup register i/ o bar1 enable field (offset d0h[1:0]) is not set to 11b. 00000_00h register 15-51. d70h bar2 ( 18h shadow copy) bit(s) description type serial eeprom default 0 memory space indicator 0 = memory bar ? only value supported ro yes 0 2:1 memory map type 00b = bar is mapped anywhere in 32-bit memory space 01b, 10b, 11b = reserved ro yes 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable ro yes 0 11:4 reserved 00h 31:12 base address 2 contains the software-assigned memory space base address: enabled and sized by bar2 setup register (offset d84h ) used for memory transactions crossing the nt port minimum address range requested is 4 kb uses direct address translation rw yes 0000_0h
nt port virtual interface registers plx technology, inc. 406 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: software (device driver) must copy the bar3 register value to the bar3 shadow register in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in the nt port virtual interface, offset 1ch or d74h, and write the value to port 8, offset d74h if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset 1ch or d74h, and write the value to port 0, offset d74h register 15-52. d74h bar3 ( 1ch shadow copy) bit(s) description type serial eeprom default 0 memory space indicator 0 = memory bar ? only value supported ro yes 0 2:1 memory map type 00b = bar is mapped anywhere in 32-bit memory address space 01b, 10b, 11b = reserved ro yes 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable ro yes 0 17:4 reserved 0000h 31:18 base address 3 contains the software-assigne d memory space base address: enabled and sized by bar3 setup register (offset d88h ) no limit register used for memory transact ions crossing the nt port minimum address range requested is 256 kb uses lut address translation rw yes 0000h
february, 2007 nt port virtual interface base address registers (bars) and bar setup registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 407 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: software (device driver) must copy the bar4 register value to the bar4 shadow register in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in the nt port virtual interface, offset 20h or d78h, and write the value to port 8, offset d78h if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset 20h or d78h, and write the value to port 0, offset d78h note: software (device driver) must copy the bar5 register value to the bar5 shadow register in the non-nt station: if the nt port is one of ports 0 through 3, software must read the value in the nt port virtual interface, offset 24h or d7ch, and write the value to port 8, offset d7ch if the nt port is one of ports 8 through 11, software must read the value in the nt port virtual interface, offset 24h or d7ch, and write the value to port 0, offset d7ch register 15-53. d78h bar4 ( 20h shadow copy) bit(s) description type serial eeprom default 0 memory space indicator 0 = memory bar ? only value supported ro yes 0 2:1 memory map type 00b = mappable anywhere in 32-bit memory space 10b = mappable anywhere in 64-bit memory space 01b, 11b = reserved ro yes 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable ro yes 0 11:4 reserved 00h 31:12 base address 4 contains the software-assigned memory space base address: enabled and sized by bar4 setup register (offset d8ch ) used for memory transactions crossing the nt port minimum address range requested is 4 kb uses direct address translation rw yes 0000_0h register 15-54. d7ch bar5 ( 24h shadow copy) bit(s) description type serial eeprom default 31:0 base address 5 nt port virtual interface upper 32-bit address when the nt port virtual interface bar4/5 setup register bar4 type field (offset dch [2:1]) is set to 10b. rw, based on bar5 setup register. the bar4/5 group uses direct address translation. rw yes 0-0h reserved when the nt port virtual interface bar4/5 setup register bar4 type field (offset dch[2:1]) is cleared to 00b. 0-0h
nt port virtual interface registers plx technology, inc. 408 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: register offset d84h must be programmed with the same value as the nt port virtual interface bar2 setup register (offset d4h ). this requirement applies only to the nt virtual interface. register 15-55. d80h bar1 setup ( d0h shadow copy) bit(s) description type serial eeprom default 1:0 i/o bar1 enable 11b = enables virtual interface bar1 as an i/o bar all other values disable bar1 . rw yes 11b 31:2 reserved 0-0h register 15-56. d84h bar2 setup ( d4h shadow copy) bit(s) description type serial eeprom default 0 reserved 0 2:1 bar2 type 00b = selects 32-bit memory bar no other values are allowed. rw yes 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable rw yes 0 11:4 reserved 00h 30:12 bar2 size specifies the address ra nge size requested by bar2 . 0 = corresponding bits in bar2 are read-only bits that always return 0, and writes are ignored 1 = corresponding bits in bar2 are rw bits rw yes 0000_0h 31 bar2 enable 0 = bar2 is disabled, all bits in bar2 read 0 1 = bar2 is enabled, size and type specified in this register rw yes 0
february, 2007 nt port virtual interface base address registers (bars) and bar setup registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 409 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: register offset d88h must be programmed with the same value as the nt port virtual interface bar3 setup register (offset d8h ). this requirement applies only to the nt virtual interface. register 15-57. d88h bar3 setup ( d8h shadow copy) bit(s) description type serial eeprom default 0 prefetchable 0 = non-prefetchable 1 = prefetchable rw yes 0 15:1 reserved 0-0h 19:16 lut page size virtual bar3 address range. the total size of this range is dependent on the page size. when the bar3 lut page size extension bit value is 0, the encodings are as follows: when the bar3 lut page size extension bit value is 1, the encodings are as follows: 0h = 8 mb 1h = 16 mb 2h = 32 mb 3h to fh = reserved rw yes 0h 20 lut page size extension allows selection of larger page size s when programming page size[19:16]. 0 = page sizes 4 kb through 4 mb are available in page size[19:16] 1 = page sizes 8 through 32 mb are available in page size[19:16] rw yes 0 31:21 reserved 000h 0h = disables bar3 ah = 128 kb 1h to 4h = reserved bh = 256 kb 5h = 4 kb ch = 512 kb 6h = 8 kb dh = 1 mb 7h = 16 kb eh = 2 mb 8h = 32 kb fh = 4 mb 9h = 64 kb
nt port virtual interface registers plx technology, inc. 410 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: register offset d8ch must be programmed with the same value as the nt port virtual interface bar4/5 setup register (offset dch ). this requirement applies only to the nt virtual interface. register 15-58. d8ch bar4 setup ( dch shadow copy) bit(s) description type serial eeprom default 0 reserved 0 2:1 bar4 type 00b = selects 32-bit memory bar 10b = selects 64-bit memory bar note: it is illegal to program 10b and clear the bar5 setup register bar5 enable bit (offset d90h [31]). rw yes 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable rw yes 0 11:4 reserved 00h 30:12 bar4 size specifies the address ra nge size requested by bar4 . 0 = corresponding bits in bar4 are read-only bits that always return 0, and writes are ignored 1 = corresponding bits in bar4 are rw bits rw yes 0000_0h 31 bar4 enable when bits [2:1] = 00b, enables bar4 ; otherwise, belongs to the bar4 size [30:12] field. 0 = bar4 is disabled, all bits in bar4 read 0 1 = bar4 is enabled, size and type specified in this register rw yes 0
february, 2007 nt port virtual interface base address registers (bars) and bar setup registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 411 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: register offset d90h must be programmed with the same value as the nt port virtual interface bar5 setup register (offset e0h ). this requirement applies only to the nt virtual interface. register 15-59. d90h bar5 setup ( e0h shadow copy) bit(s) description type serial eeprom default 30:0 bar5 size together with the bar4 setup register bar4 size field (offset d8ch [31:12]), specifies the address ra nge size requested by bar4/5 in 64-bit mode when the bar4 setup register bar4 type field (offset d8ch[2:1]) is set to 10b. 0 = corresponding bits in bar5 are read-only bits th at always return 0, and writes are ignored 1 = corresponding bits in bar5 are rw bits rw yes 0-0h reserved when the bar4 setup register bar4 type field (offset d8ch[2:1]) is cleared to 00b. 0-0h 31 bar5 enable 0 = bar5 is disabled 1 = bar5 is enabled when the bar4 setup register bar4 type field (offset d8ch[2:1]) is set to 10b note: it is illegal to program 10b and clear the bar5 setup register bar5 enable bit (offset d90h [31]). rw yes 0 reserved when the bar4 setup register bar4 type field (offset d8ch[2:1]) is cleared to 00b. 0
nt port virtual interface registers plx technology, inc. 412 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.13.5 nt port virtual interface se nd lookup table entry registers this section describes the nt port virtual interf ace send (requester id translation) lookup table (lut) entry registers. the nt port uses these regist ers for requester id translation when it forwards: memory requests from nt port virtual interface to the nt port link interface, or completion tlp from nt port link inte rface to the nt port virtual interface the nt station contains the main copy of these registers, and the transparent station contains the shadow copies of these registers. program only the main copy. the shadow register is automatically updated. the reverse is not true. table 15-22 defines the register and address locations. th e register descriptions that follow the table define the bit definitions that apply to the two register types. note: software must copy the values to the same offsets in the non-nt station (port 0 or port 8). if the nt port is one of ports 8 through 11, software must read the value(s) in the nt port virtual interface and write the value(s) to the same offs ets (d94h through db0h, respectively) in port 0; if the nt port is one of ports 0 through 3, software must read the value(s) in the nt port virtual interface and write the value(s) to the same offsets (d94h through db0h) in port 8. table 15-22. nt port virtual interface send lookup table entry_ n register locations addr location lookup table entry_ n addr location lookup table entry_ n d94h 0 da4h 4 d98h 1 da8h 5 d9ch 2 dach 6 da0h 3 db0h 7 register 15-60. d94h - db0h virtual interface send lookup table entry_ n (where n = 0 through 7) bit(s) description type serial eeprom default 2:0 requester id function number lut entry_ n requester function number. rw yes 000b 7:3 device number lut entry_ n requester device number. rw yes 0000_0b 15:8 bus number lut entry_ n requester bus number. rw yes 00h 30:16 reserved 0-0h 31 lut entry_ n enable 0 = disables 1 = enables rw yes 0
february, 2007 nt port link interface capture and virtual interface control registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 413 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.13.6 nt port link interface capture and virtual interface control registers note: the nt port link interface ca pture bus and device number register (offset df4h) exists only in the non-nt station (port 0 or port 8), and must be programmed by software: if the nt port is one of ports 0 through 3, software must program the nt port link interface bus and device numbers into port 8, offset df4h if the nt port is one of ports 8 through 11, software must program the nt port link interface bus and device numbers into port 0, offset df4h the device number should normally be 0000_0b; therefore, software should only need to program the bus number, if the bus number is not 00h (default). note: the nt port virtual interface control register (offset df8h) exists in only in the non-nt station (port 0 or port 8), and must be programmed by software indirectly by programming the nt port virtual interface status/command register (offset 04h , normally programmed by system software): if the nt port is one of ports 0 through 3, this shadow register exists only in port 8 if the nt port is one of ports 8 through 11, this shadow register exists only in port 0 (offset df8h) table 15-23. nt port link interface capture and virtual interface control register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 nt port link interface capture bus and device number df4h nt port virtual interface control (shadow copy) df8h register 15-61. df4h nt port link interface capture bus and device number bit(s) description type serial eeprom default 7:0 captured bus number rw yes 00h 12:8 captured device number rw yes 0000_0b 31:13 reserved 0-0h register 15-62. df8h nt port virtual interface control ( 04h [2:0] shadow copy) bit(s) description type serial eeprom default 0 i/o access enable 0 = disables 1 = enables rw yes 0 1 memory access enable 0 = disables 1 = enables rw yes 0 2 bus master enable 0 = disables 1 = enables rw yes 0 31:3 reserved 0-0h
nt port virtual interface registers plx technology, inc. 414 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 15.14 advanced error reporting capability registers the advanced error reporting capabi lity registers for the nt port virtual interface are equivalent to those defined in section 11.14, ?advanced error reporting capability registers.? the registers are duplicated for the nt port virtual interface, and table 15-24 defines the register map. table 15-24. advanced error reporting capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next capability offset ( 138h ) capability ve r s i o n ( 1h ) pci express extended capability id ( 0001h )fb4h uncorrectable error status fb8h uncorrectable error mask fbch uncorrectable error severity fc0h correctable error status fc4h correctable error mask fc8h advanced error capa bilities and control fcch header log_0 fd0h header log_1 fd4h header log_2 fd8h header log_3 fdch reserved fe0h ? ffch
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 415 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 16 nt port link interface registers 16.1 introduction this chapter defines the pex 8524 non-transparent (nt) port link interf ace (interface) registers. the nt port includes two sets of conf iguration, capability, control, a nd status registers to support the virtual and link interfaces. the nt port link interface regist er mapping is defined in table 16-1 . nt port virtual interface registers are defined in chapter 15, ?nt port virtual interface registers.? transparent mode registers are defined in chapter 11, ?pex 8524 transpar ent mode port registers.? for further details regarding register names and descriptions, refer to the following specifications: pci r2.3 pci power mgmt. r1.1 pci express base r1.0a
nt port link interface registers plx technology, inc. 416 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 table 16-1. nt port link interface type 0 register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 00h ? configuration header registers new capability pointer ( 40h )34h ? 3ch next capability pointer ( 48h ) capability id ( 01h )40h power management ca pability registers 44h next capability pointer ( 68h ) capability id ( 05h )48h message signaled interrupt capability registers ? 64h next capability pointer ( 00h ) capability id ( 10h )68h pci express capa bility registers ? 8ch nt port registers 90h ? fch next capability offset ( fb4h ) 1h extended capability id ( 0003h ) 100h device serial number extended capability registers 104h 108h reserved 10ch ? 134h next capability offset ( 148h ) 1h extended capability id ( 0004h ) 138h power budgeting extended capability registers ? 144h next capability offset ( 000h ) 1h extended capability id ( 0002h ) 148h virtual channel extended capability registers ? 1c4h plx-specific registers 1c8h ? c08h pex 8524 non-transparent bridging-specific registers c3ch ? fb0h next capability offset ( 138h ) 1h pci express exte nded capability id ( 0001h )fb4h advanced error reporting capability registers ? ffch
february, 2007 register access expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 417 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.2 register access the pex 8524 nt port link interface implements a 4-kb configuration space. the lower 256 bytes (offsets 00h through ffh) is the pci-compatible configuration space, and the upper 960 dwords (offsets 100h through fffh) is the pci e xpress extended configurati on space. the pex 8524 supports four mechanisms for accessing nt port link interface registers: pci express base r1.0a configuration mechanism plx-specific memory-mapped configuration mechanism plx-specific i/o-mapped co nfiguration mechanism plx-specific cursor mechanism 16.2.1 pci express base r1.0a configuration mechanism the pci express configuration mechanism is divided into two mechanisms: pci r2.3 -compatible configuration pci express enhanced configuration the pci r2.3-compatible configuration mechanism provides standard access to the first 256 bytes (the bytes at offsets 00h through ffh) of the nt port link interface co nfiguration register space. the pci express enhanced conf iguration mechanism provides access to the remaining 4 kb (offsets 100h through fffh). the pex 8524 decodes type 0 confi guration transactions received on its nt port link interface. the pex 8524 reads or writes to the nt port link inte rface register, as specified in the original type 0 configuration access. 16.2.1.1 pci r2.3 -compatible configuration mechanism the pci r2.3 -compatible configuration space consists of the first 256 bytes of the nt port link interface configuration space. (refer to figure 16-1 .) the pci r2.3 -compatible configuration mechanism provides standard access to the pex 8524 nt port link interface?s first 256 bytes (the bytes at offsets 00h through ffh) of the pci express conf iguration space. this m echanism is used to access the pex 8524 nt port link interf ace type 0 (pci endpoint) registers: configuration header registers power management capability registers message signaled interrupt capability registers pci express capability registers because the pci r2.3 -compatible configuration mechanism is limited to the first 256 bytes of the nt port link interface configurati on register space, one of the fo llowing must be used to access beyond byte ffh: pci express enhanced co nfiguration mechanism plx-specific memory-mapped configuration mechanism plx-specific cursor mechanism the pci r2.3 -compatible configuration mechanism uses th e same request format as the extended pci express mechanism. for pci-compatible configurat ion requests, the extended register address field must be all zeros (0). do not use this mechanism to access the pe x 8524 device-specific configuration registers.
nt port link interface registers plx technology, inc. 418 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.2.1.2 pci express enhanced configuration mechanism the pci express enhanced configuration mechanism uses a flat, root complex memory-mapped address space to access device configuration registers. in this case, the memory address determines the configuration register accessed, an d memory data returns the addres sed register contents. the root complex converts the memory transaction into a configuration transaction before transmitting this access to the downstream devices. this mechanism is used to access the nt port link interface type 0 registers: configuration header registers power management capability registers message signaled interrupt capability registers pci express capability registers device serial number extended capability registers power budgeting extended capability registers virtual channel extended capability registers advanced error reporting capability registers
february, 2007 plx-specific memory-mapped configuration mechanism expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 419 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.2.2 plx-specific memory-m apped configuration mechanism the plx-specific memory-mapped configuration mechanism provides a method to access the pex 8524 port configuration registers of all ports in a single memory map, as illustrated in figure 16-1 . the registers of each port are contained within a 4-kb range. when the nt port is enabled at fundamental reset, the nt port virtual and link interface configuration registers are used in place of the type 1 configuration registers for that port. to utilize the plx-specific memory-ma pped configuration mechanism, use the pci r2.3 -compatible configuration mechanism to program the pex 8524 nt port link interface base address 0 register. after the nt port li nk interface memory-mapped base address re gister is set, the nt port registers are accessed with memory reads from and writes to configuration space registers. the nt port registers are accessed with memory reads from and writes to the 4- kb range, starting at offset 64 kb for the virtual interface registers and of fset 68 kb for link interface registers. figure 16-1. pex 8524 register offset from upstream port bar0/1 base address (non-transparent mode) port 0 port 1 reserved port 8 port 9 port 10 port 11 reserved reserved pex 8524 nt port virtual interface nt port link interface 0 kb 4 kb 8 kb 32 kb 36 kb 40 kb 44 kb 48 kb 64 kb 72 kb 68 kb 128 kb
nt port link interface registers plx technology, inc. 420 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.2.3 plx-specific i/o-map ped configuration mechanism the first 256 bytes of nt port link interface confi guration space registers ar e directly accessed by an i/o transaction. the nt port link interface bar1 re gister is used for i/o- mapped access. (refer to figure 16-2 .) extended configuration space re gisters are accessed by using the cursor mechanism in i/o space. figure 16-2. i/o-mapped configuration space view 16.2.4 plx-specific cursor mechanism in figure 16-2 , the software uses the configuration address window (cfgaddr) register to select the nt port virtual or link interface configur ation space registers, including the extended configuration space register. software uses the configuration data window (cfgdata) register to write to or read from the selected configurat ion space registers. refer to section 16.8.4, ?nt port cursor mechanism control registers,? for the register descriptions. 16.3 register descriptions the remainder of this chapter details the pex 8 524 nt port link interface registers, including: bit/field names description of register functions in the pex 8524 nt port link and virtual interfaces type ( such as rw or hwinit; refer to table 11-3, ?register types, grouped by user accessibility.? for type descriptions) whether the power-on/reset value can be modified, by way of the pex 8524 serial eeprom initialization feature default power-on/reset value cfgaddr cfgdata 00h f4h f8h fch 100h ffch 32 bits pci-compatible configuration space extended configuration space bar1 (i/o bar) 31 0 7
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 421 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.4 configuration header registers table 16-2. type 0 configuration space header register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 device id vendor id 00h status command 04h class code revision id 08h bist (not supported) configuration layout type and function type master latency timer cache line size 0ch base address 0 10h base address 1 14h base address 2 18h base address 3 1ch base address 4 20h base address 5 24h reserved 28h subsystem id subsystem vendor id 2ch expansion rom base address 30h reserved new capability pointer ( 40h ) 34h reserved 38h reserved interrupt pin interrupt line 3ch register 16-1. 00h product identification bit(s) description type serial eeprom default 15:0 vendor id unless overwritten by the serial eeprom, returns the plx pci-sig-assigned vendor id. the pex 8524 serial eeprom register initialization capability is used to replace the plx vendor id with another vendor id. hwinit yes 10b5h 31:16 device id unless overwritten by the serial eeprom, the pex 8524 returns 8532h (680-ball package) or 8524h (644-ball package), the plx- assigned device id. the pex 8524 serial eeprom register initialization capability is us ed to replace the plx-assigned device id with another device id. hwinit yes 8532h (680-ball package) 8524h (644-ball package)
nt port link interface registers plx technology, inc. 422 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-2. 04h status/command bit(s) description type serial eeprom default command 0 i/o access enable 0 = pex 8524 ignores i/o requests rece ived on the nt port link interface 1 = pex 8524 accepts i/o requests rece ived on the nt port link interface rw yes 0 1 memory access enable 0 = pex 8524 ignores memory requests rece ived on the nt port link interface 1 = pex 8524 accepts memory requests re ceived on the nt port link interface rw yes 0 2 bus master enable controls pex 8524 memory request fo rwarding in the upstream direction. does not affect message forwarding and co mpletions in the upstream direction. 0 = pex 8524 handles memory requests received on the nt port virtual interface as unsupported requests (ur) ; for non-posted requests, pex 8524 returns a completion with ur completion status 1 = pex 8524 forwards memory requests from the nt port virtual interface to the link interface in the upstream direction rw yes 0 3 special cycle enable cleared to 0, as required by the pci express base r1.0a . ro no 0 4 memory write and invalidate cleared to 0, as required by the pci express base r1.0a . ro no 0 5 vga palette snoop cleared to 0, as required by the pci express base r1.0a . ro no 0 6 parity error response enable controls the master data parity error . rw yes 0 7 idsel stepping/wait cycle control cleared to 0, as required by the pci express base r1.0a . ro no 0 8 serr# enable controls the signaled system error bit. when 1, enables reporting of fatal and non-fatal errors detected by the nt po rt link interface to the root complex. rw yes 0 9 fast back-to-back transactions enabled cleared to 0, as required by the pci express base r1.0a . ro no 0 10 interrupt disable 0 = nt port link interface is enabled to generate int x interrupt messages 1 = nt port link interface is prevented from generating int x interrupt messages rw yes 0 15:11 reserved 00h
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 423 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 status 18:16 reserved 000b 19 interrupt status 0 = no int x interrupt pending 1 = int x interrupt pending internally to nt port link interface ro yes 0 20 capabilities list set to 1, as required by the pci express base r1.0a . ro yes 1 21 66 mhz capable cleared to 0, as required by the pci express base r1.0a . ro no 0 22 reserved 0 23 fast back-to-back transactions capable cleared to 0, as required by the pci express base r1.0a . ro no 0 24 master data parity error if the parity error response enable bit is set to 1, the nt port link interface sets this bit to 1 when the nt port: forwards the poisoned tlp write request from the virtual interface to the link interface, or receives a completion marked as poisoned on the link interface if the parity error response enable bit is cleared to 0, the pex 8524 never sets this bit. this error is natively reported by the uncorrectable error status register poisoned tlp status bit (offset fb8h [12]), which is mapped to this bit for conventional pci backward compatibility. rw1c yes 0 26:25 devsel timing not supported always cleared to 00b. ro no 00b 27 signaled target abort when a memory-mapped access payload length is greater than one dword, the nt port link interface sets this bit to 1. this bit is also set to 1 when the nt port forwards a completion with completer abort (ca) status from the virtual interface to the link interface. note: when set during a forwarded completion, the uncorrectable error status register completer abort status bit (offset fb8h [ 15 ]) is not updated, because the nt port does not log the requests that it forwards. rw1c yes 0 register 16-2. 04h status/command (cont.) bit(s) description type serial eeprom default
nt port link interface registers plx technology, inc. 424 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 28 received target abort cleared to 0. never set to 1. ro no 0 29 received master abort cleared to 0. never set to 1. ro no 0 30 signaled system error when the serr# enable bit is set to 1, the nt port link interface sets this bit to 1 when it transmits an err_fata l or err_nonfatal message to its upstream device. this error is natively reported by the device status register fatal error detected and non-fatal error detected bits (offset 70h [18:17], respectively), which are mapped to this bit for conventional pci backward compatibility. rw1c yes 0 31 detected parity error the nt port link interface sets this bit to 1 when it receives a poisoned tlp, regardless of the parity error response enable bit state. this error is natively reported by the uncorrectable error status register poisoned tlp status bit (offset fb8h [12]), which is mapped to this bit for conventional pci backward compatibility. rw1c yes 0 register 16-3. 08h class code and revision id bit(s) description type serial eeprom default 7:0 revision id unless overwritten by the serial eeprom, returns the silicon revision (aah, bbh, or bch for pex 8524v; bbh or bch for pex 8524), plx-assigned revision id for this version of th e pex 8524. the pex 8524 serial eeprom register initialization capability is used to replace the plx revision id with another revision id. note: silicon revision bb only ? bit 0 is hardwired to 1 and is not programmable by serial eeprom. silicon revi sion bc only ? bits [2:0] are hardwired to 100b and are not programmable by serial eeprom. ro ye s (refer to note) aah, bbh, or bch (pex 8524v) or bbh or bch (pex 8524) class code 068000h 15:8 programming interface cleared to 00h, as required by the pci r2.3 for other bridge devices. ro yes 00h 23:16 sub-class code other bridge devices. ro yes 80h 31:24 base class code bridge devices. ro yes 06h register 16-2. 04h status/command (cont.) bit(s) description type serial eeprom default
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 425 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-4. 0ch miscellaneous control bit(s) description type serial eeprom default 7:0 cache line size implemented as a read-write field for conventional pci compatibility purposes and does not impact pe x 8524 functionality. rw yes 00h 15:8 master latency timer cleared to 00h, as required by the pci express base r1.0a . ro no 00h 22:16 configuration layout type type 0 configuration header for nt port. ro yes 00h 23 function type 0 = pex 8524 is a single-function device ro yes 0 31:24 bist not supported ro no 00h register 16-5. 10h base address 0 (for nt port link interface) bit(s) description type serial eeprom default 0 memory space indicator when enabled, the base address register maps pex 8524 port configuration registers into memory space. nt port link bar0 is configured by the serial eeprom and local host. by default, the bar setup register se lects 32-bit memory bar0 and 32-bit i/ o bar1 for csr mapping. note: hardwired to 0. ro no 0 2:1 memory map type 00b = pex 8524 configuration registers ar e mapped anywhere in 32-bit memory address space only ro yes 00b 3 prefetchable the base address register maps pe x 8524 configuration registers into non-prefetchable memory space by default. note: hardwired to 0. ro no 0 16:4 reserved 0-0h 31:17 base address 0 128-kb base address in which to map the pex 8524 configuration space registers into memory space. rw yes 0000h
nt port link interface registers plx technology, inc. 426 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-6. 14h base address 1 bit(s) description type serial eeprom default 0 i/o space indicator 0 = reserved 1 = implemented as an i/o bar ro yes 1 7:1 reserved 0000_000b 31:8 i/o base address 256-byte i/o space base address. for the nt port link interface, when offset e4h [1:0]=11b, this bar is enabled. rw yes 0000_00h register 16-7. 18h base address 2 bit(s) description type serial eeprom default 0 memory space indicator 0 = implemented as a memory bar; otherwise, reserved ro yes 0 2:1 memory map type 00b = mappable anywhere in 32-bit memory space 10b = mappable anywhere in 64-bit memory space 01b, 11b = reserved ro yes 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable ro yes 0 11:4 reserved 00h 31:12 base address 2 base address is enabled and sized by the nt port link interface bar2/3 setup register. this bar2/bar3 group uses dire ct address translation. the minimum bar size is programmed to 4 kb. rw yes 0000_0h register 16-8. 1ch base address 3 bit(s) description type serial eeprom default 31:0 upper base address nt port link interface upper 32-bit address if bar2/3 is implemented as a 64-bit bar; otherwise, reserved . these fields are rw, based on the nt port link interface bar2/3 setup and nt port link interface bar3 setup registers. the bar2/3 group uses dire ct address translation. rw yes 0-0h
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 427 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-9. 20h base address 4 bit(s) description type serial eeprom default 0 memory space indicator 0 = implemented as a memory bar; otherwise, reserved ro yes 0 2:1 memory map type 00b = mappable anywhere in 32-bit memory space 10b = mappable anywhere in 64-bit memory space 01b, 11b = reserved ro yes 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable ro yes 0 11:4 reserved 00h 31:12 base address 4 base address size is se t, and enabled by the nt port link interface bar4/5 setup register. the bar4/5 group uses direct address translation. the minimum bar size is programmed to 4 kb. rw yes 0000_0h register 16-10. 24h base address 5 bit(s) description type serial eeprom default 31:0 base address 5 nt port link interface upper 32-bit ad dress if bar4/5 is implemented as a 64-bit bar; otherwise, reserved . these fields are rw, based on the nt port link interface bar4/5 setup and nt port link interface bar5 setup registers. the bar4/5 group uses direct address translation. rw yes 0-0h register 16-11. 2ch subsystem id and subsystem vendor id bit(s) description type serial eeprom default 15:0 subsystem vendor id unless overwritten by the serial eeprom, returns the plx pci-sig-assigned vendor id. the pex 8524 serial eeprom register initialization capability is used to replace the plx vendor id with another vendor id. hwinit yes 10b5h 31:16 subsystem id unless overwritten by the se rial eeprom, 8532h is returned by the pex 8524v and 8524h is returned by the pex 8524, the plx-assigned device id. the pex 8524 serial eeprom register initialization capability is used to replace the plx-assigned device id wi th another device id. hwinit yes 8532h (pex 8524v) 8524h (pex 8524)
nt port link interface registers plx technology, inc. 428 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-12. 30h expansion rom base address bit(s) description type serial eeprom default silicon revision aa 0 expansion rom enable 0 = expansion rom is disabled 1 = expansion rom is enabled rw yes 1 10:1 reserved 0-0h 31:11 expansion rom base address expansion rom = 2 kb size (program register initially to ffff_f801h). note: expansion rom size is limited to 2 kb. if expansion rom is enabled in silicon revision aa, this register must be programmed to the value for 2 kb, ffff_f801h. rw yes 0-0h silicon revi sions bb/bc 0 expansion rom enable 0 = expansion rom is disabled 1 = expansion rom is enabled rw yes 1 14:1 reserved 0-0h 31:15 expansion rom base address expansion rom = 32 kb maximum size (program register initially to ffff_8001h). note: this bar must no t be programmed to enable more than 32 kb. expansion rom is limited to 32 kb, bec ause the largest serial eeprom that can be used is 64 kb (limit of 16-bi t addressing) and the expansion rom image is stored in the serial eepr om, beginning at address 32 kb. rw yes 0-0h
february, 2007 configuration header registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 429 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-13. 34h new capabilities pointer bit(s) description type serial eeprom default 7:0 new capability pointer default 40h points to the power management capabilities register. do not change this register value. ro yes 40h 31:8 reserved 0000_00h register 16-14. 3ch interrupt bit(s) description type serial eeprom default 7:0 interrupt line interrupt line routing value communicate s interrupt line r outing information. values in this register are programme d by system software and are system architecture-specific. the value is used by device drivers and operating systems. rw yes 00h 15:8 interrupt pin identifies the conventional pci interrupt message(s) the device (or device function) uses. when values = 01h, 02h, 03h, and 04h, maps to conventional pci interrupt messages for inta#, intb#, intc#, and intd#, respectively. when 0, indicates that the devi ce does not use conventional pci interrupt message(s). only values 00h or 01h are allowed in the pex 8524. ro yes 01h 31:16 reserved 0000h
nt port link interface registers plx technology, inc. 430 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.5 power management capability registers this section details the nt port link interface power management registers. the register map is defined in table 16-3 . table 16-3. power management capability register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 power management capabilities next capability pointer ( 48h ) capability id ( 01h ) 40h data power management control/ status bridge extensions power management st atus and control 44h register 16-15. 40h power management capabilities bit(s) description type serial eeprom default 7:0 capability id default = 01h ? only value allowed. indicates that the data structure currently being pointed to is the pci power management data structure. ro yes 01h 15:8 next capability pointer default 48h points to the message signaled interrupt capability register. ro yes 48h 18:16 ve rs io n default = 010b ? only value allowed. ro yes 010b 19 pme clock cleared to 0, as required by the pci express base r1.0a . ro no 0 20 reserved 0 21 device-specific initialization default 0 indicates that devi ce-specific initialization is not required. ro yes 0 24:22 aux current not supported default 000b indicates that the pex 8524 does not support auxiliary current requirements. ro yes 000b 25 d1 support not supported default 0 indicates th at the pex 8524 does not support the d1 power state. ro no 0 26 d2 support not supported default 0 indicates th at the pex 8524 does not support the d2 power state. ro no 0 31:27 pme support default 0000_0b indicates that the nt port link interface does not forward pme messages. ro yes 0000_0b
february, 2007 power manage ment capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 431 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-16. 44h power management status and control bit(s) description type serial eeprom default power management status and control 1:0 power state this field is used to determine the current power state of the port, and to set the port into a new power state. 00b = d0 01b = d1 ? not supported 10b = d2 ? not supported 11b = d3hot if software attempts to write an unsupported state to this field, the write operation completes normally; however, the data is discarded and no state change occurs. rw yes 00b 7:2 reserved ro no 0h 8 pme enable 0 = disables pme generation ro no 0 a a. because the pex 8524 does not suppor t auxiliary power, this bi t is not sticky, and is always cleared to 0 at power-on reset. 12:9 data select rw by serial eeprom mode only b . bits [12:9] select the data and data scale registers. 0h = d0 power consumed 3h = d3hot power consumed 4h = d0 power dissipated 7h = d3hot power dissipated ro yes 0h 14:13 data scale rw by serial eeprom mode only b . there are four internal data scale registers per port. bits [12:9], data select , select the data scale register. ro yes 00b 15 pme status 0 = pme is not being ge nerated by the nt port ro no 0 a power management control/status bridge extensions 21:16 reserved 0-0h 22 b2/b3 support cleared to 0, as required by the pci express base r1.0a . ro no 0 23 bus power/clock control enable cleared to 0, as required by the pci express base r1.0a . ro no 0 power management data 31:24 data rw by serial eeprom mode only b . there are four internal data registers per port. bits [12:9], data select , select the data register. b. with no serial eeprom, reads return 0h for the data scale and data registers (for al l data selects). ro yes 00h
nt port link interface registers plx technology, inc. 432 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.6 message signaled interrupt capability registers the message signaled interrupt (msi) ca pability registers are defined in section 11.8, ?message signaled interrupt capability registers.? table 16-4 defines the register map used by the nt port link interface. table 16-4. message signaled interrupt capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 message control next capability pointer ( 68h ) capability id ( 05h ) 48h message address[31:0] 4ch message upper address[63:32] 50h reserved message data 54h reserved 58h ? 64h
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 433 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.7 pci express capability registers this section details the pex 8524 pci express capability registers. the register map is defined in table 16-5 . table 16-5. pci express capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 pci express capabilities next capability pointer ( 00h ) capability id ( 10h ) 68h device capabilities 6ch device status device control 70h link capabilities 74h link status link control 78h reserved 7ch ? 8ch register 16-17. 68h pci express capability list and capabilities bit(s) description type serial eeprom default pci express capability list 7:0 capability id set to 10h by default. ro yes 10h 15:8 next capability pointer 00h = pci express capability is the last capability in the first 256-byte configuration space of the pex 8524 nt port link interface capability list the pex 8524 nt port link interface capabilities li st starts at 100h . ro yes 00h pci express capabilities 19:16 capability version the pex 8524 nt port link interface sets th is field to 1h, as required by the pci express base r1.0a . ro yes 1h 23:20 device/port type default = pci express endpoint device. ro yes 0h 24 slot implemented not implemented in the nt port interface. ro no 0 29:25 interrupt message number the serial eeprom writes 0000_0b, because the base message and msi messages are the same. ro yes 0000_0b 31:30 reserved 00b
nt port link interface registers plx technology, inc. 434 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-18. 6ch device capabilities bit(s) description type serial eeprom default 2:0 maximum payload size supported 000b = nt port link interface sup ports 128-byte maximum payload 001b = nt port link interface sup ports 256-byte maximum payload no other values are supported. note: serial eeprom must not load greater than 256 bytes maximum payload size. ro yes 001b 4:3 phantom functions supported not supported cleared to 00b. ro yes 00b 5 extended tag field supported not supported 0 = maximum tag field is 5 bits 1 = maximum tag field is 8 bits ro yes 0 8:6 endpoint l0s acceptable latency ro yes 000b 11:9 endpoint l1 acceptable latency ro yes 000b 12 attention button present for the nt port link interface, this bit, value of 1 indicates that an attention button is implemented on that adapter board. the pex 8524 serial eeprom register initial ization capability is used to change this value to 0, indicating that an attention button is not present on an adapter board for which the pex 8524 provides the system interface. hwinit yes 1 13 attention indicator present for the nt port link interface, this bit, value of 1 indicates that an attention indicator is implemente d on the adapter board. the pex 8524 serial eeprom register initial ization capability is used to change this value to 0, indicating an attention indicator is not present on an adapter board for which the pex 8524 provides the system interface. hwinit yes 1 14 power indicator present for the nt port link interface, this bit, value of 1 indicates that a power indicator is implemented on the adapter board. the pex 8524 serial eeprom register initial ization capability is used to change this value to 0, indicating that a power indicator is not present on an adapter board for which the pex 8524 provides the system interface. hwinit yes 1 17:15 reserved 000b 25:18 captured slot power limit value for the nt port link interface, the upper limit on power supplie d by the slot is determined by multiplying the value in this field by the value in the captured slot power limit scale field. ro yes 00h 27:26 captured slot power limit scale for the nt port link interface, the upper limit on power supplie d by the slot is determined by multiplying the value in this field by the value in the captured slot power limit value field. 00b = 1.0 01b = 0.1 10b = 0.01 11b = 0.001 ro yes 00b 31:28 reserved 0h
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 435 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-19. 70h device status and control bit(s) description type serial eeprom default device control 0 correctable error reporting enable 0 = disables 1 = enables nt port link interface to repor t correctable errors to the system host rw yes 0 1 non-fatal error reporting enable 0 = disables 1 = enables nt port link interface to re port non-fatal errors to the system host rw yes 0 2 fatal error reporting enable 0 = disables 1 = enables nt port link interface to report fatal errors to the system host rw yes 0 3 unsupported request reporting enable 0 = disables 1 = enables nt port link interface to report unsupported request errors as an error message with a programmed unc orrectable error severity rw yes 0 4 relaxed ordering enable cleared to 0, as required by the pci express base r1.0a . ro no 0 7:5 maximum payload size the nt port link interface power-on/rese t value is 000b, to support a maximum payload size of 128 bytes. software can ch ange this field to configure the nt port link interface to support other payload sizes; however, software cannot change this field to a value larger than that indicated by the device capabilities register maximum payload size supported field (offset 6ch [2:0]). for the virtual and link interfaces. (requester and completer domains must possess the same maximum payload size.) 000b = indicates that initially the pe x 8524 port is configured to support a maximum payload size of 128 bytes 001b = indicates that initially the pe x 8524 port is configured to support a maximum payload size of 256 bytes no other values are supported. note: software must halt all transactions through the nt port before changing this field. rw yes 000b
nt port link interface registers plx technology, inc. 436 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 8 extended tag field enable not supported cleared to 0. ro no 0 9 phantom functions enable not supported cleared to 0. ro no 0 10 auxiliary (aux) power pm enable not supported cleared to 0. ro no 0 11 no snoop enable not supported cleared to 0. ro no 0 14:12 maximum read request size not supported cleared to 000b. ro no 000b 15 reserved 0 device status 16 correctable error detected 1 = nt port link interface detected a correctable error set when the nt port link interface de tects a correctable error, regardless of the bit 0 ( correctable error reporting enable bit) state. rw1c yes 0 17 non-fatal error detected 1 = nt port link interface de tected a non-fatal error set when the nt port link interface de tects a non-fatal error, regardless of the bit 1 ( non-fatal error reporting enable bit) state. rw1c yes 0 18 fatal error detected 1 = nt port link interface detected a fatal error set when the nt port link interface detects a fatal error, regardless of the bit 2 ( fatal error reporting enable bit) state. rw1c yes 0 19 unsupported request detected 1 = nt port link interface detected an unsupported request set when the nt port link interface dete cts an unsupported request, regardless of the bit 3 ( unsupported reques t reporting enable bit) state. rw1c yes 0 20 auxiliary (aux) power detected not supported cleared to 0. ro no 0 21 transactions pending because pex 8524 nt ports are a bridging de vice, they do not track non-posted and completion for the corresponding non-posted transactions. therefore, the nt port link interface does not implement this bit. ro no 0 31:22 reserved 000h register 16-19. 70h device status and control (cont.) bit(s) description type serial eeprom default
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 437 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-20. 74h link capabilities bit(s) description type serial eeprom default 3:0 maximum link speed set to 0001b for 2.5 gbps. ro yes 0001b 9:4 maximum link width actual link width is set by signa l ball strapping options. the pex 8524 maximum link width is x8 = 00_1000b (station 0), or x16 = 01_0000b (station 1). ro no strap levels 11:10 active state power management (aspm) support indicates the level of aspm supported by the port. 01b = l0s link power state entry is supported all other values are reserved . ro yes 01b 14:12 l0s exit latency 101b = nt port link interface l0s ex it latency is between 1 and 2 s ro no 101b 17:15 l1 exit latency 101b = nt port link interface l1 ex it latency is between 16 and 32 s ro yes 101b 23:18 reserved 0-0h 31:24 port number the nt port number is selected by signal ball strapping options. refer to strap_nt_upstrm_portsel[3:0] for details. hwinit no set by strap levels
nt port link interface registers plx technology, inc. 438 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-21. 78h link status and control bit(s) description type serial eeprom default link control 1:0 active state power management (aspm) control 00b = disables l0s link interface entry for nt port 01b = enables l0s entry 10b and 11b are not allowed . rw yes 00b 2 reserved 0 3 read completion boundary (rcb) not supported cleared to 0. ro yes 0 4 link disable reserved for nt port link interface. ro no 0 5 retrain link reserved for nt port link interface. ro no 0 6 common clock configuration 0 = nt port link interface and the device at the other end of the pci express link are operating with an asynchronous reference clock 1 = nt port link interface and the device at the other end of the pci express link are operating with a distributed common reference clock rw yes 0 7 extended sync set to 1 causes the nt port link interface to transmit: 4,096 fts ordered-sets in the l0s state, followed by a single skip ordered-set prior to entering the l0 state, finally, transmission of 1,024 ts1 or dered-sets in the recovery state. rw yes 0 15:8 reserved 00h
february, 2007 pci express capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 439 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 link status 19:16 link speed nt port link interface set to 1h for 2.5 gbps. ro yes 1h 25:20 negotiated link width indicates the negotiated widt h of the pci express link. 00_0001b = x1 00_0010b = x2 00_0100b = x4 00_1000b = x8 01_0000b = x16 (station 1 only) all other values are not supported . the value in this field is undefined when the link is not up. ro yes 00_0001b 26 training error reserved for nt port link interface. ro no 0 27 link training reserved for nt port link interface. ro no 0 28 slot clock configuration upstream port or nt port link interface is set, but not both. 0 = indicates that the pex 8524 uses an independent clock 1 = indicates that the pex 8524 uses the same physical refere nce clock that the platform provides on the connector hwinit yes 0 31:29 reserved 000b register 16-21. 78h link status and control (cont.) bit(s) description type serial eeprom default
nt port link interface registers plx technology, inc. 440 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.8 nt port registers 16.8.1 nt port link interface interrupt request (irq) doorbell registers the pex 8524 nt port interrupt control (doorbell) registers are defined in section 15.8.1, ?nt port virtual interface irq do orbell registers.? table 16-6 defines the register map used by the nt port link interface. table 16-6. nt port link interface interrupt request (irq) doorbell register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved set virtual interface irq 90h reserved clear virtual interface irq 94h reserved set virtual interface irq mask 98h reserved clear virtual interface irq mask 9ch reserved set link interface irq a0h reserved clear link interface irq a4h reserved set link interface irq mask a8h reserved clear link interface irq mask ach
february, 2007 nt port scratchpad (mailbox) registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 441 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.8.2 nt port scratchpad (mailbox) registers this section details the pex 8524 nt port scratchpad (mailbox) registers. the register map is defined in table 16-7 . table 16-7. pex 8524 nt port scratchpad (mailbox) register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 nt port scratchpad_0 b0h nt port scratchpad_1 b4h nt port scratchpad_2 b8h nt port scratchpad_3 bch nt port scratchpad_4 c0h nt port scratchpad_5 c4h nt port scratchpad_6 c8h nt port scratchpad_7 cch register 16-22. b0h nt port scratchpad_0 bit(s) description type serial eeprom default 31:0 scratchpad_0 32-bit scratchpa d_0 register. rw yes 0-0h register 16-23. b4h nt port scratchpad_1 bit(s) description type serial eeprom default 31:0 scratchpad_1 32-bit scratc hpad_1 register. rw yes 0-0h register 16-24. b8h nt port scratchpad_2 bit(s) description type serial eeprom default 31:0 scratchpad_2 32-bit scratchpad_2 register. rw yes 0-0h register 16-25. bch nt port scratchpad_3 bit(s) description type serial eeprom default 31:0 scratchpad_3 32-bit scratchpad_3 register. rw yes 0-0h
nt port link interface registers plx technology, inc. 442 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-26. c0h nt port scratchpad_4 bit(s) description type serial eeprom default 31:0 scratchpad_4 32-bit scratchpad_4 register. rw yes 0-0h register 16-27. c4h nt port scratchpad_5 bit(s) description type serial eeprom default 31:0 scratchpad_5 32-bit scratchpa d_5 register. rw yes 0-0h register 16-28. c8h nt port scratchpad_6 bit(s) description type serial eeprom default 31:0 scratchpad_6 32-bit scratc hpad_6 register. rw yes 0-0h register 16-29. cch nt port scratchpad_7 bit(s) description type serial eeprom default 31:0 scratchpad_7 32-bit scratchpad_7 register. rw yes 0-0h
february, 2007 nt port link interface bar setup registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 443 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.8.3 nt port link inte rface bar setup registers this section details the nt port link interface bar setup registers. the register map is defined in table 16-8 . table 16-8. pex 8524 nt port link interface bar setup register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved d0h ? e0h nt port link interface bar0/bar1 setup e4h nt port link interface bar2/3 setup e8h nt port link interface bar3 setup ech nt port link interface bar4/5 setup f0h nt port link interface bar5 setup f4h register 16-30. e4h nt port link interface bar0/bar1 setup bit(s) description type serial eeprom default 1:0 bar0 type 00b = 32-bit memory bar0 11b = link interface bar0 is a 32-bit memory bar and link interface bar1 is an i/o bar all other codes disable bar1 implementation. rw yes 11b 31:2 reserved 0-0h
nt port link interface registers plx technology, inc. 444 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-31. e8h nt port link interface bar2/3 setup bit(s) description type serial eeprom default 0 type ro no 0 2:1 bar2 type 00b = bar2 is implemented as a 32-bit bar 10b = bar2/3 is implemented as a 64-bit bar note: it is illegal to program 10b and clear the nt port link interface bar3 setup register bar3 enable bit (offset ech [31]). rw yes 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable rw yes 0 11:4 reserved 00h 30:12 bar2 size specifies the address range size requested by bar2. 0 = corresponding bits in bar2 are read-only bits that always return 0, and writes are ignored 1 = corresponding bits in bar2 are rw bits rw yes 0000_0h 31 bar2 enable 0 = bar2 is disabled (bits [2:1] = 00b), all bits in bar2 read 0 1 = bar2 is enabled, size and type specified in this register rw yes 0 register 16-32. ech nt port link interface bar3 setup bit(s) description type serial eeprom default 30:0 bar3 size specifies the address ra nge size requested by bar2/3 in 64-bit mode when the nt port link interface bar2/3 setup register bar2 type field (offset e8h [2:1]) is set to 10b. 0 = read-only bits that always return 0, writes are ignored 1 = corresponding bits are rw bits rw yes 0-0h reserved when the nt port link interface bar2/3 setup register bar2 type field (offset e8h[2:1]) is cleared to 00b. 0 31 bar3 enable 0 = bar3 is disabled 1 = bar2/3 is enabled when the nt port link interface bar2/3 setup register bar2 type field (offset e8h[2:1]) is set to 10b note: it is illegal to program the nt port link interface bar2/3 setup register bar2 type field (offset e8h[2:1]) to 10b and clear this bit. rw yes 0 reserved when the nt port link interface bar2/3 setup register bar2 type field (offset e8h[2:1]) is cleared to 00b. 0
february, 2007 nt port link interface bar setup registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 445 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-33. f0h nt port link interface bar4/5 setup bit(s) description type serial eeprom default 0 type ro no 0 2:1 bar4 type 00b = bar4 is implemented as a 32-bit bar 10b = bar4/5 is implemented as a 64-bit memory bar note: it is illegal to program 10b and clear the nt port link interface bar5 setup register bar5 enable bit (offset f4h [31]). rw yes 00b 3 prefetchable 0 = non-prefetchable 1 = prefetchable rw yes 0 11:4 reserved 00h 30:12 bar4 size specifies the address ra nge size requested by bar4 . 0 = corresponding bits in bar4 are read-only bits that always return 0, and writes are ignored 1 = corresponding bits in bar4 are rw bits rw yes 0000_0h 31 bar4 enable when bits [2:1] = 00b, enables bar4 ; otherwise, belongs to the bar4 size [30:12] field. 0 = bar4 is disabled, all bits in bar4 read 0 1 = bar4 is enabled, size and type specified in this register rw yes 0 register 16-34. f4h nt port link interface bar5 setup bit(s) description type serial eeprom default 30:0 bar5 size together with the nt port link interface bar4/5 setup register bar4 size field (offset f0h [31:12]), specifies the addre ss range size requested by bar4/5 in 64-bit mode when the nt port link interface bar4/5 setup register bar4 type field (offset f0h[2:1]) is set to 10b. 0 = corresponding bits in bar5 are read-only bits th at always return 0, and writes are ignored 1 = corresponding bits in bar5 are rw bits rw yes 0-0h reserved when the nt port link interface bar4/5 setup register bar4 type field (offset f0h[2:1]) is cleared to 00b. 0-0h 31 bar5 enable 0 = bar5 is disabled 1 = bar4/5 is enabled when the nt port link interface bar4/5 setup register bar4 type field (offset f0h[2:1]) is set to 10b note: it is illegal to program the nt port link interface bar4/5 setup register bar4 type field (offset f0h[2:1]) to 10b and clear this bit. rw yes 0 reserved when the nt port link interface bar4/5 setup register bar4 type field (offset f0h[2:1]) is cleared to 00b. 0
nt port link interface registers plx technology, inc. 446 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.8.4 nt port cursor mechanism control registers this section details the nt port cursor mechanism c ontrol registers. the register map for the virtual and link interfaces is defined in table 16-9 . the cursor mechanism registers at offsets f8h/ fch provide a means for accessing pci express extended configuration space registers (100h thr ough fffh) within the nt port virtual and link interfaces, when only standard pci configuration tr ansactions (that do not support extended register number), and/or i/o request tran sactions (using the nt port bar1 address, if enab led) are available. the cursor mechanism can generally access only those registers that are defined by the pci express base r1.0a , and not the device-specific registers. table 16-9. nt port cursor mechanism control register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 configuration address window reserved f8h configuration data window fch register 16-35. f8h configuration address window bit(s) description type serial eeprom default 15:0 reserved 0000h 25:16 offset register offset rw yes 000h 30:26 reserved 0h 31 interface select 0 = access to nt port link interface type 0 configuration space register 1 = access to nt port virtual interfac e type 0 configuration space register rw yes 0 register 16-36. fch configuration data window bit(s) description type serial eeprom default 31:0 data window software selects a register by writ ing into the nt port link interface configuration address window, then reads or writes to that register using this register. rw yes 0-0h
february, 2007 device serial numb er extended capability registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 447 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.9 device serial number extended capability registers the nt port link interface device serial number ex tended capability registers are the same as the pex 8524 transparent port registers defined in section 11.10, ?device serial number extended capability registers.? the register map is defined in table 16-10 and applies to the virtual and link interfaces. 16.10 power budgeting extended capability registers the nt port link interface power budgeting extended capability registers are the same as the pex 8524 transparent port registers defined in section 11.11, ?power budgeting extended capability registers.? the register map is defined in table 16-11 and applies to the vi rtual and link interfaces. table 16-10. pex 8524 device serial number extended capability register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next capability offset ( fb4h ) capability ve r s i o n ( 1h ) extended capability id ( 0003h ) 100h serial number (lower dw) 104h serial number (higher dw) 108h table 16-11. pex 8524 power budgeting extended capability register map (all ports) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next capability offset ( 148h ) capability ve r s i o n ( 1h ) extended capability id ( 0004h ) 138h reserved data select 13ch power budgeting data 140h reserved power budget capability 144h
nt port link interface registers plx technology, inc. 448 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.11 virtual channel extended capability registers the virtual channel capability registers defined in section 11.12, ?virtual channel extended capability registers,? are also applicable to the nt port link interface. table 16-12 defines the register map. the port vc capability 1 , vc0 resource control , and vc1 resource control (offsets 14ch , 15ch , and 16ch , respectively) register va lues are shadowed in the nt link interface vc capability 1 , nt link interface vc0 resource control , and nt link interface vc1 resource control shadow registers (offsets d64h , d5ch , and d60h , respectively). note: these registers are not automatically shadowed when programmed by serial eeprom; therefore, if the serial eeprom programs these registers to non-default values, software must write the values to the registers (such as by re ading the register and writing back the value), to cause the corresponding shadow registers in the nt port virtual interface to update. table 16-12. link interface virtual channel extended capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next capability offset ( 000h ) capability ve r s i o n ( 1h ) extended capability id ( 0002h ) 148h port vc capability 1 14ch port vc capability 2 150h port vc status port vc control 154h vc0 resource capability 158h vc0 resource control 15ch vc0 resource status reserved 160h vc1 resource capability 164h vc1 resource control 168h vc1 resource status reserved 16ch reserved 170h ? 1b4h virtual channel arbitration table 1b8h ? 1c4h
february, 2007 plx-specific registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 449 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.12 plx-specific registers the pex 8524 nt mode link interf ace plx-specific registers are defined in section 11.13, ?plx- specific registers,? except as defined in table 16-13 through table 16-16 and/or their respective register tables. the entire register map is defined in table 16-13 . note: this register group is accesse d using a memory-mapped cycle. it is recommended that these register values not be changed. table 16-13. nt port link interface plx-specific register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 error checking and debug registers 1c8h ? 1fch physical layer registers 200h ? 2c4h cam routing registers 2c8h ? 344h nt port link interface ingress control register 660h ? 668h i/o cam base and limit upper 16 bits registers 680h ? 6ach base address registers (bars) 6c0h ? 73ch shadow virtual channel (v c) capability registers 740h ? 9ech ingress credit handler (inch) registers 9f0h ? b7ch reserved b80h ? bfch internal credit handler (itch ) vc&t threshold registers c00h ? c08h
nt port link interface registers plx technology, inc. 450 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.12.1 error checking and debug registers the nt mode link interface error checkin g and debug registers are defined in section 11.13.1, ?error checking and debug registers,? except as defined in table 16-14 (offsets 1d4h through 1d8h are reserved ) and the register tables that follow. table 16-14. plx-specific error checking and debug register map (ports a ) a. some registers are port-specifi c, some are station-specific , and some are device-specific. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved 1c8h error handler 32-bit error status (factory test only) 1cch error handler 32-bit error mask (factory test only) 1d0h reserved 1d4h ? 1d8h debug control 1dch reserved 1e0h egress nt port link interface control and status 1e4h reserved 1e8h ? 1ech silicon revision aa ? reserved silicon revi sions bb/bc ? plx-specific relaxed ordering enable 1f0h reserved 1f4h reserved ack transmission latency limit 1f8h reserved 1fch
february, 2007 error checking and debug registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 451 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 note: all errors in register offset 1cch generate msi/intx interrupts, when enabled. note: error logging is enabled in register offset 1d0h, by default. register 16-37. 1cch error handler 32-bit error status (factory test only) bit(s) description type serial eeprom default 0 error handler completion fifo overflow status 0 = no overflow detected 1 = completion fifo overflow detected when 4-deep completion fifo for ingress, or 2-deep completi on fifo for egress, overflows rw1cs yes 0 10:1 reserved no 0h 11 credit update timeout status no useful credit update to make forward progress for 512 ms or 1s (disabled by default). 0 = no credit update timeout detected 1 = credit update timeout completed rw1cs yes 0 12 inch underrun error ingress credit underrun. 0 = no error detected 1 = credit underrun error detected rw1cs yes 0 31:13 reserved no 0h register 16-38. 1d0h error handler 32-bit error mask (factory test only) bit(s) description type serial eeprom default 0 error handler completion fifo overflow status masked 0 = no effect on reporting activity 1 = error handler completion fifo overflow status bit is masked/disabled rws yes 1 10:1 reserved no 0h 11 credit update timeout status masked 0 = no effect on reporting activity 1 = credit update timeout status bit is masked/disabled rws yes 1 12 inch underrun error masked 0 = no effect on reporting activity 1 = inch underrun error bit is masked/disabled rws yes 1 31:13 reserved no 0h
nt port link interface registers plx technology, inc. 452 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-39. 1e4h egress nt port link interface control and status bit(s) description type serial eeprom default 0 egress credit update timer enable 0 = disables egress credit update timer 1 = enables egress credit update timer rw yes 0 1 egress credit timeout value 0 = minimum 512 ms (maximum 768 ms) 1 = minimum 1,024 ms (maximum 1,280 ms) rw yes 0 2 egress debug factory test only rw yes 0 15:3 reserved 0-0h 19:16 vc&t encountered timeout 0h = vc0 posted 1h = vc0 non-posted 2h = vc0 completion 3h = vc1 posted 4h = vc1 non-posted 5h = vc1 completion ro yes 0h 31:20 reserved 000h register 16-40. 1f8h ack transmission latency limit bit(s) description type serial eeprom default 7:0 ack transmission latency limit the value of this register remains 00h. rw yes 00h 15:8 hpc test bits factory test only. testing bits ? must be 00h. rw yes 00h 31:16 reserved 0000h
february, 2007 nt port link interface physical layer registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 453 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.12.2 nt port link interfa ce physical layer registers the nt port link interface physical layer registers are defined in section 11.13.2, ?physical layer registers,? except as defined in table 16-15 and the register table that follows. table 16-15. plx-specific nt port link interface physical layer register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 reserved 200h ? 20ch phy user test pattern 0 210h phy user test pattern 4 214h phy user test pattern 8 218h phy user test pattern 12 21ch physical layer status ph ysical layer command 220h port configuration 224h physical layer test 228h physical layer 22ch physical layer port command 230h skip ordered-set interval 234h quad 0 serdes diagnostic data 238h quad 1 serdes diagnostic data 23ch quad 2 serdes diagnostic data 240h quad 3 serdes diagnostic data 244h serdes nominal drive current select 248h serdes drive current level select 1 24ch serdes drive current level select 2 250h serdes drive equalization level select 1 254h serdes drive equalization level select 2 258h reserved 25ch ? 2c4h
nt port link interface registers plx technology, inc. 454 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-41. 220h physical layer command and status (only ports 0, 8, and nt port link interface) bit(s) description type serial eeprom default physical layer command 0 port enumerator enable 0 = enumerate not enabled 1 = enumerate enabled hwinit no 0 1 tdm enable 0 = tdm not enabled 1 = tdm enabled hwinit no 0 2 reserved 0 3 upstream port as conf iguration master enable 0 = upstream port cross-link not supported 1 = upstream port cross-link supported rw no 0 4 downstream port as configuration slave enable 0 = downstream port cross-link not supported 1 = downstream port cross-link supported rw no 0 5 lane reversal disable 0 = lane reversal supported 1 = lane reversal not supported rw no 0 6 reserved 0 7 fc-init triplet enable flow control initialization. 0 = init fl1 triplet can be interrupted by skip ordered-se t/idle data symbol 1 = init fl1 triplet not interrupted rw no 1 15:8 n_fts value n_fts value to transmit in training sets. rw no 40h physical layer status 19:16 reserved 0h 22:20 number of ports enumerated number of ports in current configuration. hwinit no 00b 23 reserved 0 24 port 0 or 8 deskew buffer error status 1 = deskew buffer overflow or underflow rw1c no 0 25 port 1 or 9 deskew buffer error status 1 = deskew buffer overflow or underflow rw1c no 0 26 port 10 deskew buffer error status 1 = deskew buffer overflow or underflow reserved for station 0. rw1c no 0 27 port 11 deskew buffer error status 1 = deskew buffer overflow or underflow reserved for station 0. rw1c no 0 31:28 reserved 0h
february, 2007 nt port link interface ingress control register expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 455 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.12.3 nt port link interf ace ingress control register the nt port link interface ingress c ontrol register is defined in section 11.13.4, ?ingress control registers,? with the addition of the ingress control register no snoop disable bit (bit 24) and bit 25 is changed to factory test only . the register map is defined in table 16-16 . table 16-16. plx-specific nt port link interface ingress control register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 ingress control 660h reserved 664h ? 668h
nt port link interface registers plx technology, inc. 456 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-42. 660h ingress control (only ports 0 and 8) bit(s) description type serial eeprom default 0 enable csr access by downstream devices silicon revision aa enables acceptance of configuration reques ts from a requester that is downstream from a transparent port, targeting any do wnstream transparent port?s type 1 header registers or nt port virtual interface type 0 header registers ( such as for peer configuration access). 0 = configuration requests fro m a downstream device are not supported ; the downstream port flags an uncorrectable error, and, returns a completion with unsupported request (ur) specified in the completion status field, to the downstream requester. only this mode is pci express base r1.0a -compliant. 1 = the following types of configurat ion requests from down stream requesters are allowed: type 0 requests targeting the type 1 head er registers in that downstream port type 1 requests targeting the type 1 he ader registers in other downstream transparent ports, and type 1 requests targeting the type 0 header registers in the nt port virtual interface the upstream port registers are not accessible from the downstream port. silicon revisions bb/bc enables acceptance of both configurati on and memory requests from a requester that is downstream from a transparent port, targeting any pex 8524 registers. 0 = configuration requests fro m a downstream device are not supported ; the downstream port flags an uncorrectab le error, and, returns a completion with unsupported request (ur) specified in the completion status field, to the downstream requester. only this mode is pci express base r1.0a -compliant. 1 = configuration and memory requests from downstream re questers, targeting any pex 8524 registers in any port, are allowed. notes: this bit can be initially set only th rough the upstream port, the nt port link interface, or serial eeprom, to enable register access through downstream transparent ports; a requester downstream fr om a transparent port cannot set the bit to grant itself (or peers) access to pex 8524 registers. configuration requests can access those registers that are defined by pci-sig specifications, and generally cannot access device-specific regi sters other than the nt port cursor mechanism registers. memory requests can access all pex 8524 registers. configuration requests can access the nt port cursor mechanism registers (offsets f8h / fch ) to provide indirect access to nt port offsets above 100h, for conventional pci requesters such as a pci master connected to a pci express-to- pci bridge, that cannot generate conf iguration requests c ontaining an extended register number. the nt port virtual in terface cursor mechanism (but not the nt port link interface cursor mechanism) can access device-speci fic registers that exist in the nt port; if port 0 is the nt port, the nt port virtual interface cursor mechanism can access the device-specific regi sters (which exist only in port 0) and the station 0 registers (which exist in po rt 0 for all enabled ports in station 0). rw yes 0 1 disable unsupported re quest response for reserved configuration registers rw yes 0 23:2 factory test o nly rw yes 0-0h
february, 2007 nt port link interface ingress control register expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 457 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 24 no snoop disable silicon revision aa not supported silicon revisions bb/bc forces the packet header no snoop attribute bit to 0, for all packets transferred between the nt link and vi rtual interfaces (across the nt boundary, in both directions). can be used to handle cach e coherency-related issues in a system. 0 = disables no snoop disable feature 1 = enables no snoop disable feature rw yes 0 26:25 factory test only rw yes 00b 27 reserved silicon revision aa 0 bios enumeration fix disable silicon revisions bb/bc for nt failover in silicon revisi ons bb/bc, this bit must be set. rw yes 0 31:28 factory test only rw yes 0h register 16-42. 660h ingress control (only ports 0 and 8) (cont.) bit(s) description type serial eeprom default
nt port link interface registers plx technology, inc. 458 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.13 pex 8524 non-transparent bridging-specific registers table 16-17 defines the register map of the registers implemented to support the pex 8524 non-transparent bridging function. the nt station contains the main copy of these registers, and the transparent station contains the shadow copy of these registers. thes e registers are accessed by memory-mapped access to port 0, port 8, or nt port. table 16-17. nt port link interface nt bridging-specific register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 nt port link interface memory address translation and limit bar registers c3ch ? c58h reserved c5ch ? db0h nt port link interface receiv e lookup table entry registers db4h ? df0h reserved df4h ? fb0h
february, 2007 nt port link interface memory address translation and limit bar registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 459 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.13.1 nt port link interfa ce memory address translation and limit bar registers the nt station contains the main copy of these registers, and the transparent stati on contains the shadow copy of these registers. program only the main copy. the shadow register is automatically updated. the reverse is not true. the register map is defined in table 16-18 . table 16-18. nt port link interface memory address translation and limit bar register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 memory bar2/3 address translation[31:0] c3ch memory bar2/3 address translation[63:32] c40h memory bar4/5 address translation[31:0] c44h memory bar4/5 address translation[63:32] c48h memory bar2/3 limit[31:0] c4ch memory bar2/3 limit[63:32] c50h memory bar4/5 limit[31:0] c54h memory bar4/5 limit[63:32] c58h register 16-43. c3ch memory bar2/3 address translation[31:0] bit(s) description type serial eeprom default 11:0 reserved 0-0h 31:12 bar2/3 base translation address[31:12] nt port link interface base tr anslation address when the nt port link interface bar2/3 setup register bar2 enable bit (offset e8h [31]) is set to 1. rw yes 0-0h register 16-44. c40h memory bar2/3 address translation[63:32] bit(s) description type serial eeprom default 31:0 bar2/3 base translation address[63:32] nt port link interface base translati on upper address when bar2/3 is enabled as a 64-bit bar [ nt port link interface bar2/3 setup register bar2 type field (offset e8h [2:1]) is set to 10b]. rw yes 0-0h read-only when the nt port link interface bar2/3 setup register bar2 type field (offset e8h[2:1]) is cleared to 00b. ro no 0-0h
nt port link interface registers plx technology, inc. 460 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-45. c44h memory bar4/5 address translation[31:0] bit(s) description type serial eeprom default 11:0 reserved 0-0h 31:12 bar4/5 base translation address[31:12] nt port link interface base translation address when the nt port link interface bar4/5 setup register bar4 enable bit (offset f0h [31]) is set to 1. rw yes 0-0h register 16-46. c48h memory bar4/5 address translation[63:32] bit(s) description type serial eeprom default 31:0 bar4/5 base translation address[63:32] nt port link interface base transla tion upper address bar 4/5 is enabled as a 64-bit bar [ nt port link interface bar4/5 setup register bar4 type field (offset f0h [2:1]) is set to 10b]. rw yes 0-0h read-only when the nt port link interface bar4/5 setup register bar4 type field (offset f0h[2:1]) is cleared to 00b. ro no 0-0h register 16-47. c4ch memory bar2/3 limit[31:0] bit(s) description type serial eeprom default 11:0 reserved 0-0h 31:12 bar2/3 limit[31:0] contains the address of the memory window lower limit defined in the nt port link interface bar2/3 setup register (offset e8h ). 1 mb granularity. when the limit is greater than the window size, the limit is ignored. rw yes 000h register 16-48. c50h memory bar2/3 limit[63:32] bit(s) description type serial eeprom default 31:0 bar2/3 limit[63:32] contains the address of the memory window upper limit defined in the nt port link interface bar3 setup register (offset ech ), when the following conditions exist: nt port link interface bar2/3 setup register bar2 type field (offset e8h [2:1]) is set to 10b, and nt port link interface bar3 setup register bar3 enable bit (offset ech [31]) is set to 1 when the limit is greater than the window size, the limit is ignored. rw yes 0-0h read-only when the nt port link interface bar2/3 setup register bar2 type field (offset e8h[2:1]) is cleared to 00b. ro no 0-0h
february, 2007 nt port link interface memory address translation and limit bar registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 461 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 register 16-49. c54h memory bar4/5 limit[31:0] bit(s) description type serial eeprom default 11:0 reserved 0-0h 31:12 bar4/5 limit[31:0] contains the address of the me mory window lower limit defined in the nt port link interface bar4/5 setup register (offset f0h ). 1 mb granularity. when the limit is greater than th e window size, the limit is ignored. rw yes 0-0h register 16-50. c58h memory bar4/5 limit[63:32] bit(s) description type serial eeprom default 31:0 bar4/5 limit[63:32] contains the address of the memory window upper limit defined in the nt port link interface bar4/5 setup register (offset f0h ), when the following conditions exist: nt port link interface bar4/5 setup register bar4 type field (offset f0h [2:1]) is set to 10b, and nt port link interface bar5 setup register bar5 enable bit (offset f4h [31]) is set to 1 when the limit is greater than the window size, the limit is ignored. rw yes 0-0h read-only when the nt port link interface bar4/5 setup register bar4 type field (offset f0h[2:1]) is cleared to 00b. ro no 0-0h
nt port link interface registers plx technology, inc. 462 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.13.2 nt port link interface recei ve lookup table entry registers this section describes the nt port link interface receive (requester id translation) lookup table (lut) entry registers. the nt port uses these regist ers for requester id translation when it forwards: tlp request from nt port link inte rface to the virtual interface, or completion tlp from nt port virt ual interface to the link interface the nt station contains the main copy of these registers, and the transparent station contains the shadow copies of these registers. program only the main copy. the shadow register is automatically updated. the reverse is not true. table 16-19 defines the register and address locations. th e register descriptions that follow the table define the bit definitions that apply to the registers. note: writes to nt port link interface receive lookup table entry registers (offsets db4h through df0h) are automatically copied to the same offsets in the nt port virtual interface. if these nt port link interface registers are programmed by serial eeprom, the same data values must be programmed into the same register offsets in the nt port virtual interface (that is, the values in serial eeprom dword addresses a4dh through a5ch must also be programmed into serial eeprom dword addresses b45h through b54h , respectively). additionally, software must copy the values to the same offsets in the non-nt station (port 0 or port 8). if the nt port is one of ports 8 through 11, software must read the value(s) in the nt port link interface and write the value(s) to the same offsets (db4h through df0h) in port 0; if the nt port is one of ports 0 through 3, software must read the value(s) in the nt port link interface and write the value(s) to the same offsets (db4h through df0h) in port 8.
february, 2007 nt port link interface receive lookup table entry registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 463 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 table 16-19. link interface receive lookup table entry_ n _ m register locations addr location lookup table entry_ n _ m addr location lookup table entry_ n _ m db4h 0_1 dd4h 16_17 db8h 2_3 dd8h 18_19 dbch 4_5 ddch 20_21 dc0h 6_7 de0h 22_23 dc4h 8_9 de4h 24_25 dc8h 10_11 de8h 26_27 dcch 12_13 dech 28_29 dd0h 14_15 df0h 30_31 register 16-51. db4h - df0h link interface receive lookup table entry_ n_m (where n_m = 0_1 through 30_31) bit(s) description type serial eeprom default 0 lut entry_ n enable 0 = disables 1 = enables rw yes 0 2:1 reserved 00b 7:3 requester id lut entry_ n device number rw yes 0000_0b 15:8 lut entry_ n bus number rw yes 00h 16 lut entry_ m enable 0 = disables 1 = enables rw yes 0 18:17 reserved 00b 23:19 lut entry_ m device number rw yes 0000_0b 31:24 lut entry_ m bus number rw yes 00h
nt port link interface registers plx technology, inc. 464 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 16.14 advanced error reporting capability registers the advanced error reporting capability register s for the nt port link interface are equivalent to those defined in section 11.14, ?advanced error reporting capability registers.? the registers are duplicated for the nt po rt link interface, and table 16-20 defines the register map. table 16-20. advanced error reporting capability register map 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 next capability offset ( 138h ) capability ve r s i o n ( 1h ) pci express extended capability id ( 0001h )fb4h uncorrectable error status fb8h uncorrectable error mask fbch uncorrectable error severity fc0h correctable error status fc4h correctable error mask fc8h advanced error capa bilities and control fcch header log_0 fd0h header log_1 fd4h header log_2 fd8h header log_3 fdch reserved fe0h ? ffch
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 465 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 17 test and debug 17.1 physical layer loop-back operation 17.1.1 overview physical layer loop-back functions are used to test serdes in the pex 8524 , connections between devices, serdes of external devices, and certain pex 8524 and external digital logic. the pex 8524 supports five types of loop-back operations: internal loop-back ? connects serdes serial tx output to serial rx input . the pseudo-random bit sequence (prbs) generator is used to create a pseudo-random data pattern that is transmitted and returned to the prbs checker. analog loop-back master ? the pex 8524 enters analog loop-back master mode when the physical layer port command register port x loop-back command bit (port 0 or 8, offset 230h [ 0 , 4 , 8 , and/or 12 ]) is set. this method depends on an external device or dumb connection ( such as a cable) to loop back the transmitted data to the pex 8524. the slave device must not include its elastic buff er in the loop-back data path because no skip ordered-sets are transmitted. use the prbs generator and ch ecker to create and check the data pattern. digital loop-back master ? the pex 8524 enters digital loop-back master mode when the physical layer port command register port x loop-back command bit (port 0 or 8, offset 230h[0, 4, 8, and/or 12]) is set. as with analog loop-back master mode, this method depends upon an external slave device to loop back the transmitted data. this method is best utilized with an external slave device that includes at least its elastic buffer in the loop-back data path. the pex 8524 provides programmable test pattern generators and checkers that insert the skip ordered-set at the proper intervals. analog loop-back slave ? the pex 8524 enters analog loop-back slave mode if an external device sends at least two consecutive ts1 ordered-sets that have the loopback bit exclusively set in the ts1 training control symbol, and the physical layer test register analog loop-back enable bit (port 0 or 8, offset 228h [4]) is set. the received data is looped back from the serdes 10-bit receive interface to the 10-bit transmit interface. all dig ital logic is excluded from the loop-back data path. digital loop-back slave ? the pex 8524 enters digital loop -back slave mode if an external device sends at least two consecutive ts1 ordered-sets that have the loopback bit exclusively set in the ts1 training control symbol, and the physical layer test register analog loop-back enable bit (port 0 or 8, offset 228h[4]) is cleared. in this mode, the data is looped back at an 8-bit level, which includes the pex 8524 elastic buffer, 8b/10b decoder, and 8b/10b encoder in the loop-back data path.
test and debug plx technology, inc. 466 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 17.1.1.1 loop-back test modes the pex 8524 supports all loop-back modes described in the pci express base r1.0a . to establish a pex 8524 port as a loop-back mast er, the serial eeprom is used to write 1 to the appropriate physical layer port command register port x loop-back command bit (port 0 or 8, offset 230h [ 0 , 4 , 8 , and/or 12 ]). this enables the selected port to set the loopback bit in the training control symbol of the ts1 ordered-set during the configuration.linkwidth.start state. after a port is established as a lo op-back master, the corresponding physical layer port command register port x ready as loop-back master status bit (port 0 or 8, offset 230h[ 3 , 7 , 11 , and/or 15 ]) is set. depending on the capability of the loop- back slave, the prbs generator or phy user test pattern x registers (port 0 or 8, offsets 210h through 21ch ) are used to create a bit stream that is checked by appropriate checking logic. when the pex 8524 is established as a loop-back slave, it can operate as an analog or digital (default) far-end device: analog loop-back mode is selected by setting the physical layer test register analog loop-back enable bit (port 0 or 8, offset 228h [4]) to 1. in analog slave loop-back mode, the received data is looped back from the 10-bi t received data, to the 10-bit transmit data. when digital loop-back mode is selected (power -on default), the data is looped back from the 8-bit decoded received data to the 8-bit transmit da ta path. this loop-back point allows the elastic buffer 8b/10b decoder and 8b/10b encoder to be included in the test data path. digital loop-back mode requires that the skip ordered-se ts be included in the data stream. 17.1.2 internal loop-back figure 17-1 illustrates the loop-back data path when in ternal loop-back mode is enabled. the only items in the data path are the serializer and de-s erializer. loop-back mode is used when the serdes built-in self-test (bist) is enabled. serdes bist is intended to overlap with the serial ee prom load operation. to achieve this overlap, the physical layer test register serdes bist enable bit (port 0 or 8, offset 228h [7]) is written early in the serial eeprom load operation. after the serdes bist enable bit is set, serdes is placed in loop-back mode and the prbs generator is started. the bist is run for 512 s; if an error is detected on a serdes, the quad x serdes diagnostic data registers (port 0 or 8, offsets 238h through 244h ) log the number of prbs errors generated for a group of serdes lanes. while the serdes bist is in progress, the prbs test data is present on the exte rnal txp and txn balls. the tx pad txn signals must have an ac-coupled, 50-ohm termination to ground. reloading of the serial eeprom register load has no effect on the serdes bist. figure 17-1. internal loop-back (analog near end) data path prbs gen prbs chk tx pad rx pad pex 8524
february, 2007 analog loop-back master expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 467 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 17.1.3 analog loop-back master analog loop-back mode is normally used for analog far-end testing; however, the mode can also be used to re-create the previously described bist by looping back the data with a cable. (refer to figure 17-2 .) looping back with a cable includes the internal b ond, external balls, any board trace, and connectors in the test data path. (refer to figure 17-3 .) figure 17-2. analog far-end loop-back figure 17-3. cable loop-back prbs gen prbs chk tx pad rx pad pci express loop-back slave device tx pad rx pad pex 8524 prbs gen prbs chk tx pad rx pad pex 8524
test and debug plx technology, inc. 468 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 to cause a pex 8524 port to request to become a loop-back master: 1. after the link is up, set the appropriate physical layer port command register port x loop-back command bit (port 0 or 8, offset 230h [ 0 , 4 , 8 , and/or 12 ]), to cause the port to transition from the l0 state to recovery, then to the loop-back state: ? if a cable is used for a loop -back, the port transitions from the configuration state to the loop-back state. connect this cable only after the upstream link is up and writes are possible. ? if the cable is connected before the upstr eam device is able to set the appropriate physical layer test register prbs external loop-back and prbs enable bits (port 0 or 8, offset 228h [ 23:20 and 19:16 ], respectively) associated with the serdes assigned to the port being tested, the link with the cable can reach th e l0 state and not go to the loop-back state. ? cable length is limited only by the pc i express drivers an d cable properties. 2. after the port is in the loop- back state, the corresponding physical layer port command register port x ready as loop-back master status bit (port 0 or 8, offset 230h [ 3 , 7 , 11 , and/or 15 ]) is set: ? at this time, the prbs engine can be enabled by setting the physical layer test register prbs enable bit (port 0 or 8, offset 228h[19:16]) associated with the serdes assigned to the port being tested. ? the returned prbs data is checked by th e prbs checker. errors are logged in the quad x serdes diagnostic data registers (port 0 or 8, offsets 238h through 244h ) that correspond to the serd es quad being tested. note: the prbs generator can be difficult to use beca use skip ordered-sets are not generated by the prbs generator, and consequently the pex 8524 can lose symbol lock unless the slave device inserts the skip ordered-sets. however, if the slave device is enabled to support digital loop-back, it inserts skip ordered-sets. if the phy user test pattern x registers (port 0 or 8, offsets 210h through 21ch ) are used (rather than prbs), skip ordered-sets are automatically generated.
february, 2007 digital loop-back master expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 469 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 17.1.4 digital loop-back master the only difference between the analog and digita l loop-back master modes is that the external device is assumed to possess certain digital logic in the loop-back data path. because this includes the elastic buffer, skip ordered-sets must be included in the test pattern. for the pex 8524, this precludes prbs engine use, because the prbs genera tor does not generate skip ordered-sets. the pex 8524 provides the programmable phy user test pattern x (port 0 or 8, offsets 210h through 21ch ) transmitter for digital far-end loop-back testing. to program the phy user test pattern x transmitter: 1. after loop-back master mode is established, write the test pattern values to the phy user test pattern x registers (port 0 or 8, offsets 210h through 21ch), in port 0 for the station 0 serdes and in port 8 for the station 1 serdes. to start tran smitting the test pattern on specific serdes quads, set the corresponding physical layer test register user test pattern enable bit(s) (port 0 or 8, offset 228h [ 31:28 ]): ? if the physical layer test register port/serdes test pattern enable select bit (port 0 or 8, offset 228h[5]) is also set, the test pattern is transmitted on all corresponding port lanes, regardless of width. ? if the port/serdes test pattern enable select bit is cleared, the test pattern is transmitted only on the corresponding serdes quad lanes. ? the phy user test pattern x registers can be written to change the test pattern during the test. 2. skip ordered-sets are inserted at the in terval determined by the value in the skip ordered-set interval register skip ordered-set interval field (port 0 or 8, offset 234h [ 11:0 ]) (default value is 1,180 symbol times) at the nearest data pattern boundary. the test pattern checker ignores skip ordered-sets returned by the loop-back slave, because the number of skip symbols received differ from the number transmitted. 3. all other data is compared to the data transmitted and errors are logged in the quad x serdes diagnostic data registers. figure 17-4. digital far-end loop-back utp tx utp chk tx pad rx pad pci express loop-back slave device tx pad rx pad ebuffer pex 8524
test and debug plx technology, inc. 470 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 the following example illustrates the necessary step s for running the digital loop-back master test, with port 1 as a x4 port on serdes[4:7]: 1. write 0f00_0000h to the physical layer test register (port 0, offset 228h ), to clear the quad x serdes diagnostic data register prbs error count field (port 0, offsets 238h through 244h [ 31:24 ]). 2. to generate a specific test pattern, write the 128-bit value into phy user test pattern x registers (port 0, offsets 210h through 21ch ). 3. write 0000_0010h to the physical layer port command register (port 0, offset 230h ), to enable digital loop-back master mode on port 1. 4. read the physical layer port command register (port 0, offset 230h), to confirm that port 1 is in digital loop-back master mode. the value should be 0000_0090h. 5. write 2000_0000h to the physical layer test register (port 0, offset 228h), to enable the test pattern on serdes[4:7]. 6. read the quad 1 serdes diagnostic data register prbs error count field (port 0, offset 23ch [ 31:24 ]), to check for errors on serdes[4:7]. if there are no errors, the field has a value of 00h. 7. exit digital loop-back mast er mode by clearing the physical layer port command register (port 0, offset 230h), and then the physical layer test register (port 0, offset 228h).
february, 2007 analog loop-back slave expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 471 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 17.1.5 analog loop-back slave the pex 8524 becomes an analog loop-back slave if the following conditions exist (refer to figure 17-5 ): at least two consecutive ts1 ordered-sets have the loopback bit exclusively set in the ts1 training control symbol, and physical layer test register analog loop-back enable bit (port 0 or 8, offset 228h [4]) is set while an analog loop-back slave, th e pex 8524 includes only the seri alizer and de-serializer in the loop-back data path. the loop-back master must pr ovide the test pattern an d data pattern checking. it is unnecessary for the loop-back master to in clude skip ordered-sets in the data pattern. figure 17-5. analog loop-back slave mode data gen data chk tx pad rx pad pci express loop-back master device tx pad rx pad pex 8524
test and debug plx technology, inc. 472 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 17.1.6 digital loop-back slave the pex 8524 becomes a digital loop-back slave if the following conditions exist (refer to figure 17-6 ): at least two consecutive ts1 ordered-sets have the loopback bit exclusively set in the ts1 training control symbol, and physical layer test register analog loop-back enable bit (port 0 or 8, offset 228h [4]) is cleared when a pex 8524 port is a digital loop-back slave, it includes the elastic buffer and 8b/10b decoder and encoder in the loop-back data path. the loop-b ack master must provide the test pattern and data pattern checker. additionally, the master must transmit valid 8b/10b symbols, for the loop-back data from the slave to be valid. the loop-back master must also tr ansmit skip ordered-sets with th e data pattern. the data checker must make provisions for the pex 8524 to return more or fewer skip symbols than it received. figure 17-6. digital loop-back slave mode data tx data chk tx pad rx pad pci express loop-back master device tx pad rx pad ebuffer 8b/10b dec 8b/10b enc pex 8524
february, 2007 using the diagnostic registers expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 473 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 17.1.7 using the diagnostic registers there are two diagnostic registers fo r station 0, and four diagnostic registers for station 1, one for each serdes quad. registers at offsets 240h and 244h are reserved for station 0. the quad x serdes diagnostic data register (port 0 or 8, offsets 238h through 244h ) contents reflect the performance of the serdes selected by the physical layer test register prbs diagnostic data select serdes select field (port 0 or 8, offset 228h [ 9:8 ]). for example , if the serdes select field is set to 10b, the information in the quad 0 serdes diagnostic data register (port 0 or 8, offset 238h ) is for serdes 2 in quad 0 for port 0, and serdes 18 in quad 0 for port 8. table 17-1 further illustrates this example. the prbs diagnostic data select serdes select field must be set up before the test is started. table 17-1. serdes register contents when prbs diagnostic data select serdes select field = 10b port 0 or 8, register offset register port 0 port 8 238h quad 0 serdes diagnostic data serdes 2 serdes 18 23ch quad 1 serdes diagnostic data serdes 6 serdes 22 240h quad 2 serdes diagnostic data ?serdes 26 244h quad 3 serdes diagnostic data ?serdes 30
test and debug plx technology, inc. 474 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 17.2 pseudo-random and bit-pattern generation each serdes quad has an associated prbs genera tor and checker. the prbs generator is based on a 7-bit linear feedback sh ift register (lfsr), which can generate up to (2 7 ? 1) unique patterns. the prbs logic is assigned to a serdes in the quad by manipulating the physical layer test register prbs diagnostic data select serdes select field (port 0 or 8, offset 228h [ 9:8 ]) in each station. the prbs bit stream is used for internal serdes or analog far-end loop-back testing. the pex 8524 also provides a method of creating a repeating programmable bit pattern. each of the four 32-bit phy user test pattern x registers (port 0 or 8, offsets 210h through 21ch ) are loaded with a 32-bit data pattern. after a port is es tablished as a loop-back master, set the physical layer test register user test pattern enable bit(s) (port 0 or 8, offset 228h[ 31:28 ]) to 1, for the serdes quad(s) associated with that port. the pex 8524 proceeds to tr ansmit the data pattern on all lanes, starting with byte 0 of the phy user test pattern 0 register, and continuing, in sequence, through byte 3 of the phy user test pattern 12 register. skip ordered-sets are inserted at the proper intervals, which makes this method appropriate for digital far-end loop-back testing. the received patt ern is compared to the transmitted pattern. any errors are logged and retrieve d by reading the quad x serdes diagnostic data registers (port 0 or 8, offsets 238h through 244h ). to produce a pseudo-clock bitstream in analog loop-back mode, set the registers as follows: 1. in the slave device, enable an alog loop-back by setting the physical layer test register analog loop-back enable bit (port 0 or 8, offset 228h[4] in plx switches). 2. in the pex 8524 loop-back master device: a. write the value 4a4a_4a4ah into each of the phy user test pattern x registers (port 0 or 8, offsets 210h through 21ch). b. set the physical layer port command register port x loop-back command bit (port 0 or 8, offset 230h [ 0 , 4 , 8 , and/or 12 ]) for the specific port. to verify whether loop-back is successful, read the corresponding physical layer port command register port x ready as loop-back master status bit (port 0 or 8, offset 230h[ 3 , 7 , 11 , and/or 15 ]) in the same nibble that was set in step a . the nibble value will be 9h if loop-back is successful. c. set the physical layer test register user test pattern enable bit(s) (port 0 or 8, offset 228h[ 31:28 ]) for the particular serdes quad(s ) used by the port selected step b , for the the physical layer port command register (port 0 or 8, offset 230h). d. the interval between skip ordered-sets can be programmed in the skip ordered-set interval register skip ordered-set interval field (port 0 or 8, offset 234h [ 11:0 ]). note: a high value for offset 234h[11:0] (such as fffh) can cause the link to fail. 3. exit analog loop-back mode by clearing the physical layer port command register (port 0 or 8, offset 230h), and then the physical layer test register (port 0 or 8, offset 228h). the link will re-establish itself.
february, 2007 jtag interface expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 475 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 17.3 jtag interface the pex 8524 provides a jtag bounda ry scan interface, which is util ized to debug board connectivity for each ball. 17.3.1 ieee 1149.1 and 1149.6 test access port the ieee 1149.1 test access port (tap), commonly called the jtag (joint test action group) debug port, is an architectural standard described in the ieee standard 1149.1-1990 . the ieee standard 1149.6-2003 defines extensions to 1149.1 to support pc i express serdes testing. these standards describe methods for accessing internal chip f acilities, using a four- or five-signal interface. the jtag debug port, originally designed to support scan-based board testing, is enhanced to support the attachment of debug tools. th e enhancements, which comply with ieee standard 1149.1-1994 specifications for vendor-specific extensions , are compatible with sta ndard jtag hardware for boundary-scan system testing. jtag signals ? jtag debug port implements the four required jtag signals ? jtag_tck , jtag_tdi , jtag_tdo , and jtag_tms ? and optional jtag_trst# signal clock requirements ? jtag_tck signal frequency ranges from dc to 10 mhz jtag reset requirements ? section 17.3.4, ?jtag reset input signal jtag_trst#?
test and debug plx technology, inc. 476 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 17.3.2 jtag instructions the jtag debug port provides the ieee standard 1149.1-1990 extest, sample/preload, bypass, and idcode instructions. ieee standard 1149.6-2003 extest_pulse and extest_train instructions are also supported. private instructions are for plx use only. invalid instructions behave as bypass instructions. table 17-2 lists the jtag instructions, along with their input codes. table 17-2. jtag instructions instruction input code comments extest 00000b ieee standard 1149.1-1990 idcode 00001b sample/preload 00010b bypass 11111b extest_pulse 00011b ieee standard 1149.6-2003 extest_train 00100b private a a. warning: non-plx use of private instructions can cause a component to operate in a hazardous manner. 00101b 00110b 00111b 01000b 01001b 01010b 01011b 01100b 01101b 01110b 01111b
february, 2007 jtag instructions expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 477 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 table 17-3 defines the jtag idcode values returned by the pex 8524v for silicon revisions aa, bb, and bc, and pex 8524 for silicon revisions bb and bc. table 17-3. jtag idcode values device unit of measure version part number plx manufacturer identity least significant bit pex 8524vaa bits 0001b 0010_0001_0101_0100b 001_1100_1101b 1 hex 1h 2154h 1cdh 1h decimal 1 8532 461 1 pex 8524vbb bits 0100b 0010_0001_0101_0100b 001_1100_1101b 1 hex 4h 2154h 1cdh 1h decimal 4 8532 461 1 pex 8524vbc bits 1000b 0010_0001_0101_0100b 001_1100_1101b 1 hex 8h 2154h 1cdh 1h decimal 8 8532 461 1 pex 8524bb bits 0100b 0010_0001_0100_1100b 001_1100_1101b 1 hex 4h 214ch 1cdh 1h decimal 4 8524 461 1 pex 8524bc bits 1000b 0010_0001_0100_1100b 001_1100_1101b 1 hex 8h 214ch 1cdh 1h decimal 8 8524 461 1
test and debug plx technology, inc. 478 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 17.3.3 jtag boundary scan scan description language (bsdl), ieee 1149.1-1994 , is a supplement to ieee standard 1149.1-1990 and ieee standard 1149.1a-1 993, ieee standard test access port and boundary-scan architecture . bsdl, a subset of the ieee 1076-1993 st andard vhsic hardware de scription language (vhdl) , allows a rigorous description of testability features in components which comply with the standard. this standard is used by automated test pattern generati on tools for package interc onnect tests and electronic design automation (eda) tools for synthesized test logic and verification. bsdl supports robust extensions that can be used for internal test generation and to write software for hardware debug and diagnostics. the primary components of bsdl include the logical port description, physical ball map, instruction set, and boundary register description. the logical port description assigns symbolic names to the chip balls. each ball includes a logical type of in , out , in out , buffer , or linkage that defines the logical direction of signal flow. the physical ball map correlates the chip logical ports to the physical balls of a specific package. a bsdl description can include several physical ball maps, and maps are provided with a unique name. instruction set statements describe the bit patterns that must be shifted into the instruction register to place the chip in the various test modes defined by th e standard. instruction set statements also support descriptions of instructions that are unique to the chip. the boundary register description lists each cell or shift stage of the bou ndary register. each cell contains a unique number, the cell numbered 0 is the closest to the test data out ( jtag_tdo ) ball and the cell with the highest number is closest to the test data in ( jtag_tdi ) ball. each cell contains additional information, including: cell type logical port associated with the cell logical function of the cell safe value control cell number disable value result value 17.3.4 jtag reset input signal jtag_trst# the jtag_trst# input ball is the asynchronous jtag logic reset. when jtag_trst# is set low, it causes the pex 8524?s jtag tap controller to initialize. in addition, when the jtag tap controller is initialized, it selects the pex 8524 standard logic path (core-to-i/o). it is recommended to take the following into consideration when implementing the asynchronous jtag logic reset on a board: if jtag functionality is required, consider one of the following: ? jtag_trst# input signal to use a low-to-high transition once during pex 8524 boot-up, along with the system pex_perst# signal ? hold the jtag_tms ball high while clocking the jtag_tck ball five times if jtag functionality is not required, the jt ag_trst# signal must be directly connected to vss to hold the jtag tap controller inactive if the pex 8524?s jtag tap controller is not intended to be used by the design, it is recommended that a 1.5k-ohm pull-down resist or be connected to the jtag_trst# ball, to hold the jtag tap controller in the test-logic-reset state, which enables standard logic operation
february, 2007 lane good status leds expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 479 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 17.4 lane good status leds the pex 8524 provides lane good outputs, pex_lane_good[7:0]# and pex_lane_good[31:16]# , that can directly drive external common anode led modules to provide visual indication of the negotia ted link width for each port. each led corresponds to one lane. software can determine: which lanes have completed physical layer linkup, by performing a memory read of the software-controlled lane status register software-controlled lane status bits (port 0, offset 1f4h ). bits [ 31:16 , 7:0 ] correspond to lanes [31:16, 7:0], respectively. whether the link for each port ha s trained, by reading the vc0 resource status register vc0 negotiation pending and vc1 resource status register vc1 negotiation pending bits (offsets 160h [ 17 ] and 16ch [ 17 ], respectively) in each port. if the bit value is 0, the link has completed flow control initia lization. these registers can be read by either a pci express configuration request or memory read. the negotiated link width of each port, by reading the link status register negotiated link width field (offset 78h [ 25:20 ]) in each port. this register can be read by ei ther a configuration request or memory read.
test and debug plx technology, inc. 480 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 this page intentionally left blank.
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 481 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 18 electrical specifications 18.1 introduction this chapter contains the pex 8524 power-up /power-down sequencing rules and electrical specifications. 18.2 power-up/power-down sequence for reliable operation, vdd10 , vdd10s , and vdd10a should power-up first and power-down last. no specific sequence is required between the vtt_pex, vdd33 , and vdd33a supplies. all supply rails should power-up within 50 ms of one another. 18.3 absolute maximum ratings warning: maximum limits indicate the temperatures a nd voltages above which permanent damage can occur. proper operation at these conditions is not guaranteed, and continuous operation of the device at these limits is not recommended. table 18-1. absolute maximum rating (all voltages referenced to vss system ground) item symbol absolute maximum rating units i/o interface supply voltage vdd33 -0.5 to +4.6 v pll supply voltage vdd33a -0.5 to +4.6 v core (logic) supply voltage vdd10 -0.3 to +1.65 v serdes analog supply voltage vdd10a -0.3 to +1.65 a a. the serdes analog and digital power supplies should track within 0.01v of one another. v serdes digital supply voltage vdd10s -0.3 to +1.65 a v serdes termination supply voltage vtt_pex -0.3 to +2.5 v input voltage (3.3v interface) v i -0.3 to +4.6 v operating ambient temperature pex 8524vaa (commercial) pex 8524vbb/bc, pex 8524bb/bc (industrial) t a 0 to +70 -40 to +85 c c storage temperature t stg -55 to +150 c
electrical specifications plx technology, inc. 482 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 18.4 power characteristics table 18-2. operating condition power supply rails symbol parameter min typ max units vdd33 i/o supply 3.3v 10% 3.0 3.3 3.6 v vdd33a pll supply 3.3v 10% 3.0 3.3 3.6 v vdd10 digital core supply pex 8524vaa 1.153% pex 8524vbb/bc, pex 8524bb/bc 1.0v 10% 1.12 0.9 1.15 1.0 1.18 1.1 v v vdd10a analog serdes supply pex 8524vaa 1.153% pex 8524vbb/bc, pex 8524bb/bc 1.0v 10% 1.12 0.9 1.15 1.0 1.18 1.1 v v vdd10s digital serdes supply pex 8524vaa 1.153% pex 8524vbb/bc, pex 8524bb/bc 1.0v 10% 1.12 0.9 1.15 1.0 1.18 1.1 v v vtt_pex serdes termination supply voltage 1.35 1.5 1.8 v
february, 2007 power consumption expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 483 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 18.5 power consumption note: the total power values listed in table 18-3 are rounded to two digits. table 18-3. pex 8524vaa power dissipation (watts) {4 to 24 lanes} traffic conditions serdes/core vdd10 serdes vtt vdd33 total typ max typ max typ max typ max a. heavy 5.088 7.891 0.96 1.08 0.092 0.109 6.14 9.08 b. medium 4.688 7.601 0.96 1.08 0.092 0.109 5.74 8.79 c. light 4.288 6.891 0.96 1.08 0.092 0.109 5.34 8.08 a. peer-to-peer traffic, all lanes active, 80 to 90% link utilization. b. host-centric traffic, all lanes active, 50 to 70% link utilization. c. host-centric traffic, 75% la nes active, 50% link utilization. typical condition ? nominal process, room temperature and nominal voltage. maximum condition ? fast/fast process, -40c temperature and worst voltage. maximum power/serdes quad ? 325 mw. table 18-4. pex 8524vbb/bc power dissipation (watts) {4 to 24 lanes} traffic conditions core/ serdes digital (vdd10) pci express digital (vdd10s) pci express analog (vdd10a) serdes termination (vtt_pex) pll (vdd33a) gpio (vdd33) total typ max typ max typ max typ max typ max typ max typ max a. heavy 3.423.881.521.720.420.481.041.260.020.030.020.03 6.44 7.40 b. medium 3.15 3.57 1.28 1.45 0.36 0.40 0.88 1.06 0.02 0.03 0.02 0.03 5.71 6.54 c. light 2.56 2.9. 1.28 1.45 0.36 0.40 0.88 1.06 0.02 0.03 0.02 0.03 5.12 5.87 a. 85% lane bandwidth utilization. all 24 lanes in l0 active state. b. 35% lane bandwidth utilization. all 24 lanes in l0 active state. c. 10% lane bandwidth utilization. all 24 lanes in l0 active state. typ condition ? typical silicon process, 25c, nominal supply voltage. max condition ? fast silicon process, 0c, +10% supply voltage.
electrical specifications plx technology, inc. 484 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 table 18-5. pex 8524bb/bc power dissipation (watts) {4 to 24 lanes} traffic conditions core/ serdes digital (vdd10) pci express digital (vdd10s) pci express analog (vdd10a) serdes termination (vtt_pex) pll (vdd33a) gpio (vdd33) total typ max typ max typ max typ max typ max typ max typ max a. heavy 3.033.431.141.290.320.360.780.950.020.030.020.03 5.31 6.09 b. medium 1.99 2.26 0.958 1.09 0.27 0.30 0.66 0.79 0.02 0.03 0.02 0.03 3.92 4.50 c. light 1.44 1.63 0.958 1.09 0.27 0.30 0.66 0.79 0.02 0.03 0.02 0.03 3.37 3.87 a. 85% lane bandwidth utilization. all 24 lanes in l0 active state. b. 35% lane bandwidth utilization. all 24 lanes in l0 active state. c. 10% lane bandwidth utilization. all 24 lanes in l0 active state. typ condition ? typical silicon process, 25c, nominal supply voltage. max condition ? fast silicon process, 0c, +10% supply voltage.
february, 2007 i/o interface signal groupings expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 485 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 18.6 i/o interface signal groupings table 18-6. signal group pci express analog interface signal group signal type signals notes (a) pci express output (transmit) pex_petn[31:16, 7:0], pex_petp[31:16, 7:0], refer to table 18-9 (b) pci express input (receive) pex_pern[31:16, 7:0], pex_perp[31:16, 7:0], refer to table 18-10 (c) pci express differential clock input pex_refclkn, pex_refclkp refer to table 18-11 table 18-7. signal group digital interface signal group signal type signals notes (d) digital output ee_cs#, ee_di, ee_sk, hp_atnled[11:8, 1:0]#, hp_clken[11:8, 1:0]#, hp_perst[11:8, 1:0]#, hp_pwren[11:8, 1:0]#, hp_pwrled[11:8, 1:0]#, jtag_tdo, pex_lane_good[31:16, 7:0]#, pex_nt_reset# refer to table 18-8 (e) digital input a a. strap_ signals must be tied high to vdd33 or low to vss (gnd), ee_pr#, pex_perst#, strap_factory_test1#, strap_mode_sel[1:0], strap_nt_upstrm_portsel[3:0], strap_stn0_portcfg[4:0], strap_stn1_portcfg[3:0], strap_testmode[3:0], strap_upstrm_portsel[3:0] (f) digital input with internal pull-up resistor ee_do, hp_button[11:8, 1:0]#, hp_mrl[11:8, 1:0]#, hp_prsnt[11:8, 1:0]#, hp_pwrflt[11:8, 1:0]#, jtag_tck, jtag_tdi, jtag_tms, jtag_trst#
electrical specifications plx technology, inc. 486 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 table 18-8. dc electrical characteristics ? digital interface symbol signal group parameter min typ max unit conditions i ol (d) output low current 8 ma v ol = 0.4v i oh (d) output high current 8 ma v oh = 1.5v v il (e) (f) input low voltage 0.8 v v ih (e) (f) input high voltage 2.0 v c pin (a) ball capacitance tbd pf (b) ball capacitance tbd pf (c) ball capacitance 5 pf (d) ball capacitance 6 pf (e) (f) ball capacitance 5 pf i leakage (d) three-state leakage 500 na (e) input leakage 50 na (f) pull-up leakage +0.1/-8 +0.1/-20 a r pu (f) pull-up impedance 200k ohm
february, 2007 i/o interface signal groupings expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 487 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 table 18-9. pci express transmit (signal group a) ac and dc characteristics symbol parameter min typ max units comments ui unit interval 399.88 400 400.12 ps v tx-diffp-p differential peak-to-peak output voltage 0.800 1.2 v v tx-diffp-p = 2 * | v tx-d+ ? v tx-d-| v tx-de-ratio de-emphasized differential output voltage (ratio) -3.0 -3.5 -4.0 db ratio of the v tx-diffp-p of the 2 nd and following bits after a transition divided by the v tx-diffp-p of the 1 st bit after a transition. refer to note 1 . t tx-eye minimum tx eye width 0.75 ui the maximum transmitter jitter can be derived as: t tx-max-jitter = 1 ? t tx-eye = 0.25 ui this parameter is measured with the equivalent of a zero-j itter refere nce clock. refer to notes 1 and 2 . t tx-eye-median-to- max-jitter maximum time between the jitter median and maximum deviation from the median 0.125 ui jitter is defined as th e measurement variation of the crossing points (v tx-diff = 0v) in relation to recovered tx ui. refer to notes 1 and 2 . t tx-rise, t tx-fall d+/d- tx output rise/fall time 0.125 ui refer to notes 1 and 4 . v tx-cm-acp rms ac peak common mode output voltage 20 mv v tx-cm-acp = rms(|v tx-d+ + v tx-d- |/2 ? v tx-cm-dc ) v tx-cm-dc = dc (avg) of |v tx-d+ + v tx-d- |/2 refer to note 1 . v tx-cm-dc-active- idle-delta absolute delta of dc common mode voltage during l0 and electrical idle 0 100 mv |v tx-cm-dc [during l0] - v tx-cm-idle-dc [during electrical idle]| < 100mv v tx-cm-dc = dc (avg) of |v tx-d+ + v tx-d- |/2 [l0] v tx-cm-idle-dc = dc (avg) of |v tx-d+ + v tx-d- |/2 [electrical idle] refer to note 1 . v tx-cm-dc-line- delta absolute delta of dc common mode voltage between d+ and d- 025mv |v tx-cm-dc-d+ - v tx-cm-dc-d- | < 25mv v tx-cm-dc-d+ = dc (avg) of |v tx-d+ | v tx-cm-dc-d- = dc (avg) of |v tx-d- | refer to note 1 . v tx-idle-diffp electrical idle differential peak output voltage 0 20 mv v tx-idle-diffp = |v tx-idle-d+ - v tx-idle-d- | < 20mv refer to note 1 . v tx-rcv-detect amount of voltage change allowed during receiver detection 600 mv the total amount of voltage change that a transmitter can appl y to sense whether a low-impedance receiver is present. v tx-dc-cm tx dc common mode voltage 03.6v the allowed dc common mode voltage under any condition.
electrical specifications plx technology, inc. 488 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 i tx-short tx short circuit current limit 90 ma the total current the transmitter can provide when shorted to its ground. t tx-idle-min minimum time spent in electrical idle 50 ui minimum time a transmitter must be in electrical idle. utilized by the receiver to start looking for an elec trical idle exit after successfully receiving an electrical idle ordered-set. t tx-idle-set-to- idle maximum time to transition to a valid electrical idle after sending an electrical idle ordered-set 20 ui after sending an electrical idle ordered-set, the transmitter must meet all electrical idle specifications within this time. a de-bounce time for the transmitter to meet electrical idle after transitioning from l0. rl tx-diff differential return loss 10 db measured over 50 mhz to 1.25 ghz. rl tx-cm common mode return loss 6 db measured over 50 mhz to 1.25 ghz. z tx-diff-dc dc differential tx impedance 80 100 120 ohm tx dc differential mode low impedance. refer to note 5 . l tx-skew lane-to-lane output skew 500 + 2ui ps static skew between any two transmitter lanes within a single link. table 18-9. pci express transmit (signal group a) ac and dc characteristics (cont.) symbol parameter min typ max units comments
february, 2007 i/o interface signal groupings expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 489 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 notes: 1. specified at the measurement point into a timing and voltage compliance test load, as illustrated in figure 18-1 . figure 18-1. compliance test/measurement load 2. at t tx-eye = 0.75 ui provides for a total sum of deterministic and random jitter budget of t tx-jitter-max = 0.25 ui for the transmitter. the t tx-eye-median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half the total tx jitter budget. ( note: the median is not the same as the mean.) the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. this parameter is measured with the equivalent of a zero-jitter reference clock. the t tx-eye measurement is to be met at the target bit error rate. the t tx-eye-median-to-max-jitter specification is to be met using the compliance pattern at a sample size of 1,000,000 ui. 3. the transmitter input impedance shall result in a differential return loss, greater than or equal to 10 db, with a differential test input signal no less than 200 mv (peak value, 400 mv differential peak-to-peak) swing around ground, applied to d+ and d- lines and a common mode return loss greater than or equal to 6 db over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements is 50 ohms to ground for both the d+ and d- lines. the series capacitance c tx is optional for the return loss measurement. 4. measured between 20 to 80% at transmitter package balls into a test load, as illustrated in figure 18-1 , both v tx-d+ and v tx-d-. 5. z tx-diff-dc is the small signal resistance of the transmitter measured at a dc operating point that is equivalent to that established by connecting a 100 ohm resistor from d+ and d- while the tx is driving a static logic 1 or logic 0. equivalently, this parameter can be derived by measuring the rms voltage of the tx while transmitting a test pattern into two different differential terminations that are near 100 ohms. small signal resistance is measured by forcing a small change in differential voltage and dividing this by the corresponding change in current. tx silicon + package c = c tx c = c tx r = 50 ohms d+ package pin d- package pin r = 50 ohms
electrical specifications plx technology, inc. 490 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 table 18-10. pci express receive (signal group b) ac and dc characteristics symbol parameter min typ max units comments ui unit interval 399.88 400 400.12 ps the ui is 400 ps 300 ppm. v rx-diffp-p differential input peak-to-peak voltage 0.175 1.200 v v rx-diffp-p = 2*|v rx-d+ - v rx-d- | t rx-eye minimum receiver eye width 0.4 ui the maximum interconnect media and transmitter jitter that can be tolerated by the receiver can be derived as: t rx-max-jitter = 1 ? t rx-eye = 0.6 ui refer to notes 6 , 7 , and 8 . t rx-eye-median- to-max-jitter maximum time between the jitter median and maximum deviation from the median 0.3 ui jitter is defined as th e measurement variation of the crossing points (v tx-diff = 0v) in relation to recovered tx ui. refer to notes 6 and 7 . v rx-cm-acp ac peak common mode input voltage 150 mv v rx-cm-acp = |v rx-d+ + v rx-d- | /2 ? v rx-cm-dc ) v rx-cm-dc = dc (avg) of |v rx-d+ | refer to note 6 . rl rx-diff differential return loss 10 db measured over 50 mhz to 1.25 ghz. refer to note 9 . rl rx-cm common mode return loss 6db measured over 50 mhz to 1.25 ghz. refer to note 9 . z rx-diff-dc dc differential tx impedance 80 100 120 ohm rx dc differen tial mode impedance. z rx-dc dc input impedance 40 50 60 ohm required rx d+ and d- dc impedance (50 ohms 20% tolerance). refer to note 6 . v rx-idle-det- diffp-p electrical idle detect threshold 65 175 mv v rx-idle-det-diffp-p = 2* |v rx-d+ + v rx-d- | measured at the package balls of the receiver. t rx-idle-det-diff- entertime unexpected electrical idle enter idle detect threshold integration time 10 ms an un-expected electrical idle (v rx-diffp-p < v rx-idle-det-diffp-p ) must be recognized no longer than t rx-idle-det-diff-entertime to signal an unexpected idle condition. l rx-skew total skew 20 ns skew across all lanes in a link.
february, 2007 i/o interface signal groupings expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 491 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 notes: 6. the test load in figure 18-1 should be used as the rx device when taking measurements. 7. the t rx-eye-median-to-max-jitter specification ensures a jitter distribution in which the median and the maximum deviation from the median is less than half the total, 0.64. ( note: the median is not the same as the mean.) the jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. the t rx-eye measurement is to be met at the target bit error rate. the t rx-eye-median-to-max-jitter specification is to be me t using the compliance pattern at the sample size of 1,000,000 ui. 8. refer to the pci express jitter and ber white paper for details regarding the rx-eye measurement. 9. the receiver input impedance shall result in a differenti al return loss, greater than or equal to 10 db, with a differential test input signal of no less than 200 mv (peak value, 400 mv differential peak-to-peak) swing around ground, applied to d+ and d- lines and a common mode return loss greater than or equal to 6 db (no bias required) over a frequency range of 50 mhz to 1.25 ghz. this input impedance requirement applies to all valid input levels. the reference impedance for return loss measurements is 50 ohms to ground for both the d+ and d- lines. the series capacitance c tx is optional for the return loss measurement.
electrical specifications plx technology, inc. 492 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 notes: 1. pex_refclkn/p must be ac-coupled. use a 0.01 to 0.1 f capacitor. 2. specified at 20 to 80% points at the package balls. table 18-11. pci express differential clock (signal group c) ac and dc characteristics symbol parameter min typ max unit notes f refclk reference clock frequency 100 mhz v cm input common mode voltage 0.6 0.65 0.7 v 1 v sw differential voltage swing (0-to-peak) 125 800 mv differential voltage swi ng (peak-to-peak) 250 1,600 mv t r /t f clock input rise/fall time 1.5 ns 2 dc refclk input clock duty cycle 40 50 60 % r term input parallel terminat ion (single-ended) 55 ohm input parallel terminat ion (differential) 110 ohm ppm reference clock tolerance -300 +300 ppm
february, 2007 transmit drive characteristics expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 493 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 18.7 transmit drive characteristics the drive current and the transmit equalization function is programmable, to allow for optimization of different backplane lengths and materials. 18.7.1 drive current the nominal drive current is progr ammable (2-bit) within the range of 10 to 28 ma. [refer to the serdes nominal drive current select register (offset 248h ) for details.] the nominal drive current can be further programmed (4-bit) with finer granularity, within the range of 0.65x to 1.35x. [refer to the serdes drive current level select 1 and serdes drive current level select 2 registers (offsets 24ch and 250h , respectively) for details.] 18.7.2 transmit equalization the transmitter incorporates programmable (4-bit) first-order equalization, within the range of 0 to -7.96 db. [refer to the serdes drive equalization level select 1 and serdes drive equalization level select 2 registers (offsets 254h and 258h , respectively) for details.] 18.7.3 transmit termination adjust the pci express base r1.0a specifies termination (50 ohms nominal ) at the transmit side to vtt. the transmit driver incorporat es a 2-bit register (per serdes quad) , which allows for a 20% termination adjustment to mitigate stub effects and other non-idealities in the pcb channel. refer to the physical layer register serdes quad x txtermadjust fields (offset 22ch [15:8]) for details. 18.8 receive characteristics the following programmable bits cont rol the electrical charact eristics of the receiver circuit, to mitigate the effects of signal loss and distortion across the pcb channel. 18.8.1 receive equalization the receiver incorporates a programmable 2-bit regist er (per serdes quad) to modify the high-pass filter within the circuit, which serves to mitiga te the effects of inter symbol interference due to frequency-dependent losses across the pcb material. refer to physical layer register serdes quad x rxeqctl fields (offset 22ch[31:24]) for details. 18.8.2 receive termination adjust the pci express base r1.0a specifies termination (50 ohms nomi nal) at the receive side to ground. the receiver input incorporates a 2-bit register (per serdes quad), which allows for a 20% termination adjustment to mitigate stub effects and other non-idealities in the pcb channel. refer to the physical layer register serdes quad x rxtermadjust fields (offset 22ch[23:16]) for details.
electrical specifications plx technology, inc. 494 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 this page intentionally left blank.
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 495 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 chapter 19 mechanical specifications 19.1 pex 8524 package specifications the pex 8524vaa/bb/bc is offered in a 35-mm square, 680-ball pbga (plastic bga) package. table 19-1 defines the package specifications. the pex 8524bb/bc is offered in a 31-mm square, 644-ball pbga (plastic bga) package. table 19-2 defines the package specifications. unpopulated bga balls allow board design and placement of board-leve l de-coupling capacitors between vdd33, vdd10, vdd10a, vdd10s, and vss/ground. table 19-1. pex 8524vaa/bb/bc package specifications parameter specification package type plastic ball grid array (pbga) number of balls 680 package dimensions 35 x 35 mm (approximately 2.23 mm high) ball matrix pattern 34 x 34 mm (10 x 10 center area reserved for ground) ball pitch 1.00 mm ball diameter 0.60 0.15 mm ball spacing 0.40 mm table 19-2. pex 8524bb/bc package specifications parameter specification package type plastic ball grid array (pbga) number of balls 644 package dimensions 31 x 31 mm (approximately 2.42 mm high) ball matrix pattern 30 x 30 mm (10 x 10 center area reserved for ground) ball pitch 1.00 mm ball diam eter 0.61 mm ball spacing 0.40 mm
mechanical specifications plx technology, inc. 496 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 19.2 pex 8524 mechanical dimensions figure 19-1. pex 8524vaa/bb/bc 680-ball pbga mechanical dimensions 35.00 33.00 35.00 30.00 4.00 45 o 34 4 3 2 1 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al am an ap 1.00 35.00 33.00 1.00 0.50 2.23 0.56 1.17 heat slug exposed area ball a1 corner identification dimensions: dimensions in mm; all dimensions are nominal bottom view 0.20 (3x) 30 o ty p
february, 2007 pex 8524 mechanical dimensions expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 497 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 figure 19-2. pex 8524bb/bc 644-ball pbga mechanical dimensions
mechanical specifications plx technology, inc. 498 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 19.3 thermal characteristics neither the pex 8524v nor pex 8524 includes a heat si nk. the information described in this section is based on sample thermal performance when a heat sink is used with the pex 8524v or pex 8524, and is provided for reference only. table 19-3. sample pex 8524vaa heat sink and airflow requirements* traffic commercial commercial heat sink airflow light yes 2 m/s medium high table 19-4. sample pex 8524vbb/bc and pex 8524bb/bc heat sink and airflow requirements* traffic commercial industrial heat sink airflow heat sink airflow light yes1 m/syes2 m/s medium high * legend for table 19-3 and table 19-4 : light traffic host-centric traffic, 75% lanes active, 50% link utilization medium traffic host-centric traffic, a ll lanes active, 50 to 70% link utilization heavy traffic peer-to-peer traffic, all lanes active, 80 to 90% link utilization typical nominal process, room temperature and nominal voltage maximum fast/fast process, -40c temperature and worst voltage maximum power/serdes quad 325 mw
february, 2007 thermal characteristics expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 499 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 table 19-5 defines the package thermal resistance, in c/w ( j-a ). table 19-5. sample pex 8524v and pex 8524 package thermal resistance device air flow no heat sink heat sink pex 8524v 0 m/s ? 8.0 1 m/s 6.5 2 m/s 5.3 pex 8524 0 m/s ? 11.1 1 m/s 6.4 2 m/s 5.5
mechanical specifications plx technology, inc. 500 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 figure 19-3. sample pex 8524v copper fin heat sink (38 x 38 x 12.7 mm) figure 19-4. sample pex 8524 copper fin heat sink (31 x 31 x 13 mm) note: the 3-d heat sink illustration for the pex 8524 will be included in a future data book update. 38.0 mm 38.0 mm 1.8 mm dia. 2.0 mm 12.7 mm 1.8 mm dia. 1.5 mm 31.0 mm 31.0 mm 13.0 mm
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 501 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 appendix a serial eeprom memory map a.1 serial eeprom memory map in table a-1 , all register offsets are byte addresses, and all serial eeprom addresses are dword addresses (byte addresses shifted right 2 bits). th e serial eeprom dword addresses are used directly for the serial eeprom control register serial eeprom block address field (port 0, offset 260h [ 12:0 ]).
502 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port /24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 serial eeprom memory map plx technology, inc. table a-1. pex 8524v and pex 8524 serial eeprom memory map register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual 000h product identification 000h 31ah 4b8h 7d2h 85ch 8e6h 970h a68h 004h command/status 001h 31bh 4b9h 7d3h 85dh 8e7h 971h a69h 008h class code and revision id 002h 31ch 4bah 7d4h 85eh 8e8h 972h a6ah 00ch miscellaneous control 003h 31dh 4bbh 7d5h 85fh 8e9h 973h a6bh 010h base address 0 004h 31eh 4bch 7d6h 860h 8eah 974h a6ch 014h base address 1 005h 31fh 4bdh 7d7h 861h 8ebh 975h a6dh 018h bus number 006h 320h 4beh 7d8h 862h 8ech 976h a6eh 01ch secondary status, i/o limit, and i/o base 007h 321h 4bfh 7d9h 863h 8edh 977h a6fh 020h memory base and limit address 008h 322h 4c0h 7dah 864h 8eeh 978h a70h 024h prefetchable memory base and limit address 009h 323h 4c1h 7dbh 865h 8efh 979h a71h 028h prefetchable memory upper base address[63:32] 00ah 324h 4c2h 7dch 866h 8f0h 97ah a72h 02ch prefetchable memory upper limit address[63:32] 00bh 325h 4c3h 7ddh 867h 8f1h 97bh a73h 030h i/o base address[31:16] a nd i/o limit address[31:16] (transparent mode) expansion rom base address (nt link port) reserved (nt virtual ports) 00ch 326h 4c4h 7deh 868h 8f2h 97ch a74h 034h capabilities pointer 00dh 327h 4c5h 7dfh 869h 8f3h 97dh a75h 038h expansion rom base address 00eh 328h 4c6h 7e0h 86ah 8f4h 97eh a76h 03ch bridge control and interrupt signal 00fh 329h 4c7h 7e1h 86bh 8f5h 97fh a77h
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 503 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 february, 2007 serial eeprom memory map 040h power management capability 010h 32ah 4c8h 7e2h 86ch 8f6h 980h a78h 044h power management status and control 011h 32bh 4c9h 7e3h 86dh 8f7h 981h a79h pm data [31:24] and data scale [14:13], for data select [12:9] = 0h b7ch b89h bb0h bbdh bcah bd7h b62h b6fh pm data [31:24] and data scale [14:13], for data select [12:9] = 3h b7dh b8ah bb1h bbeh bcbh bd8h b63h b70h pm data [31:24] and data scale [14:13], for data select [12:9] = 4h b7eh b8bh bb2h bbfh bcch bd9h b64h b71h pm data [31:24] and data scale [14:13], for data select [12:9] = 7h b7fh b8ch bb3h bc0h bcdh bdah b65h b72h 048h message signaled in terrupt capability 012h 32ch 4cah 7e4h 86eh 8f8h 982h a7ah 04ch message address[31:0] 013h 32dh 4cbh 7e5h 86fh 8f9h 983h a7bh 050h message upper address[63:32] 014h 32eh 4cch 7e6h 870h 8fah 984h a7ch 054h message data 015h 32fh 4cdh 7e7h 871h 8fbh 985h a7dh 058h reserved 016h 330h 4ceh 7e8h 872h 8fch 986h a7eh 05ch reserved 017h 331h 4cfh 7e9h 873h 8fdh 987h a7fh 060h reserved 018h 332h 4d0h 7eah 874h 8feh 988h a80h 064h reserved 019h 333h 4d1h 7ebh 875h 8ffh 989h a81h 068h pci express capability list and capabilities 01ah 334h 4d2h 7ech 876h 900h 98ah a82h 06ch device capabilities 01bh 335h 4d3h 7edh 877h 901h 98bh a83h 070h device status and control 01ch 336h 4d4h 7eeh 878h 902h 98ch a84h 074h link capabilities 01dh 337h 4d5h 7efh 879h 903h 98dh a85h 078h link status and control 01eh 338h 4d6h 7f0h 87ah 904h 98eh a86h 07ch slot capabilities 01fh 339h 4d7h 7f1h 87bh 905h 98fh a87h 080h slot status and control 020h 33ah 4d8h 7f2h 87ch 906h 990h a88h 084h reserved 021h 33bh 4d9h 7f3h 87dh 907h 991h a89h 088h reserved 022h 33ch 4dah 7f4h 87eh 908h 992h a8ah 08ch reserved 023h 33dh 4dbh 7f5h 87fh 909h 993h a8bh 090h set virtual interface irq (nt virtual/link port s only) ? ? ? ? ? ? 994h a8ch 094h clear virtual interface irq (nt virtual/link port s only) ? ? ? ? ? ? 995h a8dh 098h set virtual interface irq mask (nt virtual/link ports only) ? ? ? ? ? ? 996h a8eh 09ch clear virtual interface irq mask (nt virtual/link ports only) ? ? ? ? ? ? 997h a8fh table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
504 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port /24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 serial eeprom memory map plx technology, inc. 0a0h set link interface irq (nt virtual/link ports only) ? ? ? ? ? ? 998h a90h 0a4h clear link interface irq (nt virtual/link ports only) ? ? ? ? ? ? 999h a91h 0a8h set link interface irq mask (nt virtual/link ports only) ? ? ? ? ? ? 99ah a92h 0ach clear link interface irq mask (nt virtual/link ports only) ? ? ? ? ? ? 99bh a93h 0b0h nt port scratchpad_0 (nt virtual/link ports only) ? ? ? ? ? ? 99ch a94h 0b4h nt port scratchpad_1 (nt virtual/link ports only) ? ? ? ? ? ? 99dh a95h 0b8h nt port scratchpad_2 (nt virtual/link ports only) ? ? ? ? ? ? 99eh a96h 0bch nt port scratchpad_3 (nt virtual/link ports only) ? ? ? ? ? ? 99fh a97h 0c0h nt port scratchpad_4 (nt virtual/link ports only) ? ? ? ? ? ? 9a0h a98h 0c4h nt port scratchpad_5 (nt virtual/link ports only) ? ? ? ? ? ? 9a1h a99h 0c8h nt port scratchpad_6 (nt virtual/link ports only) ? ? ? ? ? ? 9a2h a9ah 0cch nt port scratchpad_7 (nt virtual/link ports only) ? ? ? ? ? ? 9a3h a9bh 0d0h nt port virtual interface bar1 setup (nt virtual/link ports only) ? ? ? ? ? ? 9a4h a9ch 0d4h nt port virtual interface bar2 setup (nt virtual/link ports only) ? ? ? ? ? ? 9a5h a9dh 0d8h nt port virtual interface bar3 setup (nt virtual/link ports only) ? ? ? ? ? ? 9a6h a9eh 0dch nt port virtual interface bar4/5 setup (nt virtual/link ports only) ??????9a7ha9fh 0e0h nt port virtual interface bar5 setup (nt virtual/link ports only) ? ? ? ? ? ? 9a8h aa0h 0e4h reserved 039h 353h 4f1h 80bh 895h 91fh 9a9h aa1h 0e8h reserved 03ah 354h 4f2h 80ch 896h 920h 9aah aa2h 0ech reserved 03bh 355h 4f3h 80dh 897h 921h 9abh aa3h 0f0h reserved 03ch 356h 4f4h 80eh 898h 922h 9ach aa4h 0f4h reserved 03dh 357h 4f5h 80fh 899h 923h 9adh aa5h 0f8h configuration address window (nt virtual/link ports only) ? ? ? ? ? ? 9aeh aa6h 0fch configuration data window (nt virtual/link ports only) ? ? ? ? ? ? 9afh aa7h 100h device serial number extended capability 040h 35ah 4f8h 812h 89ch 926h 9b0h aa8h 104h serial number (lower dw) 041h 35bh 4f9h 813h 89dh 927h 9b1h aa9h 108h serial number (higher dw) 042h 35ch 4fah 814h 89eh 928h 9b2h aaah 138h power budgeting extended capability 04eh 368h 506h 820h 8aah 934h 9beh ab6h 13ch data select 04fh 369h 507h 821h 8abh 935h 9bfh ab7h table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 505 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 february, 2007 serial eeprom memory map 140h power budgeting data (next row overwrites this row) 050h 36ah 508h 822h 8ach 936h 9c0h ab8h power budgeting data, data se lect (offset 13ch) = 00h b81h b8eh bb5h bc2h bcfh bdch b67h b74h power budgeting data, data se lect (offset 13ch) = 01h b82h b8fh bb6h bc3h bd0h bddh b68h b75h power budgeting data, data se lect (offset 13ch) = 02h b83h b90h bb7h bc4h bd1h bdeh b69h b76h power budgeting data, data se lect (offset 13ch) = 03h b84h b91h bb8h bc5h bd2h bdfh b6ah b77h power budgeting data, data se lect (offset 13ch) = 04h b85h b92h bb9h bc6h bd3h be0h b6bh b78h power budgeting data, data se lect (offset 13ch) = 05h b86h b93h bbah bc7h bd4h be1h b6ch b79h power budgeting data, data se lect (offset 13ch) = 06h b87h b94h bbbh bc8h bd5h be2h b6dh b7ah power budgeting data, data se lect (offset 13ch) = 07h b88h b95h bbch bc9h bd6h be3h b6eh b7bh 144h power budget capability 051h 36bh 509h 823h 8adh 937h 9c1h ab9h 148h virtual channel ex tended capability 052h 36ch 50ah 824h 8aeh 938h 9c2h abah 14ch port vc capability 1 053h 36dh 50bh 825h 8afh 939h 9c3h abbh 150h port vc capability 2 054h 36eh 50ch 826h 8b0h 93ah 9c4h abch 154h port vc status and control (next row overwrites this row) 055h 36fh 50dh 827h 8b1h 93bh 9c5h abdh port vc status and control (must load after vc arbitration table (offsets 1b8h to 1c4h ) b80h b8dh bb4h bc1h bceh bdbh b66h b73h 158h vc0 resource capability 056h 370h 50eh 828h 8b2h 93ch 9c6h abeh 15ch vc0 resource control 057h 371h 50fh 829h 8b3h 93dh 9c7h abfh 160h vc0 resource status 058h 372h 510h 82ah 8b4h 93eh 9c8h ac0h 164h vc1 resource capability 059h 373h 511h 82bh 8b5h 93fh 9c9h ac1h 168h vc1 resource control 05ah 374h 512h 82ch 8b6h 940h 9cah ac2h 16ch vc1 resource status 05bh 375h 513h 82dh 8b7h 941h 9cbh ac3h 1b8h vc arbitration table phase 7-0 06eh 388h 526h 840h 8cah 954h 9deh ad6h 1bch vc arbitration table phase 15-8 06fh 389h 527h 841h 8cbh 955h 9dfh ad7h 1c0h vc arbitration table phase 23-16 070h 38ah 528h 842h 8cch 956h 9e0h ad8h 1c4h vc arbitration table phase 31-24 071h 38bh 529h 843h 8cdh 957h 9e1h ad9h 1c8h ecc check disable 072h 38ch 52ah 844h 8ceh 958h 9e2h adah 1cch error handler 32-bit error status (factory test only) 073h 38dh 52bh 845h 8cfh 959h 9e3h adbh 1d0h error handler 32-bit error mask (factory test only) 074h 38eh 52ch 846h 8d0h 95ah 9e4h adch 1d4h reserved 075h ? 52dh ? ? ? ? ? 1d8h reserved 076h ? 52eh ? ? ? ? ? table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
506 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port /24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 serial eeprom memory map plx technology, inc. 1dch debug control 077h ? ? ? ? ? 9e7h adfh 1e0h power management hot pl ug user configuration 078h 392h 530h 84ah 8d4h 95eh 9e8h ae0h 1e4h egress control and status 079h 393h 531h 84bh 8d5h 95fh 9e9h ae1h 1e8h bad tlp count 07ah 394h 532h 84ch 8d6h 960h 9eah ae2h 1ech bad dllp count 07bh 395h 533h 84dh 8d7h 961h 9ebh ae3h 1f0h plx-specific relaxed ordering enable 07ch 396h 534h 84eh 8d8h 962h 9ech ae4h 1f4h software-controlled lane status 07dh 397h 535h 84fh 8d9h 963h 9edh ae5h 1f8h ack transmission latency limit 07eh 398h 536h 850h 8dah 964h 9eeh ae6h 1fch reserved 07fh ? 537h ? ? ? ? ? 200h reserved 080h ? 538h ? ? ? ? ? 204h reserved 081h ? 539h ? ? ? ? ? 208h reserved 082h ? 53ah ? ? ? ? ? 20ch reserved 083h ? 53bh ? ? ? ? ? 210h phy user test pattern 0 084h ? 53ch ? ? ? ? ? 214h phy user test pattern 4 085h ? 53dh ? ? ? ? ? 218h phy user test pattern 8 086h ? 53eh ? ? ? ? ? 21ch phy user test pattern 12 087h ? 53fh ? ? ? ? ? 220h physical layer co mmand and status 088h ? 540h ? ? ? ? ? 224h port configuration 089h ? 541h ? ? ? ? ? 228h physical layer test 08ah ? 542h ? ? ? ? ? 22ch physical layer (factory test only) 08bh ? 543h ? ? ? ? ? 230h physical layer port command 08ch ? 544h ? ? ? ? ? 234h skip ordered-set interval 08dh ? 545h ? ? ? ? ? 238h quad 0 serdes diagnostic data 08eh ? 546h ? ? ? ? ? 23ch quad 1 serdes diagnostic data 08fh ? 547h ? ? ? ? ? 240h quad 2 serdes diagnostic data 090h ? 548h ? ? ? ? ? 244h quad 3 serdes diagnostic data 091h ? 549h ? ? ? ? ? 248h serdes nominal drive current select 092h ? 54ah ? ? ? ? ? 24ch serdes drive current level select 1 093h ? 54bh ? ? ? ? ? 250h serdes drive current level select 2 094h ? 54ch ? ? ? ? ? table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 507 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 february, 2007 serial eeprom memory map 254h serdes drive equalization level select 1 095h ? 54dh ? ? ? ? ? 258h serdes drive equalization level select 2 096h ? 54eh ? ? ? ? ? 25ch reserved 097h ? 54fh ? ? ? ? ? 260h serial eeprom status and control 098h ? ? ? ? ? ? ? 264h serial eeprom buffer 099h ? ? ? ? ? ? ? 28ch reserved 0a3h ? 55bh ? ? ? ? ? 290h reserved 0a4h ? 55ch ? ? ? ? ? 2c8h bus number cam 0 0b2h ? 56ah ? ? ? ? ? 2cch bus number cam 1 0b3h ? 56bh ? ? ? ? ? 2d0h reserved 0b4h ? 56ch ? ? ? ? ? 2d4h reserved 0b5h ? 56dh ? ? ? ? ? 2e8h bus number cam 8 0bah ? 572h ? ? ? ? ? 2ech bus number cam 9 0bbh ? 573h ? ? ? ? ? 2f0h bus number cam 10 0bch ? 574h ? ? ? ? ? 2f4h bus number cam 11 0bdh ? 575h ? ? ? ? ? 308h i/o cam_0 and i/o cam_1 0c2h ? 57ah ? ? ? ? ? 30ch reserved 0c3h ? 57bh ? ? ? ? ? 318h i/o cam_8 and i/o cam_9 0c6h ? 57eh ? ? ? ? ? 31ch i/o cam_10 and i/o cam_11 0c7h ? 57fh ? ? ? ? ? 348h amcam_0 memory limit and base 0d2h ? 58ah ? ? ? ? ? 34ch amcam_0 prefetchable memo ry limit and base[31:0] 0d3h ? 58bh ? ? ? ? ? 350h amcam_0 prefetchable memory base[63:32] 0d4h ? 58ch ? ? ? ? ? 354h amcam_0 prefetchable memory limit[63:32] 0d5h ? 58dh ? ? ? ? ? 358h amcam_1 memory limit and base 0d6h ? 58eh ? ? ? ? ? 35ch amcam_1 prefetchable memo ry limit and base[31:0] 0d7h ? 58fh ? ? ? ? ? 360h amcam_1 prefetchable memory base[63:32] 0d8h ? 590h ? ? ? ? ? 364h amcam_1 prefetchable memory limit[63:32] 0d9h ? 591h ? ? ? ? ? 368h reserved 0dah ? 592h ? ? ? ? ? 36ch reserved 0dbh ? 593h ? ? ? ? ? 370h reserved 0dch ? 594h ? ? ? ? ? table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
508 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port /24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 serial eeprom memory map plx technology, inc. 374h reserved 0ddh ? 595h ? ? ? ? ? 378h reserved 0deh ? 596h ? ? ? ? ? 37ch reserved 0dfh ? 597h ? ? ? ? ? 380h reserved 0e0h ? 598h ? ? ? ? ? 384h reserved 0e1h ? 599h ? ? ? ? ? 3c8h amcam_8 memory limit and base 0f2h?5aah????? 3cch amcam_8 prefetchable memo ry limit and base[31:0] 0f3h ? 5abh ? ? ? ? ? 3d0h amcam_8 prefetchable memory base[63:32] 0f4h ? 5ach ? ? ? ? ? 3d4h amcam_8 prefetchable memory limit[63:32] 0f5h?5adh????? 3d8h amcam_9 memory limit and base 0f6h ? 5aeh ? ? ? ? ? 3dch amcam_9 prefetchable memo ry limit and base[31:0] 0f7h ? 5afh ? ? ? ? ? 3e0h amcam_9 prefetchable memory base[63:32] 0f8h ? 5b0h ? ? ? ? ? 3e4h amcam_9 prefetchable memory limit[63:32] 0f9h ? 5b1h ? ? ? ? ? 3e8h amcam_10 memory limit and base 0fah?5b2h????? 3ech amcam_10 prefetchable lim it and memory base[31:0] 0fbh ? 5b3h ? ? ? ? ? 3f0h amcam_10 prefetchable memory base[63:32] 0fch ? 5b4h ? ? ? ? ? 3f4h amcam_10 prefetchable memory limit[63:32] 0fdh?5b5h????? 3f8h amcam_11 memory limit and base 0feh?5b6h????? 3fch amcam_11 prefetchable lim it and memory base[31:0] 0ffh ? 5b7h ? ? ? ? ? 400h amcam_11 prefetchable memory base[63:32] 100h ? 5b8h ? ? ? ? ? 404h amcam_11 prefetchable memory limit[63:32] 101h ? 5b9h ? ? ? ? ? 660h ingress control 198h ? 650h ? ? ? ? ? 664h reserved 199h ? 651h ? ? ? ? ? 668h ingress port enable 19ah ? 652h ? ? ? ? ? 680h i/ocam_0 upper port 0 1a0h ? 658h ? ? ? ? ? 684h i/ocam_1 upper port 1 1a1h ? 659h ? ? ? ? ? 688h reserved 1a2h ? 65ah ? ? ? ? ? 68ch reserved 1a3h ? 65bh ? ? ? ? ? 690h reserved 1a4h ? 65ch ? ? ? ? ? 694h reserved 1a5h ? 65dh ? ? ? ? ? table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 509 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 february, 2007 serial eeprom memory map 698h reserved 1a6h ? 65eh ? ? ? ? ? 69ch reserved 1a7h ? 65fh ? ? ? ? ? 6a0h i/ocam_8 upper port 8 1a8h ? 660h ? ? ? ? ? 6a4h i/ocam_9 upper port 9 1a9h ? 661h ? ? ? ? ? 6a8h i/ocam_10 upper port 10 1aah ? 662h ? ? ? ? ? 6ach i/ocam_11 upper port 11 1abh ? 663h ? ? ? ? ? 6b0h reserved 1ach ? 664h ? ? ? ? ? 6b4h reserved 1adh ? 665h ? ? ? ? ? 6b8h reserved 1aeh ? 666h ? ? ? ? ? 6bch reserved 1afh ? 667h ? ? ? ? ? 6c0h bar0 for port 0 1b0h ? 668h ? ? ? ? ? 6c4h bar1 for port 0 1b1h ? 669h ? ? ? ? ? 6c8h bar0 for port 1 1b2h ? 66ah ? ? ? ? ? 6cch bar1 for port 1 1b3h ? 66bh ? ? ? ? ? 6d0h reserved 1b4h ? 66ch ? ? ? ? ? 6d4h reserved 1b5h ? 66dh ? ? ? ? ? 6d8h reserved 1b6h ? 66eh ? ? ? ? ? 6dch reserved 1b7h ? 66fh ? ? ? ? ? 6e0h reserved 1b8h ? 670h ? ? ? ? ? 6e4h reserved 1b9h ? 671h ? ? ? ? ? 6e8h reserved 1bah ? 672h ? ? ? ? ? 6ech reserved 1bbh ? 673h ? ? ? ? ? 6f0h reserved 1bch ? 674h ? ? ? ? ? 6f4h reserved 1bdh ? 675h ? ? ? ? ? 6f8h reserved 1beh ? 676h ? ? ? ? ? 6fch reserved 1bfh ? 677h ? ? ? ? ? 700h bar0 for port 8 1c0h ? 678h ? ? ? ? ? 704h bar1 for port 8 1c1h ? 679h ? ? ? ? ? 708h bar0 for port 9 1c2h ? 67ah ? ? ? ? ? 70ch bar1 for port 9 1c3h ? 67bh ? ? ? ? ? table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
510 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port /24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 serial eeprom memory map plx technology, inc. 710h bar0 for port 10 1c4h ? 67ch ? ? ? ? ? 714h bar1 for port 10 1c5h ? 67dh ? ? ? ? ? 718h bar0 for port 11 1c6h ? 67eh ? ? ? ? ? 71ch bar1 for port 11 1c7h ? 67fh ? ? ? ? ? 720h reserved 1c8h ? 680h ? ? ? ? ? 724h reserved 1c9h ? 681h ? ? ? ? ? 728h reserved 1cah ? 682h ? ? ? ? ? 72ch reserved 1cbh ? 683h ? ? ? ? ? 730h reserved 1cch ? 684h ? ? ? ? ? 734h reserved 1cdh ? 685h ? ? ? ? ? 738h reserved 1ceh ? 686h ? ? ? ? ? 73ch reserved 1cfh ? 687h ? ? ? ? ? 740h vc0 port 0 capability 1d0h ? 688h ? ? ? ? ? 744h vc1 port 0 capability 1d1h ? 689h ? ? ? ? ? 748h vc0 port 1 capability 1d2h ? 68ah ? ? ? ? ? 74ch vc1 port 1 capability 1d3h ? 68bh ? ? ? ? ? 750h reserved 1d4h ? 68ch ? ? ? ? ? 754h reserved 1d5h ? 68dh ? ? ? ? ? 758h reserved 1d6h ? 68eh ? ? ? ? ? 75ch reserved 1d7h ? 68fh ? ? ? ? ? 760h reserved 1d8h ? 690h ? ? ? ? ? 764h reserved 1d9h ? 691h ? ? ? ? ? 768h reserved 1dah ? 692h ? ? ? ? ? 76ch reserved 1dbh ? 693h ? ? ? ? ? 770h reserved 1dch ? 694h ? ? ? ? ? 774h reserved 1ddh ? 695h ? ? ? ? ? 778h reserved 1deh ? 696h ? ? ? ? ? 77ch reserved 1dfh ? 697h ? ? ? ? ? 780h vc0 port 8 capability 1e0h ? 698h ? ? ? ? ? 784h vc1 port 8 capability 1e1h ? 699h ? ? ? ? ? table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 511 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 february, 2007 serial eeprom memory map 788h vc0 port 9 capability 1e2h ? 69ah ? ? ? ? ? 78ch vc1 port 9 capability 1e3h ? 69bh ? ? ? ? ? 790h vc0 port 10 capability 1e4h ? 69ch ? ? ? ? ? 794h vc1 port 10 capability 1e5h ? 69dh ? ? ? ? ? 798h vc0 port 11 capability 1e6h ? 69eh ? ? ? ? ? 79ch vc1 port 11 capability 1e7h ? 69fh ? ? ? ? ? 7a0h reserved 1e8h?6a0h????? 7a4h reserved 1e9h?6a1h????? 7a8h reserved 1eah ? 6a2h ? ? ? ? ? 7ach reserved 1ebh?6a3h????? 7b0h reserved 1ech?6a4h????? 7b4h reserved 1edh ? 6a5h ? ? ? ? ? 7b8h reserved 1eeh?6a6h????? 7bch reserved 1efh?6a7h????? 7c0h reserved 1f0h ? 6a8h ? ? ? ? ? 7c4h reserved 1f1h ? 6a9h ? ? ? ? ? 7c8h reserved 1f2h?6aah????? 7cch reserved 1f3h ? 6abh ? ? ? ? ? 7d0h reserved 1f4h ? 6ach ? ? ? ? ? 7d4h reserved 1f5h?6adh????? 7d8h reserved 1f6h ? 6aeh ? ? ? ? ? 7dch reserved 1f7h ? 6afh ? ? ? ? ? 7e0h reserved 1f8h ? 6b0h ? ? ? ? ? 7e4h reserved 1f9h ? 6b1h ? ? ? ? ? 7e8h reserved 1fah?6b2h????? 7ech reserved 1fbh ? 6b3h ? ? ? ? ? 7f0h reserved 1fch ? 6b4h ? ? ? ? ? 7f4h reserved 1fdh?6b5h????? 7f8h reserved 1feh?6b6h????? 7fch reserved 1ffh ? 6b7h ? ? ? ? ? table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
512 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port /24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 serial eeprom memory map plx technology, inc. 800h reserved 200h ? 6b8h ? ? ? ? ? 804h reserved 201h ? 6b9h ? ? ? ? ? 808h reserved 202h ? 6bah ? ? ? ? ? 80ch reserved 203h ? 6bbh ? ? ? ? ? 810h reserved 204h ? 6bch ? ? ? ? ? 814h reserved 205h ? 6bdh ? ? ? ? ? 818h reserved 206h ? 6beh ? ? ? ? ? 81ch reserved 207h ? 6bfh ? ? ? ? ? 820h reserved 208h ? 6c0h ? ? ? ? ? 824h reserved 209h ? 6c1h ? ? ? ? ? 828h reserved 20ah ? 6c2h ? ? ? ? ? 82ch reserved 20bh ? 6c3h ? ? ? ? ? 830h reserved 20ch ? 6c4h ? ? ? ? ? 834h reserved 20dh ? 6c5h ? ? ? ? ? 838h reserved 20eh ? 6c6h ? ? ? ? ? 83ch reserved 20fh ? 6c7h ? ? ? ? ? 840h port 0 vc capability_1 210h ? 6c8h ? ? ? ? ? 844h port 1 vc capability_1 211h ? 6c9h ? ? ? ? ? 848h reserved 212h ? 6cah ? ? ? ? ? 84ch reserved 213h ? 6cbh ? ? ? ? ? 860h port 8 vc capability_1 218h ? 6d0h ? ? ? ? ? 864h port 9 vc capability_1 219h ? 6d1h ? ? ? ? ? 868h port 10 vc capability_1 21ah ? 6d2h ? ? ? ? ? 86ch port 11 vc capability_1 21bh ? 6d3h ? ? ? ? ? 9f4h inch fc update pending timer 27dh ? 735h ? ? ? ? ? 9fch inch mode 27fh ? 737h ? ? ? ? ? a00h inch threshold port 0 or 8 vc0 posted 280h ? 738h ? ? ? ? ? a04h inch threshold port 0 or 8 vc0 non-posted 281h ? 739h ? ? ? ? ? a08h inch threshold port 0 or 8 vc0 completion 282h ? 73ah ? ? ? ? ? a0ch inch threshold port 0 or 8 vc1 posted 283h ? 73bh ? ? ? ? ? table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 513 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 february, 2007 serial eeprom memory map a10h inch threshold port 0 or 8 vc1 non-posted 284h ? 73ch ? ? ? ? ? a14h inch threshold port 0 or 8 vc1 completion 285h ? 73dh ? ? ? ? ? a18h inch threshold port 1 or 9 vc0 posted 286h ? 73eh ? ? ? ? ? a1ch inch threshold port 1 or 9 vc0 non-posted 287h ? 73fh ? ? ? ? ? a20h inch threshold port 1 or 9 vc0 completion 288h ? 740h ? ? ? ? ? a24h inch threshold port 1 or 9 vc1 posted 289h ? 741h ? ? ? ? ? a28h inch threshold port 1 or 9 vc1 non-posted 28ah ? 742h ? ? ? ? ? a2ch inch threshold port 1 or 9 vc1 completion 28bh ? 743h ? ? ? ? ? a30h inch threshold port 10 vc0 posted 28ch ? 744h ? ? ? ? ? a34h inch threshold port 10 vc0 non-posted 28dh ? 745h ? ? ? ? ? a38h inch threshold port 10 vc0 completion 28eh ? 746h ? ? ? ? ? a3ch inch threshold port 10 vc1 posted 28fh ? 747h ? ? ? ? ? a40h inch threshold port 10 vc1 non-posted 290h ? 748h ? ? ? ? ? a44h inch threshold port 10 vc1 completion 291h ? 749h ? ? ? ? ? a48h inch threshold port 11 vc0 posted 292h ? 74ah ? ? ? ? ? a4ch inch threshold port 11 vc0 non-posted 293h ? 74bh ? ? ? ? ? a50h inch threshold port 11 vc0 completion 294h ? 74ch ? ? ? ? ? a54h inch threshold port 11 vc1 posted 295h ? 74dh ? ? ? ? ? a58h inch threshold port 11 vc1 non-posted 296h ? 74eh ? ? ? ? ? a5ch inch threshold port 11 vc1 completion 297h ? 74fh ? ? ? ? ? b80h reserved 2e0h ? 798h ? ? ? ? ? b84h reserved 2e1h ? 799h ? ? ? ? ? b88h reserved 2e2h ? 79ah ? ? ? ? ? b98h reserved 2e6h ? 79eh ? ? ? ? ? b9ch reserved 2e7h ? 79fh ? ? ? ? ? be8h ingress one-bit ecc error count 2fah?7b2h????? bech plx-specific relaxed completion ordering (ingress) (silicon revisions bb/bc only) 2fbh ? 7b3h ? ? ? ? ? bfch plx-specific relaxed ordering mode (ingress) 2ffh ? 7b7h ? ? ? ? ? table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
514 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port /24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 serial eeprom memory map plx technology, inc. c00h itch vc&t threshold_1 300h ? 7b8h ? ? ? ? ? c04h itch vc&t threshold_2 301h ? 7b9h ? ? ? ? ? c08h itch vc&t threshold_3 302h ? 7bah ? ? ? ? ? c0ch reserved 303h ? 7bbh ? ? ? ? ? c10h reserved 304h ? 7bch ? ? ? ? ? c14h reserved 305h ? 7bdh ? ? ? ? ? c18h reserved 306h ? 7beh ? ? ? ? ? c1ch reserved 307h ? 7bfh ? ? ? ? ? c20h reserved 308h ? 7c0h ? ? ? ? ? c24h reserved 309h ? 7c1h ? ? ? ? ? c28h reserved 30ah ? 7c2h ? ? ? ? ? c2ch reserved 30bh ? 7c3h ? ? ? ? ? c30h reserved 30ch ? 7c4h ? ? ? ? ? c34h reserved 30dh ? 7c5h ? ? ? ? ? c38h reserved 30eh ? 7c6h ? ? ? ? ? c3ch memory bar2/3 address translation[31:0] ??????9efhae7h c40h memory bar2/3 address translation[63:32] ??????9f0hae8h c44h memory bar4/5 address translation[31:0] ??????9f1hae9h c48h memory bar4/5 address translation[63:32] ??????9f2haeah c4ch memory bar2/3 limit[31:0] ??????9f3haebh c50h memory bar2/3 limit[63:32] ??????9f4haech c54h memory bar4/5 limit[31:0] ??????9f5haedh c58h memory bar4/5 limit[63:32] ??????9f6haeeh c5ch lookup table entry 0 ? ? ? ? ? ? 9f7h aefh c60h lookup table entry 1 ? ? ? ? ? ? 9f8h af0h c64h lookup table entry 2 ? ? ? ? ? ? 9f9h af1h c68h lookup table entry 3 ? ? ? ? ? ? 9fah af2h c6ch lookup table entry 4 ? ? ? ? ? ? 9fbh af3h c70h lookup table entry 5 ? ? ? ? ? ? 9fch af4h c74h lookup table entry 6 ? ? ? ? ? ? 9fdh af5h table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 515 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 february, 2007 serial eeprom memory map c78h lookup table entry 7 ? ? ? ? ? ? 9feh af6h c7ch lookup table entry 8 ? ? ? ? ? ? 9ffh af7h c80h lookup table entry 9 ? ? ? ? ? ? a00h af8h c84h lookup table entry 10 ? ? ? ? ? ? a01h af9h c88h lookup table entry 11 ? ? ? ? ? ? a02h afah c8ch lookup table entry 12 ? ? ? ? ? ? a03h afbh c90h lookup table entry 13 ? ? ? ? ? ? a04h afch c94h lookup table entry 14 ? ? ? ? ? ? a05h afdh c98h lookup table entry 15 ? ? ? ? ? ? a06h afeh c9ch lookup table entry 16 ? ? ? ? ? ? a07h affh ca0h lookup table entry 17 ? ? ? ? ? ? a08h b00h ca4h lookup table entry 18 ? ? ? ? ? ? a09h b01h ca8h lookup table entry 19 ? ? ? ? ? ? a0ah b02h cach lookup table entry 20 ? ? ? ? ? ? a0bh b03h cb0h lookup table entry 21 ? ? ? ? ? ? a0ch b04h cb4h lookup table entry 22 ? ? ? ? ? ? a0dh b05h cb8h lookup table entry 23 ? ? ? ? ? ? a0eh b06h cbch lookup table entry 24 ? ? ? ? ? ? a0fh b07h cc0h lookup table entry 25 ? ? ? ? ? ? a10h b08h cc4h lookup table entry 26 ? ? ? ? ? ? a11h b09h cc8h lookup table entry 27 ? ? ? ? ? ? a12h b0ah ccch lookup table entry 28 ? ? ? ? ? ? a13h b0bh cd0h lookup table entry 29 ? ? ? ? ? ? a14h b0ch cd4h lookup table entry 30 ? ? ? ? ? ? a15h b0dh cd8h lookup table entry 31 ? ? ? ? ? ? a16h b0eh cdch lookup table entry 32 ? ? ? ? ? ? a17h b0fh ce0h lookup table entry 33 ? ? ? ? ? ? a18h b10h ce4h lookup table entry 34 ? ? ? ? ? ? a19h b11h ce8h lookup table entry 35 ? ? ? ? ? ? a1ah b12h cech lookup table entry 36 ? ? ? ? ? ? a1bh b13h table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
516 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port /24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 serial eeprom memory map plx technology, inc. cf0h lookup table entry 37 ? ? ? ? ? ? a1ch b14h cf4h lookup table entry 38 ? ? ? ? ? ? a1dh b15h cf8h lookup table entry 39 ? ? ? ? ? ? a1eh b16h cfch lookup table entry 40 ? ? ? ? ? ? a1fh b17h d00h lookup table entry 41 ? ? ? ? ? ? a20h b18h d04h lookup table entry 42 ? ? ? ? ? ? a21h b19h d08h lookup table entry 43 ? ? ? ? ? ? a22h b1ah d0ch lookup table entry 44 ? ? ? ? ? ? a23h b1bh d10h lookup table entry 45 ? ? ? ? ? ? a24h b1ch d14h lookup table entry 46 ? ? ? ? ? ? a25h b1dh d18h lookup table entry 47 ? ? ? ? ? ? a26h b1eh d1ch lookup table entry 48 ? ? ? ? ? ? a27h b1fh d20h lookup table entry 49 ? ? ? ? ? ? a28h b20h d24h lookup table entry 50 ? ? ? ? ? ? a29h b21h d28h lookup table entry 51 ? ? ? ? ? ? a2ah b22h d2ch lookup table entry 52 ? ? ? ? ? ? a2bh b23h d30h lookup table entry 53 ? ? ? ? ? ? a2ch b24h d34h lookup table entry 54 ? ? ? ? ? ? a2dh b25h d38h lookup table entry 55 ? ? ? ? ? ? a2eh b26h d3ch lookup table entry 56 ? ? ? ? ? ? a2fh b27h d40h lookup table entry 57 ? ? ? ? ? ? a30h b28h d44h lookup table entry 58 ? ? ? ? ? ? a31h b29h d48h lookup table entry 59 ? ? ? ? ? ? a32h b2ah d4ch lookup table entry 60 ? ? ? ? ? ? a33h b2bh d50h lookup table entry 61 ? ? ? ? ? ? a34h b2ch d54h lookup table entry 62 ? ? ? ? ? ? a35h b2dh d58h lookup table entry 63 ? ? ? ? ? ? a36h b2eh d5ch nt link interface vc0 resource control ??????a37hb2fh d60h nt link interface vc1 resource control ? ? ? ? ? ? a38h b30h d64h nt link interface vc capability 1 ? ? ? ? ? ? a39h b31h table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 517 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 february, 2007 serial eeprom memory map d68h bar0 = reserved (virtual) ? ? ? ? ? ? a3ah b32h d6ch bar1 (virtual) ? ? ? ? ? ? a3bh b33h d70h bar2 (virtual) ? ? ? ? ? ? a3ch b34h d74h bar3 (virtual) ? ? ? ? ? ? a3dh b35h d78h bar4 (virtual) ? ? ? ? ? ? a3eh b36h d7ch bar5 (virtual) ? ? ? ? ? ? a3fh b37h d80h bar1 setup ? ? ? ? ? ? a40h b38h d84h bar2 setup ? ? ? ? ? ? a41h b39h d88h bar3 setup ??????a42hb3ah d8ch bar4 setup ? ? ? ? ? ? a43h b3bh d90h bar5 setup ? ? ? ? ? ? a44h b3ch d94h requester id translati on lut entry 0 ? ? ? ? ? ? a45h b3dh d98h requester id translati on lut entry 1 ? ? ? ? ? ? a46h b3eh d9ch requester id translati on lut entry 2 ? ? ? ? ? ? a47h b3fh da0h requester id translati on lut entry 3 ? ? ? ? ? ? a48h b40h da4h requester id translati on lut entry 4 ? ? ? ? ? ? a49h b41h da8h requester id translati on lut entry 5 ? ? ? ? ? ? a4ah b42h dach requester id translati on lut entry 6 ? ? ? ? ? ? a4bh b43h db0h requester id translati on lut entry 7 ? ? ? ? ? ? a4ch b44h db4h requester id translati on lut entry 0_1 ? ? ? ? ? ? a4dh b45h db8h requester id translati on lut entry 2_3 ? ? ? ? ? ? a4eh b46h dbch requester id translati on lut entry 4_5 ? ? ? ? ? ? a4fh b47h dc0h requester id translati on lut entry 6_7 ? ? ? ? ? ? a50h b48h dc4h requester id translati on lut entry 8_9 ? ? ? ? ? ? a51h b49h dc8h requester id translati on lut entry 10_11 ? ? ? ? ? ? a52h b4ah dcch requester id translati on lut entry 12_13 ? ? ? ? ? ? a53h b4bh dd0h requester id translati on lut entry 14_15 ? ? ? ? ? ? a54h b4ch dd4h requester id translati on lut entry 16_17 ? ? ? ? ? ? a55h b4dh dd8h requester id translati on lut entry 18_19 ? ? ? ? ? ? a56h b4eh ddch requester id translati on lut entry 20_21 ? ? ? ? ? ? a57h b4fh table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
518 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port /24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 serial eeprom memory map plx technology, inc. de0h requester id translati on lut entry 22_23 ? ? ? ? ? ? a58h b50h de4h requester id translati on lut entry 24_25 ? ? ? ? ? ? a59h b51h de8h requester id translati on lut entry 26_27 ? ? ? ? ? ? a5ah b52h dech requester id translati on lut entry 28_29 ? ? ? ? ? ? a5bh b53h df0h requester id translati on lut entry 30_31 ? ? ? ? ? ? a5ch b54h df4h nt port link interface capt ure bus and device number ???????b55h df8h nt port virtual interface control ???????b56h fb4h pci express enhanced capability header 30fh 399h 7c7h 851h 8dbh 965h a5dh b57h fb8h uncorrectable error status 310h 39ah 7c8h 852h 8dch 966h a5eh b58h fbch uncorrectable error mask 311h 39bh 7c9h 853h 8ddh 967h a5fh b59h fc0h uncorrectable error severity 312h 39ch 7cah 854h 8deh 968h a60h b5ah fc4h correctable error status 313h 39dh 7cbh 855h 8dfh 969h a61h b5bh fc8h correctable error mask 314h 39eh 7cch 856h 8e0h 96ah a62h b5ch fcch advanced error capabi lities and control 315h 39fh 7cdh 857h 8e1h 96bh a63h b5dh fd0h header log_0 316h 3a0h 7ceh 858h 8e2h 96ch a64h b5eh fd4h header log_1 317h 3a1h 7cfh 859h 8e3h 96dh a65h b5fh fd8h header log_2 318h 3a2h 7d0h 85ah 8e4h 96eh a66h b60h fdch header log_3 319h 3a3h 7d1h 85bh 8e5h 96fh a67h b61h n/a crc value be4h table a-1. pex 8524v and pex 8524 serial eeprom memory map (cont.) register offset register name port register loaded from listed serial eeprom address non-transparent ports station 0 station 1 port 0 port 1 port 8 port 9 port 10 port 11 link virtual
expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-port/2 4-lane versatile pci express switch data book 519 copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 appendix b general information b.1 product ordering information contact your local plx sales representative for ordering information. table b-1. pex 8524vbb/bc 680-ball pbga product orderi ng information part numbers description PEX8524-BB25VBI pex 8524vbb 6-port, 24-lane pci expre ss switch plastic bga pack age (680-ball, 35 x 35 mm) PEX8524-BB25VBI g pex 8524vbb 6-port, 24-lane pci express switch plastic bga package (680-ball, 35 x 35 mm), lead-free rohs green package pex8524-bc25vbi pex 8524vbc 6-port, 24-lane pci expre ss switch plastic bga pack age (680-ball, 35 x 35 mm) pex8524-bc25vbi g pex 8524vbc 6-port, 24-lane pci express switch plastic bga package (680-ball, 35 x 35 mm), lead-free rohs green package pex 8524- bc25v b i g g ? lead-free, rohs compliant, fully green i ? industrial temperature b ? plastic ball grid array package v ? 35 x 35 mm package bb or bc ? silicon revision 25 ? signaling rate (2.5 gbps) 8524 ? part number pex ? pci express product family pex 8524vrdk-1 rdk pex 8524vbc (35 x 35 mm) rapid developm ent kit with x16 edge connector and x1 adapter pex 8524vrdk-4 rdk pex 8524vbc (35 x 35 mm) rapid developm ent kit with x16 edge connector and x4 adapter pex 8524vrdk-8 rdk pex 8524vbc (35 x 35 mm) rapid developm ent kit with x16 edge connector and x8 adapter
general information plx technology, inc. 520 expresslane pex 8524vaa/bb/bc and pex 8524bb/bc 6-po rt/24-lane versatile pci express switch data book copyright ? 2007 by plx technology, inc. all rights reserved ? version 1.5 b.2 united states and international representatives, and distributors plx technology, inc., representative s and distributors are listed at www.plxtech.com . b.3 technical support plx technology, inc., technical support information is listed at www.plxtech.com/support/ , or call 800 759-3735 (domestic only) or 408 774-9060. table b-2. pex 8524bb/bc 644-ball pbga product ordering information part numbers description pex8524-bb25bi pex 8524bb 6-port, 24-lane pci express switch plastic bga package (644- ball, 31 x 31 mm) pex8524-bb25bi g pex 8524bb 6-port, 24-lane pci express switch plastic bga package (644-ball, 31 x 31 mm), lead-free rohs green package pex8524-bc25bi pex 8524bc 6-port, 24-lane pci express switch plastic bga package (644- ball, 31 x 31 mm) pex8524-bc25bi g pex 8524bc 6-port, 24-lane pci express switch plastic bga package (644-ball, 31 x 31 mm), lead-free rohs green package pex8524 - bc25 b i g g ? lead-free, rohs compliant, fully green i ? industrial temperature b ? plastic ball grid array package bb or bc ? silicon revision 25 ? signaling rate (2.5 gbps) 8524 ? part number pex ? pci express product family pex 8524-bb rdk pex 8524bb (31 x 31mm) rapid development kit with x8 edge connector pex 8524-bc rdk pex 8524bc (31 x 31mm) rapid development kit with x8 edge connector x1 adapter pci express x16 to x1 adapter x4 adapter pci express x16 to x4 adapter

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